This document discusses network-on-chip (NoC) architectures for multiprocessor systems-on-chip. It describes how NoCs use routers and wires to connect hundreds or thousands of processor cores. The document outlines the different layers of a typical NoC architecture, including the application, transport, network, data link and physical layers. It also discusses common NoC router architectures and design methodologies, and introduces a bidirectional NoC architecture that aims to improve bandwidth utilization.

1. Network on Chip
Structure and Design Methodologies1

2. • Introduction
• Network-on-Chip Architecture and Function Layers
• Network-on-Chip Design Methodologies
• Bidirectional Network-on-Chip (BiNoC)
Architecture
• Conclusion
2
Content

3. •The next generation of multiprocessor system on
chip (MPSoC) and chip multiprocessors (CMPs)
will contain hundreds or thousands of cores.
Such a many-core system requires high-
performance interconnections to transfer data
among the cores on the chip.
3
Abstract

4. •As the density of VLSI design increases, the
complexity of each component in a system
raises rapidly.
•Today’s SoC designers face a new challenge
in the design of the on-chip interconnects
beyond the evolution of an increasing
number of processing elements
4
Introduction

5. Why we need of it ?..
• Power efficient processors combined with hardware
accelerators are the preferred choice for most
designers to deliver the best trade off between
performance and power consumption.
• Hoc methods of selecting few blocks may work based
on a designer’s experience, this may not work as
today’s MPSoC and CMP designs which becomes more
and more complex.
5
Content

6. Network-on-Chip Architecture and Function Layers
•A typical NoC architecture consists of
multiple segments of wires and routers.
•The NoC function can be classified into
several layers: application, transport,
network, data link, and physical layers.
6

7. NI-Network Interface R-Routers
7
Typical NoC architecture in a mesh topology.

8. • Application Layer: At the application layer, target applications will
be broken down into a set of computation.
• Transport Layer: Prevent buffer overflow and avoid traffic
congestion.
• Network Layer: Deal with the routing data between processing
elements.
• Data Link: Increase the reliability of the link up to a minimum
required level.
• Physical Layers: Transfer the data from node to node.
8
Network-on-Chip Function Layers

9. 9
Typical NoC Router Architecture

10. 10
Network-on-Chip Design Methodologies

11. • Problem Description: Waist of Bandwidth
• Example: 2*2 Two-Dimensional Mesh NOC
11
Bidirectional Network-on-Chip (BiNoC) Architecture

12. • Channel Bandwidth Utilization:
• Bandwidth Utilization Analysis of a conventional NOC router
• NOC with Virtual Channel Control
12
Bidirectional Network-on-Chip (BiNoC) Architecture Cont.

13. • NoC (BiNoC) backbone architecture, which can be
easily integrated into most conventional NoC designs
and successfully improve the NoC performance with a
reasonable cost.
13
Conclusion

14. • Hindawi Publishing Corporation
Journal of Electrical and Computer Engineering
Volume 2012, Article ID 509465
14
Reference

15. THANK’S
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