This document describes a study that designed and analyzed the performance of an 8x8 network-on-chip router. The researchers implemented a 2D mesh network-on-chip router with four ports connected in each of the four directions (north, south, east, west) and a fifth port connected to a local processing element. The goal was to improve quality-of-service by employing algorithms like wormhole routing, arbitration, and crossbar switching. The router architecture and modules were designed and synthesized using Xilinx ISE to optimize for lower power consumption while maintaining high throughput and quality-of-service.
This document discusses mapping networks onto a hybrid Network-on-Chip (NoC) architecture that integrates packet switching, circuit switching, and virtual circuit switching. It reviews prior work on mapping applications onto NoC architectures to optimize performance, energy consumption, and latency. The paper proposes a hybrid scheme to map cores and communications onto different switching mechanisms in the NoC to balance latency, flexibility, and efficiency.
A LIGHT WEIGHT VLSI FRAME WORK FOR HIGHT CIPHER ON FPGAIRJET Journal
This document discusses the implementation of a lightweight VLSI design for the HIGHT cipher on an FPGA. It begins with an introduction to lightweight VLSI architecture and its applications in low-resource devices. It then provides background on the HIGHT cipher and discusses prior work implementing cryptographic algorithms on FPGAs. The document goes on to describe the proposed VLSI design for the HIGHT cipher, which is optimized for size, power, and speed. It achieves a throughput of 25 Mbps with an encryption/decryption delay of 0.64 ms. Evaluation results demonstrate the effectiveness and suitability of the design for low-power applications.
FPGA IMPLEMENTATION OF PRIORITYARBITER BASED ROUTER DESIGN FOR NOC SYSTEMSIAEME Publication
An efficient Priority-Arbiter based Router is designed along with 2X2 and 3X3 mesh
topology based NOC architecture are designed. The Priority –Arbiter based Router
design includes Input registers, Priority arbiter, and XY- Routing algorithm. The
Priority-Arbiter based Router and NOC 2X2 and 3X3 Router designs are synthesized
and implemented using Xilinx ISE Tool and simulated using Modelsim6.5f. The
implementation is done by Artix-7 FPGA device, and the physically debugging of the
NOC 2X2 Router design is verified using Chipscope pro tool. The performance results
are analyzed in terms of the Area (Slices, LUT’s), Timing period, and Maximum
operating frequency. The comparison of the Priority-Arbiter based Router is made
concerning previous similar architecture with improvements.
FPGA IMPLEMENTATION OF PRIORITYARBITER BASED ROUTER DESIGN FOR NOC SYSTEMSIAEME Publication
An efficient Priority-Arbiter based Router is designed along with 2X2 and 3X3 mesh
topology based NOC architecture are designed. The Priority –Arbiter based Router
design includes Input registers, Priority arbiter, and XY- Routing algorithm. The
Priority-Arbiter based Router and NOC 2X2 and 3X3 Router designs are synthesized
and implemented using Xilinx ISE Tool and simulated using Modelsim6.5f. The
implementation is done by Artix-7 FPGA device, and the physically debugging of the
NOC 2X2 Router design is verified using Chipscope pro tool. The performance results
are analyzed in terms of the Area (Slices, LUT’s), Timing period, and Maximum
operating frequency. The comparison of the Priority-Arbiter based Router is made
concerning previous similar architecture with improvements.
Many intellectual property (IP) modules are present in contemporary system on chips (SoCs). This could provide an issue with interconnection among different IP modules, which would limit the system's ability to scale. Traditional bus-based SoC architectures have a connectivity bottleneck, and network on chip (NoC) has evolved as an embedded switching network to address this issue. The interconnections between various cores or IP modules on a chip have a significant impact on communication and chip performance in terms of power, area latency and throughput. Also, designing a reliable fault tolerant NoC became a significant concern. In fault tolerant NoC it becomes critical to identify faulty node and dynamically reroute the packets keeping minimum latency. This study provides an insight into a domain of NoC, with intention of understanding fault tolerant approach based on the XY routing algorithm for 4×4 mesh architecture. The fault tolerant NoC design is synthesized on field programmable gate array (FPGA).
IRJET- Sink Mobility based Energy Efficient Routing Protocol for Wireless Sen...IRJET Journal
The document describes a proposed sink mobility based energy efficient routing protocol for wireless sensor networks. The protocol uses both a static centralized sink and a mobile sink that follows a predetermined path with 4 sojourn locations. This is aimed to improve network lifetime by balancing energy load across nodes. Simulation results show that the proposed approach with a mobile sink performs better than the Threshold sensitive Energy Efficient sensor Network (TEEN) protocol alone in terms of number of alive nodes, number of cluster heads, and number of packets sent to the base station over multiple rounds. Using a mobile sink helps scatter the energy load in the network and extends lifetime compared to only using a static sink.
Network on Chip Architecture and Routing Techniques: A surveyIJRES Journal
This document summarizes research on Network on Chip (NOC) architecture and routing techniques. It discusses NOC topology options including mesh, torus, ring and irregular networks. It also reviews router architecture, switching techniques, virtual channels, buffering, error correction, quality of service implementations, and routing algorithms. Specific NOC implementations discussed include QNOC, Ethereal NOC, and SPIN NOC. The document provides an overview of research on improving performance and efficiency in NOC design.
IRJET- Investigation on Delay and Power Minimization in IEEE 802.15.4 Protoco...IRJET Journal
This document investigates delay and power minimization in the IEEE 802.15.4 protocol using the CSMA-CA algorithm. It analyzes the average delay and power of the Zigbee protocol with and without considering maximum retry limits. Theoretical calculations show that the average delay and power of the Zigbee protocol without maximum retry limits is greater than when maximum retry limits are considered. This is because without maximum retry limits, packets can be retransmitted indefinitely, leading to higher delays and power consumption. The analysis provides insights into optimizing the Zigbee protocol to improve quality of service parameters like delay and power usage.
This document discusses mapping networks onto a hybrid Network-on-Chip (NoC) architecture that integrates packet switching, circuit switching, and virtual circuit switching. It reviews prior work on mapping applications onto NoC architectures to optimize performance, energy consumption, and latency. The paper proposes a hybrid scheme to map cores and communications onto different switching mechanisms in the NoC to balance latency, flexibility, and efficiency.
A LIGHT WEIGHT VLSI FRAME WORK FOR HIGHT CIPHER ON FPGAIRJET Journal
This document discusses the implementation of a lightweight VLSI design for the HIGHT cipher on an FPGA. It begins with an introduction to lightweight VLSI architecture and its applications in low-resource devices. It then provides background on the HIGHT cipher and discusses prior work implementing cryptographic algorithms on FPGAs. The document goes on to describe the proposed VLSI design for the HIGHT cipher, which is optimized for size, power, and speed. It achieves a throughput of 25 Mbps with an encryption/decryption delay of 0.64 ms. Evaluation results demonstrate the effectiveness and suitability of the design for low-power applications.
FPGA IMPLEMENTATION OF PRIORITYARBITER BASED ROUTER DESIGN FOR NOC SYSTEMSIAEME Publication
An efficient Priority-Arbiter based Router is designed along with 2X2 and 3X3 mesh
topology based NOC architecture are designed. The Priority –Arbiter based Router
design includes Input registers, Priority arbiter, and XY- Routing algorithm. The
Priority-Arbiter based Router and NOC 2X2 and 3X3 Router designs are synthesized
and implemented using Xilinx ISE Tool and simulated using Modelsim6.5f. The
implementation is done by Artix-7 FPGA device, and the physically debugging of the
NOC 2X2 Router design is verified using Chipscope pro tool. The performance results
are analyzed in terms of the Area (Slices, LUT’s), Timing period, and Maximum
operating frequency. The comparison of the Priority-Arbiter based Router is made
concerning previous similar architecture with improvements.
FPGA IMPLEMENTATION OF PRIORITYARBITER BASED ROUTER DESIGN FOR NOC SYSTEMSIAEME Publication
An efficient Priority-Arbiter based Router is designed along with 2X2 and 3X3 mesh
topology based NOC architecture are designed. The Priority –Arbiter based Router
design includes Input registers, Priority arbiter, and XY- Routing algorithm. The
Priority-Arbiter based Router and NOC 2X2 and 3X3 Router designs are synthesized
and implemented using Xilinx ISE Tool and simulated using Modelsim6.5f. The
implementation is done by Artix-7 FPGA device, and the physically debugging of the
NOC 2X2 Router design is verified using Chipscope pro tool. The performance results
are analyzed in terms of the Area (Slices, LUT’s), Timing period, and Maximum
operating frequency. The comparison of the Priority-Arbiter based Router is made
concerning previous similar architecture with improvements.
Many intellectual property (IP) modules are present in contemporary system on chips (SoCs). This could provide an issue with interconnection among different IP modules, which would limit the system's ability to scale. Traditional bus-based SoC architectures have a connectivity bottleneck, and network on chip (NoC) has evolved as an embedded switching network to address this issue. The interconnections between various cores or IP modules on a chip have a significant impact on communication and chip performance in terms of power, area latency and throughput. Also, designing a reliable fault tolerant NoC became a significant concern. In fault tolerant NoC it becomes critical to identify faulty node and dynamically reroute the packets keeping minimum latency. This study provides an insight into a domain of NoC, with intention of understanding fault tolerant approach based on the XY routing algorithm for 4×4 mesh architecture. The fault tolerant NoC design is synthesized on field programmable gate array (FPGA).
IRJET- Sink Mobility based Energy Efficient Routing Protocol for Wireless Sen...IRJET Journal
The document describes a proposed sink mobility based energy efficient routing protocol for wireless sensor networks. The protocol uses both a static centralized sink and a mobile sink that follows a predetermined path with 4 sojourn locations. This is aimed to improve network lifetime by balancing energy load across nodes. Simulation results show that the proposed approach with a mobile sink performs better than the Threshold sensitive Energy Efficient sensor Network (TEEN) protocol alone in terms of number of alive nodes, number of cluster heads, and number of packets sent to the base station over multiple rounds. Using a mobile sink helps scatter the energy load in the network and extends lifetime compared to only using a static sink.
Network on Chip Architecture and Routing Techniques: A surveyIJRES Journal
This document summarizes research on Network on Chip (NOC) architecture and routing techniques. It discusses NOC topology options including mesh, torus, ring and irregular networks. It also reviews router architecture, switching techniques, virtual channels, buffering, error correction, quality of service implementations, and routing algorithms. Specific NOC implementations discussed include QNOC, Ethereal NOC, and SPIN NOC. The document provides an overview of research on improving performance and efficiency in NOC design.
IRJET- Investigation on Delay and Power Minimization in IEEE 802.15.4 Protoco...IRJET Journal
This document investigates delay and power minimization in the IEEE 802.15.4 protocol using the CSMA-CA algorithm. It analyzes the average delay and power of the Zigbee protocol with and without considering maximum retry limits. Theoretical calculations show that the average delay and power of the Zigbee protocol without maximum retry limits is greater than when maximum retry limits are considered. This is because without maximum retry limits, packets can be retransmitted indefinitely, leading to higher delays and power consumption. The analysis provides insights into optimizing the Zigbee protocol to improve quality of service parameters like delay and power usage.
Design and Implementation of JPEG CODEC using NoCIRJET Journal
This document describes the design and implementation of a JPEG codec using a Network-on-Chip (NoC) structure. It aims to speed up the image transfer process and provide shorter processing times. The key steps are:
1. The JPEG encoding process includes color space conversion, downsampling, block division, discrete cosine transform, quantization, and entropy coding to compress the image.
2. A NoC is used to transmit the compressed image data packets across the chip to reduce latency during transfer.
3. The JPEG decoding process reverses the encoding steps through entropy decoding, dequantization, inverse discrete cosine transform, and image reconstruction to decompress the image for viewing.
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
IRJET- DOE to Minimize the Energy Consumption of RPL Routing Protocol in IoT ...IRJET Journal
This document discusses minimizing the energy consumption of the RPL routing protocol in IoT networks to support green wireless communication. It first uses the Taguchi method to determine that network size is the most influential factor on energy consumption. It then simulates RPL under different network sizes (10-50 nodes) and mobility scenarios. The results show that energy consumption decreases by 22.11% and throughput increases by 2.82% for smaller networks compared to larger networks. Therefore, optimizing network size can help reduce energy usage and carbon footprint to achieve more sustainable green wireless communication.
EFFICIENT APPROACH FOR DESIGNING A PROTOCOL FOR IMPROVING THE CAPACITY OF ADH...IJCI JOURNAL
In Adhoc Network, prime issues which affects the deployment, design and performance of an Adhoc
Wireless System are Routing, MAC Scheme, TCP, Multicasting, Energy management, Pricing Scheme &
self-organization, Security & Deployment consideration. Routing protocols are designed in such a way that
it should have improvement of throughput and minimum loss of packets. Another aspect is efficient
management of energy and the requirement of protracted connectivity of the network. The routing
algorithm designed for this network should monitor the energy of the node and route the packet
accordingly. Adhoc Network in general has many limitations such as bandwidth, memory and
computational power. In Adhoc Network there are frequent path break due to mobility. Also time
synchronization is difficult & consumes more Bandwidth. Bandwidth reservations requires complex
Medium Access Control protocol. In this field the work of quantitative and qualitative metrics analysis has
been done. The analysis of protocol performance for improving the capacity of adhoc network using
probabilistic approaches of the network is yet to be proposed. Our probabilistic approach will cover
analysis of various computational parameters for different mobility structures. In our proposed method we
have distributed mobile nodes using Pareto distribution & formulated various energy models using
regression statistic.
S3 Infotech provides summaries of 10 VLSI projects related to low-power logic circuits, level shifters, adder architectures, optical counters, modular multiplication, transaction IDs, modulo adders, DACs, median filters, and quantum-dot SRAM. The projects explore techniques like spin-based devices, dynamic voltage scaling, pipelining, and cellular automata to improve efficiency, throughput, power consumption, and process variability tolerance in VLSI design.
1) A router and 2x2 mesh and torus topologies for a Network on Chip (NoC) were designed using Verilog and implemented on a Spartan 3E FPGA.
2) The router utilized only 2% of the FPGA slices, while a previously reported router used 3.16% of slices.
3) Simulations showed the designed router and 2x2 NoC topologies functioned correctly.
Servant-ModLeach Energy Efficient Cluster Base Routing Protocol for Large Sca...IRJET Journal
The document proposes a new routing protocol called Servant-MODLEACH (S-MODLEACH) to address some challenges in the MODLEACH protocol for wireless sensor networks. S-MODLEACH introduces servant nodes that are responsible for data aggregation to reduce the workload on cluster heads. It also selects cluster heads based on residual energy rather than probability, allowing nodes with higher energy to serve as cluster heads for longer. Simulation results showed S-MODLEACH performs better than MODLEACH in terms of throughput, energy conservation, and extending network lifetime.
Review on optimized area,delay and power efficient carry select adder using n...IRJET Journal
This document discusses optimized area, delay, and power efficient carry select adders using NAND gates. Carry select adders are commonly used fast adders but require more area due to using two ripple carry adders and a multiplexer. The proposed design aims to significantly reduce area, power, and redundant logic in carry select adders by developing a new logic formulation technique using only NAND gates. NAND gates have advantages including lower delay than NOR gates, easier fabrication, and better power performance. The design aims to optimize area, delay, and power over conventional carry select adder designs.
The router is a network device that is used to connect subnetwork and packet-switched networking by directing the data packets to the intended IP addresses. It succeeds the traffic between different systems and allows several devices to share the internet connection. The router is applicable for the effective commutation in system on chip (SoC) modules for network on chip (NoC) communication. The research paper emphasizes the design of the two dimensional (2D) router hardware chip in the Xilinx integrated system environment (ISE) 14.7 software and further logic verification using the data packets transmitted from all input/output ports. The design evaluation is done based on the pre-synthesis device utilization summary relating to different field programmable gate array (FPGA) boards such as Spartan-3E (XC3S500E), Spartan-6 (XC6SLX45), Virtex-4 (XC4VFX12), Virtex-5 (XC5VSX50T), and Virtex-7 (XC7VX550T). The 64-bit data logic is verified on the different ports of the router configuration in the Xilinx and Modelsim waveform simulator. The Virtex-7 has proven the fast-switching speed and optimal hardware parameters in comparison to other FPGAs.
This document summarizes a research paper that proposes a new protocol called E2EEST to estimate end-to-end delays in 802.11 ad hoc networks. It first discusses related work on QoS and delay estimation techniques. It then describes the authors' contributions, including using an available bandwidth estimation protocol called ABE to estimate available bandwidth, which the delay estimation depends on. The paper develops mathematical expressions to model nodes and estimate collision probability and delay. It presents the E2EEST protocol and simulations showing it provides lower delay, higher success rate and better QoS than other approaches.
Low power network on chip architectures: A surveyCSITiaesprime
Mostly communication now days is done through system on chip (SoC) models so, network on chip (NoC) architecture is most appropriate solution for better performance. However, one of major flaws in this architecture is power consumption. To gain high performance through this type of architecture it is necessary to confirm power consumption while designing this. Use of power should be diminished in every region of network chip architecture. Lasting power consumption can be lessened by reaching alterations in network routers and other devices used to form that network. This research mainly focusses on state-of-the-art methods for designing NoC architecture and techniques to reduce power consumption in those architectures like, network architecture, network links between nodes, network design, and routers.
Regular clocking scheme based design of cost-efficient comparator in QCAnooriasukmaningtyas
Quantum-dot cellular automata (QCA) gained a notable attraction in the emerging nanotechnology to get the better of power consumption, density, nano-scale design, the performance of the present CMOS technology. Many designs had been proposed in QCA for an arithmetic circuit like adder, divider, parity checker and comparator etc. Most of the designs have been facing the challenges of cost efficiency, power dissi-pation, device density etc. However, consideration of design automation, underlying clocking layout and integration of the sub modules are the most important which has a direct impact on the fabrication of the design. This work proposed a novel cost ef-fective and power aware comparator design, which is an essential segment in central processing unit (CPU). The noticeable novelty of the design was the use of underlying regular clocking scheme. A new scalable, regular clocking scheme has been utilized in the coplanar design of the comparator which enables regular or uniform cell layout of QCA circuit. It also exhibited the significant improvement over existing counterparts having irregular clocking in terms of area and latency. QCADesigner was used to test and verify the functionality of the circuit and by using QCAPro the power dissipation has been analyzed.
OPTIMIZED ROUTING AND DENIAL OF SERVICE FOR ROBUST TRANSMISSION IN WIRELESS N...IRJET Journal
This document proposes a system to optimize routing and prevent denial of service attacks in wireless networks. It aims to detect distributed denial of service (DDoS) attacks using a classifier system called CS_DDoS that classifies packets as malicious or normal. Malicious packets will be blocked and their IP addresses blacklisted. It also aims to use a hybrid optimization system (HOS) for efficient, quality routing to increase network lifetime and user communication. The system is designed to differentiate between genuine and malicious traffic, transfer data via alternative paths if attacks are detected, and balance network load for stable data transfer while improving packet delivery and throughput.
IRJET- Re-Configuration Topology for On-Chip Networks by Back-TrackingIRJET Journal
1) A novel reconfigurable network-on-chip architecture is proposed that allows for self-adaptive application-specific topologies to be implemented with backtracking to ensure throughput.
2) The architecture supports multiple applications by reconfiguring its topology according to the topology that best matches the input application and also supports a deadlock-free dynamic routing scheme.
3) Reconfigurability is achieved by changing the inter-switch connections according to a predefined configuration for the application. Backtracking is used to handle blockages and support deadlock-free routing through an efficient switch design.
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
A Survey on System-On-Chip Bus ProtocolsIRJET Journal
This document provides an overview of various on-chip bus protocols used in system-on-chips (SoCs) for communication between devices, including Inter-Integrated Circuit (I2C), Improved Inter-Integrated Circuit (I3C), Serial Peripheral Interface (SPI), Universal Asynchronous Receiver/Transmitter (UART), and Peripheral Component Interconnect Express (PCIe). It discusses the implementation and applications of these bus protocols, as well as enhancements like I3C that improve upon I2C. The document also reviews related work analyzing the implementation and comparison of bus protocols like I2C and SPI.
This document presents a VHDL-based cycle accurate register transfer level model for evaluating the dynamic area and leakage power consumption of dynamically self-reconfigurable BiNoC (bidirectional network on chip) architectures. The design is parameterized for factors like packet size, link properties, number/depth of virtual channels, and switching technique. The architecture and characterization of BiNoC components are discussed in detail. The values are integrated into the VHDL model to build a cycle accurate performance model. The goal is to implement a parameterized register transfer level design of BiNoC architecture elements to evaluate dynamic area and leakage power consumption.
IRJET- AODV and DSR Routing Protocol Performance Comparison in MANET using Ne...IRJET Journal
This document compares the performance of two mobile ad hoc network (MANET) routing protocols: Ad hoc On-Demand Distance Vector (AODV) and Dynamic Source Routing (DSR). The protocols were evaluated using the Network Simulator 2 (NS2) across three simulation scenarios with varying time durations. The results showed that AODV had lower initial packet loss compared to DSR. However, at longer simulation times both protocols performed similarly with comparable packet delivery ratios. In conclusion, AODV is more suitable when the MANET needs to be established quickly, while both protocols can be used for longer-term MANETs as their performance converges over time.
IRJET- A Study on Hierarchical Cluster based Routing Techniques in Wireless S...IRJET Journal
This document provides a summary of a study on hierarchical cluster-based routing techniques in wireless sensor networks. It begins with an abstract that outlines the paper's focus on energy conservation in WSNs and surveying cluster-based routing protocols. The document then covers non-clustered and clustered WSN network structures, characteristics and design considerations of WSNs, categories of routing protocols (proactive, reactive, hybrid), and classifications of hierarchical cluster-based routing protocols including LEACH, LEACH-C, HEED, and DEEC. The overall purpose is to analyze various cluster-based routing techniques and their ability to minimize energy consumption and maximize network lifetime in WSNs.
This document outlines a research proposal on developing a congestion-aware adaptive routing protocol for an on-chip network. The objectives are to minimize congestion and enhance network performance by dynamically adjusting routing paths based on real-time network conditions. The proposal will involve implementing a congestion-aware adaptive routing algorithm using Verilog, gathering performance data from conventional and proposed algorithms, and analyzing results to optimize the routing protocol and network structure. The desired outcome is to improve latency and throughput in the on-chip network at low cost by exploiting adaptive routing.
TUNNELING IN HIMALAYAS WITH NATM METHOD: A SPECIAL REFERENCES TO SUNGAL TUNNE...IRJET Journal
1) The document discusses the Sungal Tunnel project in Jammu and Kashmir, India, which is being constructed using the New Austrian Tunneling Method (NATM).
2) NATM involves continuous monitoring during construction to adapt to changing ground conditions, and makes extensive use of shotcrete for temporary tunnel support.
3) The methodology section outlines the systematic geotechnical design process for tunnels according to Austrian guidelines, and describes the various steps of NATM tunnel construction including initial and secondary tunnel support.
STUDY THE EFFECT OF RESPONSE REDUCTION FACTOR ON RC FRAMED STRUCTUREIRJET Journal
This study examines the effect of response reduction factors (R factors) on reinforced concrete (RC) framed structures through nonlinear dynamic analysis. Three RC frame models with varying heights (4, 8, and 12 stories) were analyzed in ETABS software under different R factors ranging from 1 to 5. The results showed that displacement increased as the R factor decreased, indicating less linear behavior for lower R factors. Drift also decreased proportionally with increasing R factors from 1 to 5. Shear forces in the frames decreased with higher R factors. In general, R factors of 3 to 5 produced more satisfactory performance with less displacement and drift. The displacement variations between different building heights were consistent at different R factors. This study evaluated how R factors influence
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Design and Implementation of JPEG CODEC using NoCIRJET Journal
This document describes the design and implementation of a JPEG codec using a Network-on-Chip (NoC) structure. It aims to speed up the image transfer process and provide shorter processing times. The key steps are:
1. The JPEG encoding process includes color space conversion, downsampling, block division, discrete cosine transform, quantization, and entropy coding to compress the image.
2. A NoC is used to transmit the compressed image data packets across the chip to reduce latency during transfer.
3. The JPEG decoding process reverses the encoding steps through entropy decoding, dequantization, inverse discrete cosine transform, and image reconstruction to decompress the image for viewing.
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
IRJET- DOE to Minimize the Energy Consumption of RPL Routing Protocol in IoT ...IRJET Journal
This document discusses minimizing the energy consumption of the RPL routing protocol in IoT networks to support green wireless communication. It first uses the Taguchi method to determine that network size is the most influential factor on energy consumption. It then simulates RPL under different network sizes (10-50 nodes) and mobility scenarios. The results show that energy consumption decreases by 22.11% and throughput increases by 2.82% for smaller networks compared to larger networks. Therefore, optimizing network size can help reduce energy usage and carbon footprint to achieve more sustainable green wireless communication.
EFFICIENT APPROACH FOR DESIGNING A PROTOCOL FOR IMPROVING THE CAPACITY OF ADH...IJCI JOURNAL
In Adhoc Network, prime issues which affects the deployment, design and performance of an Adhoc
Wireless System are Routing, MAC Scheme, TCP, Multicasting, Energy management, Pricing Scheme &
self-organization, Security & Deployment consideration. Routing protocols are designed in such a way that
it should have improvement of throughput and minimum loss of packets. Another aspect is efficient
management of energy and the requirement of protracted connectivity of the network. The routing
algorithm designed for this network should monitor the energy of the node and route the packet
accordingly. Adhoc Network in general has many limitations such as bandwidth, memory and
computational power. In Adhoc Network there are frequent path break due to mobility. Also time
synchronization is difficult & consumes more Bandwidth. Bandwidth reservations requires complex
Medium Access Control protocol. In this field the work of quantitative and qualitative metrics analysis has
been done. The analysis of protocol performance for improving the capacity of adhoc network using
probabilistic approaches of the network is yet to be proposed. Our probabilistic approach will cover
analysis of various computational parameters for different mobility structures. In our proposed method we
have distributed mobile nodes using Pareto distribution & formulated various energy models using
regression statistic.
S3 Infotech provides summaries of 10 VLSI projects related to low-power logic circuits, level shifters, adder architectures, optical counters, modular multiplication, transaction IDs, modulo adders, DACs, median filters, and quantum-dot SRAM. The projects explore techniques like spin-based devices, dynamic voltage scaling, pipelining, and cellular automata to improve efficiency, throughput, power consumption, and process variability tolerance in VLSI design.
1) A router and 2x2 mesh and torus topologies for a Network on Chip (NoC) were designed using Verilog and implemented on a Spartan 3E FPGA.
2) The router utilized only 2% of the FPGA slices, while a previously reported router used 3.16% of slices.
3) Simulations showed the designed router and 2x2 NoC topologies functioned correctly.
Servant-ModLeach Energy Efficient Cluster Base Routing Protocol for Large Sca...IRJET Journal
The document proposes a new routing protocol called Servant-MODLEACH (S-MODLEACH) to address some challenges in the MODLEACH protocol for wireless sensor networks. S-MODLEACH introduces servant nodes that are responsible for data aggregation to reduce the workload on cluster heads. It also selects cluster heads based on residual energy rather than probability, allowing nodes with higher energy to serve as cluster heads for longer. Simulation results showed S-MODLEACH performs better than MODLEACH in terms of throughput, energy conservation, and extending network lifetime.
Review on optimized area,delay and power efficient carry select adder using n...IRJET Journal
This document discusses optimized area, delay, and power efficient carry select adders using NAND gates. Carry select adders are commonly used fast adders but require more area due to using two ripple carry adders and a multiplexer. The proposed design aims to significantly reduce area, power, and redundant logic in carry select adders by developing a new logic formulation technique using only NAND gates. NAND gates have advantages including lower delay than NOR gates, easier fabrication, and better power performance. The design aims to optimize area, delay, and power over conventional carry select adder designs.
The router is a network device that is used to connect subnetwork and packet-switched networking by directing the data packets to the intended IP addresses. It succeeds the traffic between different systems and allows several devices to share the internet connection. The router is applicable for the effective commutation in system on chip (SoC) modules for network on chip (NoC) communication. The research paper emphasizes the design of the two dimensional (2D) router hardware chip in the Xilinx integrated system environment (ISE) 14.7 software and further logic verification using the data packets transmitted from all input/output ports. The design evaluation is done based on the pre-synthesis device utilization summary relating to different field programmable gate array (FPGA) boards such as Spartan-3E (XC3S500E), Spartan-6 (XC6SLX45), Virtex-4 (XC4VFX12), Virtex-5 (XC5VSX50T), and Virtex-7 (XC7VX550T). The 64-bit data logic is verified on the different ports of the router configuration in the Xilinx and Modelsim waveform simulator. The Virtex-7 has proven the fast-switching speed and optimal hardware parameters in comparison to other FPGAs.
This document summarizes a research paper that proposes a new protocol called E2EEST to estimate end-to-end delays in 802.11 ad hoc networks. It first discusses related work on QoS and delay estimation techniques. It then describes the authors' contributions, including using an available bandwidth estimation protocol called ABE to estimate available bandwidth, which the delay estimation depends on. The paper develops mathematical expressions to model nodes and estimate collision probability and delay. It presents the E2EEST protocol and simulations showing it provides lower delay, higher success rate and better QoS than other approaches.
Low power network on chip architectures: A surveyCSITiaesprime
Mostly communication now days is done through system on chip (SoC) models so, network on chip (NoC) architecture is most appropriate solution for better performance. However, one of major flaws in this architecture is power consumption. To gain high performance through this type of architecture it is necessary to confirm power consumption while designing this. Use of power should be diminished in every region of network chip architecture. Lasting power consumption can be lessened by reaching alterations in network routers and other devices used to form that network. This research mainly focusses on state-of-the-art methods for designing NoC architecture and techniques to reduce power consumption in those architectures like, network architecture, network links between nodes, network design, and routers.
Regular clocking scheme based design of cost-efficient comparator in QCAnooriasukmaningtyas
Quantum-dot cellular automata (QCA) gained a notable attraction in the emerging nanotechnology to get the better of power consumption, density, nano-scale design, the performance of the present CMOS technology. Many designs had been proposed in QCA for an arithmetic circuit like adder, divider, parity checker and comparator etc. Most of the designs have been facing the challenges of cost efficiency, power dissi-pation, device density etc. However, consideration of design automation, underlying clocking layout and integration of the sub modules are the most important which has a direct impact on the fabrication of the design. This work proposed a novel cost ef-fective and power aware comparator design, which is an essential segment in central processing unit (CPU). The noticeable novelty of the design was the use of underlying regular clocking scheme. A new scalable, regular clocking scheme has been utilized in the coplanar design of the comparator which enables regular or uniform cell layout of QCA circuit. It also exhibited the significant improvement over existing counterparts having irregular clocking in terms of area and latency. QCADesigner was used to test and verify the functionality of the circuit and by using QCAPro the power dissipation has been analyzed.
OPTIMIZED ROUTING AND DENIAL OF SERVICE FOR ROBUST TRANSMISSION IN WIRELESS N...IRJET Journal
This document proposes a system to optimize routing and prevent denial of service attacks in wireless networks. It aims to detect distributed denial of service (DDoS) attacks using a classifier system called CS_DDoS that classifies packets as malicious or normal. Malicious packets will be blocked and their IP addresses blacklisted. It also aims to use a hybrid optimization system (HOS) for efficient, quality routing to increase network lifetime and user communication. The system is designed to differentiate between genuine and malicious traffic, transfer data via alternative paths if attacks are detected, and balance network load for stable data transfer while improving packet delivery and throughput.
IRJET- Re-Configuration Topology for On-Chip Networks by Back-TrackingIRJET Journal
1) A novel reconfigurable network-on-chip architecture is proposed that allows for self-adaptive application-specific topologies to be implemented with backtracking to ensure throughput.
2) The architecture supports multiple applications by reconfiguring its topology according to the topology that best matches the input application and also supports a deadlock-free dynamic routing scheme.
3) Reconfigurability is achieved by changing the inter-switch connections according to a predefined configuration for the application. Backtracking is used to handle blockages and support deadlock-free routing through an efficient switch design.
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
A Survey on System-On-Chip Bus ProtocolsIRJET Journal
This document provides an overview of various on-chip bus protocols used in system-on-chips (SoCs) for communication between devices, including Inter-Integrated Circuit (I2C), Improved Inter-Integrated Circuit (I3C), Serial Peripheral Interface (SPI), Universal Asynchronous Receiver/Transmitter (UART), and Peripheral Component Interconnect Express (PCIe). It discusses the implementation and applications of these bus protocols, as well as enhancements like I3C that improve upon I2C. The document also reviews related work analyzing the implementation and comparison of bus protocols like I2C and SPI.
This document presents a VHDL-based cycle accurate register transfer level model for evaluating the dynamic area and leakage power consumption of dynamically self-reconfigurable BiNoC (bidirectional network on chip) architectures. The design is parameterized for factors like packet size, link properties, number/depth of virtual channels, and switching technique. The architecture and characterization of BiNoC components are discussed in detail. The values are integrated into the VHDL model to build a cycle accurate performance model. The goal is to implement a parameterized register transfer level design of BiNoC architecture elements to evaluate dynamic area and leakage power consumption.
IRJET- AODV and DSR Routing Protocol Performance Comparison in MANET using Ne...IRJET Journal
This document compares the performance of two mobile ad hoc network (MANET) routing protocols: Ad hoc On-Demand Distance Vector (AODV) and Dynamic Source Routing (DSR). The protocols were evaluated using the Network Simulator 2 (NS2) across three simulation scenarios with varying time durations. The results showed that AODV had lower initial packet loss compared to DSR. However, at longer simulation times both protocols performed similarly with comparable packet delivery ratios. In conclusion, AODV is more suitable when the MANET needs to be established quickly, while both protocols can be used for longer-term MANETs as their performance converges over time.
IRJET- A Study on Hierarchical Cluster based Routing Techniques in Wireless S...IRJET Journal
This document provides a summary of a study on hierarchical cluster-based routing techniques in wireless sensor networks. It begins with an abstract that outlines the paper's focus on energy conservation in WSNs and surveying cluster-based routing protocols. The document then covers non-clustered and clustered WSN network structures, characteristics and design considerations of WSNs, categories of routing protocols (proactive, reactive, hybrid), and classifications of hierarchical cluster-based routing protocols including LEACH, LEACH-C, HEED, and DEEC. The overall purpose is to analyze various cluster-based routing techniques and their ability to minimize energy consumption and maximize network lifetime in WSNs.
This document outlines a research proposal on developing a congestion-aware adaptive routing protocol for an on-chip network. The objectives are to minimize congestion and enhance network performance by dynamically adjusting routing paths based on real-time network conditions. The proposal will involve implementing a congestion-aware adaptive routing algorithm using Verilog, gathering performance data from conventional and proposed algorithms, and analyzing results to optimize the routing protocol and network structure. The desired outcome is to improve latency and throughput in the on-chip network at low cost by exploiting adaptive routing.
Similar to Design and Performance Analysis of 8 x 8 Network on Chip Router (20)
TUNNELING IN HIMALAYAS WITH NATM METHOD: A SPECIAL REFERENCES TO SUNGAL TUNNE...IRJET Journal
1) The document discusses the Sungal Tunnel project in Jammu and Kashmir, India, which is being constructed using the New Austrian Tunneling Method (NATM).
2) NATM involves continuous monitoring during construction to adapt to changing ground conditions, and makes extensive use of shotcrete for temporary tunnel support.
3) The methodology section outlines the systematic geotechnical design process for tunnels according to Austrian guidelines, and describes the various steps of NATM tunnel construction including initial and secondary tunnel support.
STUDY THE EFFECT OF RESPONSE REDUCTION FACTOR ON RC FRAMED STRUCTUREIRJET Journal
This study examines the effect of response reduction factors (R factors) on reinforced concrete (RC) framed structures through nonlinear dynamic analysis. Three RC frame models with varying heights (4, 8, and 12 stories) were analyzed in ETABS software under different R factors ranging from 1 to 5. The results showed that displacement increased as the R factor decreased, indicating less linear behavior for lower R factors. Drift also decreased proportionally with increasing R factors from 1 to 5. Shear forces in the frames decreased with higher R factors. In general, R factors of 3 to 5 produced more satisfactory performance with less displacement and drift. The displacement variations between different building heights were consistent at different R factors. This study evaluated how R factors influence
A COMPARATIVE ANALYSIS OF RCC ELEMENT OF SLAB WITH STARK STEEL (HYSD STEEL) A...IRJET Journal
This study compares the use of Stark Steel and TMT Steel as reinforcement materials in a two-way reinforced concrete slab. Mechanical testing is conducted to determine the tensile strength, yield strength, and other properties of each material. A two-way slab design adhering to codes and standards is executed with both materials. The performance is analyzed in terms of deflection, stability under loads, and displacement. Cost analyses accounting for material, durability, maintenance, and life cycle costs are also conducted. The findings provide insights into the economic and structural implications of each material for reinforcement selection and recommendations on the most suitable material based on the analysis.
Effect of Camber and Angles of Attack on Airfoil CharacteristicsIRJET Journal
This document discusses a study analyzing the effect of camber, position of camber, and angle of attack on the aerodynamic characteristics of airfoils. Sixteen modified asymmetric NACA airfoils were analyzed using computational fluid dynamics (CFD) by varying the camber, camber position, and angle of attack. The results showed the relationship between these parameters and the lift coefficient, drag coefficient, and lift to drag ratio. This provides insight into how changes in airfoil geometry impact aerodynamic performance.
A Review on the Progress and Challenges of Aluminum-Based Metal Matrix Compos...IRJET Journal
This document reviews the progress and challenges of aluminum-based metal matrix composites (MMCs), focusing on their fabrication processes and applications. It discusses how various aluminum MMCs have been developed using reinforcements like borides, carbides, oxides, and nitrides to improve mechanical and wear properties. These composites have gained prominence for their lightweight, high-strength and corrosion resistance properties. The document also examines recent advancements in fabrication techniques for aluminum MMCs and their growing applications in industries such as aerospace and automotive. However, it notes that challenges remain around issues like improper mixing of reinforcements and reducing reinforcement agglomeration.
Dynamic Urban Transit Optimization: A Graph Neural Network Approach for Real-...IRJET Journal
This document discusses research on using graph neural networks (GNNs) for dynamic optimization of public transportation networks in real-time. GNNs represent transit networks as graphs with nodes as stops and edges as connections. The GNN model aims to optimize networks using real-time data on vehicle locations, arrival times, and passenger loads. This helps increase mobility, decrease traffic, and improve efficiency. The system continuously trains and infers to adapt to changing transit conditions, providing decision support tools. While research has focused on performance, more work is needed on security, socio-economic impacts, contextual generalization of models, continuous learning approaches, and effective real-time visualization.
Structural Analysis and Design of Multi-Storey Symmetric and Asymmetric Shape...IRJET Journal
This document summarizes a research project that aims to compare the structural performance of conventional slab and grid slab systems in multi-story buildings using ETABS software. The study will analyze both symmetric and asymmetric building models under various loading conditions. Parameters like deflections, moments, shears, and stresses will be examined to evaluate the structural effectiveness of each slab type. The results will provide insights into the comparative behavior of conventional and grid slabs to help engineers and architects select appropriate slab systems based on building layouts and design requirements.
A Review of “Seismic Response of RC Structures Having Plan and Vertical Irreg...IRJET Journal
This document summarizes and reviews a research paper on the seismic response of reinforced concrete (RC) structures with plan and vertical irregularities, with and without infill walls. It discusses how infill walls can improve or reduce the seismic performance of RC buildings, depending on factors like wall layout, height distribution, connection to the frame, and relative stiffness of walls and frames. The reviewed research paper analyzes the behavior of infill walls, effects of vertical irregularities, and seismic performance of high-rise structures under linear static and dynamic analysis. It studies response characteristics like story drift, deflection and shear. The document also provides literature on similar research investigating the effects of infill walls, soft stories, plan irregularities, and different
This document provides a review of machine learning techniques used in Advanced Driver Assistance Systems (ADAS). It begins with an abstract that summarizes key applications of machine learning in ADAS, including object detection, recognition, and decision-making. The introduction discusses the integration of machine learning in ADAS and how it is transforming vehicle safety. The literature review then examines several research papers on topics like lightweight deep learning models for object detection and lane detection models using image processing. It concludes by discussing challenges and opportunities in the field, such as improving algorithm robustness and adaptability.
Long Term Trend Analysis of Precipitation and Temperature for Asosa district,...IRJET Journal
The document analyzes temperature and precipitation trends in Asosa District, Benishangul Gumuz Region, Ethiopia from 1993 to 2022 based on data from the local meteorological station. The results show:
1) The average maximum and minimum annual temperatures have generally decreased over time, with maximum temperatures decreasing by a factor of -0.0341 and minimum by -0.0152.
2) Mann-Kendall tests found the decreasing temperature trends to be statistically significant for annual maximum temperatures but not for annual minimum temperatures.
3) Annual precipitation in Asosa District showed a statistically significant increasing trend.
The conclusions recommend development planners account for rising summer precipitation and declining temperatures in
P.E.B. Framed Structure Design and Analysis Using STAAD ProIRJET Journal
This document discusses the design and analysis of pre-engineered building (PEB) framed structures using STAAD Pro software. It provides an overview of PEBs, including that they are designed off-site with building trusses and beams produced in a factory. STAAD Pro is identified as a key tool for modeling, analyzing, and designing PEBs to ensure their performance and safety under various load scenarios. The document outlines modeling structural parts in STAAD Pro, evaluating structural reactions, assigning loads, and following international design codes and standards. In summary, STAAD Pro is used to design and analyze PEB framed structures to ensure safety and code compliance.
A Review on Innovative Fiber Integration for Enhanced Reinforcement of Concre...IRJET Journal
This document provides a review of research on innovative fiber integration methods for reinforcing concrete structures. It discusses studies that have explored using carbon fiber reinforced polymer (CFRP) composites with recycled plastic aggregates to develop more sustainable strengthening techniques. It also examines using ultra-high performance fiber reinforced concrete to improve shear strength in beams. Additional topics covered include the dynamic responses of FRP-strengthened beams under static and impact loads, and the performance of preloaded CFRP-strengthened fiber reinforced concrete beams. The review highlights the potential of fiber composites to enable more sustainable and resilient construction practices.
Survey Paper on Cloud-Based Secured Healthcare SystemIRJET Journal
This document summarizes a survey on securing patient healthcare data in cloud-based systems. It discusses using technologies like facial recognition, smart cards, and cloud computing combined with strong encryption to securely store patient data. The survey found that healthcare professionals believe digitizing patient records and storing them in a centralized cloud system would improve access during emergencies and enable more efficient care compared to paper-based systems. However, ensuring privacy and security of patient data is paramount as healthcare incorporates these digital technologies.
Review on studies and research on widening of existing concrete bridgesIRJET Journal
This document summarizes several studies that have been conducted on widening existing concrete bridges. It describes a study from China that examined load distribution factors for a bridge widened with composite steel-concrete girders. It also outlines challenges and solutions for widening a bridge in the UAE, including replacing bearings and stitching the new and existing structures. Additionally, it discusses two bridge widening projects in New Zealand that involved adding precast beams and stitching to connect structures. Finally, safety measures and challenges for strengthening a historic bridge in Switzerland under live traffic are presented.
React based fullstack edtech web applicationIRJET Journal
The document describes the architecture of an educational technology web application built using the MERN stack. It discusses the frontend developed with ReactJS, backend with NodeJS and ExpressJS, and MongoDB database. The frontend provides dynamic user interfaces, while the backend offers APIs for authentication, course management, and other functions. MongoDB enables flexible data storage. The architecture aims to provide a scalable, responsive platform for online learning.
A Comprehensive Review of Integrating IoT and Blockchain Technologies in the ...IRJET Journal
This paper proposes integrating Internet of Things (IoT) and blockchain technologies to help implement objectives of India's National Education Policy (NEP) in the education sector. The paper discusses how blockchain could be used for secure student data management, credential verification, and decentralized learning platforms. IoT devices could create smart classrooms, automate attendance tracking, and enable real-time monitoring. Blockchain would ensure integrity of exam processes and resource allocation, while smart contracts automate agreements. The paper argues this integration has potential to revolutionize education by making it more secure, transparent and efficient, in alignment with NEP goals. However, challenges like infrastructure needs, data privacy, and collaborative efforts are also discussed.
A REVIEW ON THE PERFORMANCE OF COCONUT FIBRE REINFORCED CONCRETE.IRJET Journal
This document provides a review of research on the performance of coconut fibre reinforced concrete. It summarizes several studies that tested different volume fractions and lengths of coconut fibres in concrete mixtures with varying compressive strengths. The studies found that coconut fibre improved properties like tensile strength, toughness, crack resistance, and spalling resistance compared to plain concrete. Volume fractions of 2-5% and fibre lengths of 20-50mm produced the best results. The document concludes that using a 4-5% volume fraction of coconut fibres 30-40mm in length with M30-M60 grade concrete would provide benefits based on previous research.
Optimizing Business Management Process Workflows: The Dynamic Influence of Mi...IRJET Journal
The document discusses optimizing business management processes through automation using Microsoft Power Automate and artificial intelligence. It provides an overview of Power Automate's key components and features for automating workflows across various apps and services. The document then presents several scenarios applying automation solutions to common business processes like data entry, monitoring, HR, finance, customer support, and more. It estimates the potential time and cost savings from implementing automation for each scenario. Finally, the conclusion emphasizes the transformative impact of AI and automation tools on business processes and the need for ongoing optimization.
Multistoried and Multi Bay Steel Building Frame by using Seismic DesignIRJET Journal
The document describes the seismic design of a G+5 steel building frame located in Roorkee, India according to Indian codes IS 1893-2002 and IS 800. The frame was analyzed using the equivalent static load method and response spectrum method, and its response in terms of displacements and shear forces were compared. Based on the analysis, the frame was designed as a seismic-resistant steel structure according to IS 800:2007. The software STAAD Pro was used for the analysis and design.
Cost Optimization of Construction Using Plastic Waste as a Sustainable Constr...IRJET Journal
This research paper explores using plastic waste as a sustainable and cost-effective construction material. The study focuses on manufacturing pavers and bricks using recycled plastic and partially replacing concrete with plastic alternatives. Initial results found that pavers and bricks made from recycled plastic demonstrate comparable strength and durability to traditional materials while providing environmental and cost benefits. Additionally, preliminary research indicates incorporating plastic waste as a partial concrete replacement significantly reduces construction costs without compromising structural integrity. The outcomes suggest adopting plastic waste in construction can address plastic pollution while optimizing costs, promoting more sustainable building practices.
ACEP Magazine edition 4th launched on 05.06.2024Rahul
This document provides information about the third edition of the magazine "Sthapatya" published by the Association of Civil Engineers (Practicing) Aurangabad. It includes messages from current and past presidents of ACEP, memories and photos from past ACEP events, information on life time achievement awards given by ACEP, and a technical article on concrete maintenance, repairs and strengthening. The document highlights activities of ACEP and provides a technical educational article for members.
Batteries -Introduction – Types of Batteries – discharging and charging of battery - characteristics of battery –battery rating- various tests on battery- – Primary battery: silver button cell- Secondary battery :Ni-Cd battery-modern battery: lithium ion battery-maintenance of batteries-choices of batteries for electric vehicle applications.
Fuel Cells: Introduction- importance and classification of fuel cells - description, principle, components, applications of fuel cells: H2-O2 fuel cell, alkaline fuel cell, molten carbonate fuel cell and direct methanol fuel cells.
UNLOCKING HEALTHCARE 4.0: NAVIGATING CRITICAL SUCCESS FACTORS FOR EFFECTIVE I...amsjournal
The Fourth Industrial Revolution is transforming industries, including healthcare, by integrating digital,
physical, and biological technologies. This study examines the integration of 4.0 technologies into
healthcare, identifying success factors and challenges through interviews with 70 stakeholders from 33
countries. Healthcare is evolving significantly, with varied objectives across nations aiming to improve
population health. The study explores stakeholders' perceptions on critical success factors, identifying
challenges such as insufficiently trained personnel, organizational silos, and structural barriers to data
exchange. Facilitators for integration include cost reduction initiatives and interoperability policies.
Technologies like IoT, Big Data, AI, Machine Learning, and robotics enhance diagnostics, treatment
precision, and real-time monitoring, reducing errors and optimizing resource utilization. Automation
improves employee satisfaction and patient care, while Blockchain and telemedicine drive cost reductions.
Successful integration requires skilled professionals and supportive policies, promising efficient resource
use, lower error rates, and accelerated processes, leading to optimized global healthcare outcomes.
Embedded machine learning-based road conditions and driving behavior monitoringIJECEIAES
Car accident rates have increased in recent years, resulting in losses in human lives, properties, and other financial costs. An embedded machine learning-based system is developed to address this critical issue. The system can monitor road conditions, detect driving patterns, and identify aggressive driving behaviors. The system is based on neural networks trained on a comprehensive dataset of driving events, driving styles, and road conditions. The system effectively detects potential risks and helps mitigate the frequency and impact of accidents. The primary goal is to ensure the safety of drivers and vehicles. Collecting data involved gathering information on three key road events: normal street and normal drive, speed bumps, circular yellow speed bumps, and three aggressive driving actions: sudden start, sudden stop, and sudden entry. The gathered data is processed and analyzed using a machine learning system designed for limited power and memory devices. The developed system resulted in 91.9% accuracy, 93.6% precision, and 92% recall. The achieved inference time on an Arduino Nano 33 BLE Sense with a 32-bit CPU running at 64 MHz is 34 ms and requires 2.6 kB peak RAM and 139.9 kB program flash memory, making it suitable for resource-constrained embedded systems.
Advanced control scheme of doubly fed induction generator for wind turbine us...IJECEIAES
This paper describes a speed control device for generating electrical energy on an electricity network based on the doubly fed induction generator (DFIG) used for wind power conversion systems. At first, a double-fed induction generator model was constructed. A control law is formulated to govern the flow of energy between the stator of a DFIG and the energy network using three types of controllers: proportional integral (PI), sliding mode controller (SMC) and second order sliding mode controller (SOSMC). Their different results in terms of power reference tracking, reaction to unexpected speed fluctuations, sensitivity to perturbations, and resilience against machine parameter alterations are compared. MATLAB/Simulink was used to conduct the simulations for the preceding study. Multiple simulations have shown very satisfying results, and the investigations demonstrate the efficacy and power-enhancing capabilities of the suggested control system.
Introduction- e - waste – definition - sources of e-waste– hazardous substances in e-waste - effects of e-waste on environment and human health- need for e-waste management– e-waste handling rules - waste minimization techniques for managing e-waste – recycling of e-waste - disposal treatment methods of e- waste – mechanism of extraction of precious metal from leaching solution-global Scenario of E-waste – E-waste in India- case studies.
The CBC machine is a common diagnostic tool used by doctors to measure a patient's red blood cell count, white blood cell count and platelet count. The machine uses a small sample of the patient's blood, which is then placed into special tubes and analyzed. The results of the analysis are then displayed on a screen for the doctor to review. The CBC machine is an important tool for diagnosing various conditions, such as anemia, infection and leukemia. It can also help to monitor a patient's response to treatment.
Comparative analysis between traditional aquaponics and reconstructed aquapon...bijceesjournal
The aquaponic system of planting is a method that does not require soil usage. It is a method that only needs water, fish, lava rocks (a substitute for soil), and plants. Aquaponic systems are sustainable and environmentally friendly. Its use not only helps to plant in small spaces but also helps reduce artificial chemical use and minimizes excess water use, as aquaponics consumes 90% less water than soil-based gardening. The study applied a descriptive and experimental design to assess and compare conventional and reconstructed aquaponic methods for reproducing tomatoes. The researchers created an observation checklist to determine the significant factors of the study. The study aims to determine the significant difference between traditional aquaponics and reconstructed aquaponics systems propagating tomatoes in terms of height, weight, girth, and number of fruits. The reconstructed aquaponics system’s higher growth yield results in a much more nourished crop than the traditional aquaponics system. It is superior in its number of fruits, height, weight, and girth measurement. Moreover, the reconstructed aquaponics system is proven to eliminate all the hindrances present in the traditional aquaponics system, which are overcrowding of fish, algae growth, pest problems, contaminated water, and dead fish.
KuberTENes Birthday Bash Guadalajara - K8sGPT first impressionsVictor Morales
K8sGPT is a tool that analyzes and diagnoses Kubernetes clusters. This presentation was used to share the requirements and dependencies to deploy K8sGPT in a local environment.
Electric vehicle and photovoltaic advanced roles in enhancing the financial p...IJECEIAES
Climate change's impact on the planet forced the United Nations and governments to promote green energies and electric transportation. The deployments of photovoltaic (PV) and electric vehicle (EV) systems gained stronger momentum due to their numerous advantages over fossil fuel types. The advantages go beyond sustainability to reach financial support and stability. The work in this paper introduces the hybrid system between PV and EV to support industrial and commercial plants. This paper covers the theoretical framework of the proposed hybrid system including the required equation to complete the cost analysis when PV and EV are present. In addition, the proposed design diagram which sets the priorities and requirements of the system is presented. The proposed approach allows setup to advance their power stability, especially during power outages. The presented information supports researchers and plant owners to complete the necessary analysis while promoting the deployment of clean energy. The result of a case study that represents a dairy milk farmer supports the theoretical works and highlights its advanced benefits to existing plants. The short return on investment of the proposed approach supports the paper's novelty approach for the sustainable electrical system. In addition, the proposed system allows for an isolated power setup without the need for a transmission line which enhances the safety of the electrical network
Harnessing WebAssembly for Real-time Stateless Streaming PipelinesChristina Lin
Traditionally, dealing with real-time data pipelines has involved significant overhead, even for straightforward tasks like data transformation or masking. However, in this talk, we’ll venture into the dynamic realm of WebAssembly (WASM) and discover how it can revolutionize the creation of stateless streaming pipelines within a Kafka (Redpanda) broker. These pipelines are adept at managing low-latency, high-data-volume scenarios.