MAJOR PROJEC TVLSI

ANURAGENGINEERINGCOLLEGE
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DEPARTMENT OF ECE
1. INTRODUCTION
1.1 INTRODUCTION
In the world of serial data communication, there are protocols like RS-232, RS-422, RS-
485, SPI (Serial peripheral interface), Micro wire for interfacing high speed and low speed
peripherals. These protocols require more pin connection in the IC(Integrated Circuit) for
serial data communication to take place, as the physical size of IC have decreased over the
years, we require less amount of pin connection for serial data transfer. USB/SPI/Micro wire
and mostly UARTS are all just ‘one point to one point’ data transfer bus systems. They use
multiplexing of the data path and forwarding of messages to service multiple devices. To
overcome this problem, the I2C protocol was introduced by Phillips which requires only two
lines for communication with two or more chips and can control a network of device chips
with just a two general purpose I/O pins whereas, other bus protocols require more
pins and signals to connect devices.
In this project, I2C bus protocol for interfacing low speed peripheral devices on FPGA
is implemented. It is also the best bus for the control applications, where devices may have to
be added or removed from the system. I2C protocol can also be used for communication
between multiple circuit boards in equipments with or without using a shielded cable
depending on the distance and speed of data transfer. I2C bus is a medium for
communication where master controller is used to send and receive data to and from the slave
DS1307. The low speed peripheral, DS1307 is interfaced with I2C master bus and
synthesized on Spartan 3E.
1.2 INTRODUCTION TO VLSI
1.2.1 Historical Perspective
The electronics industry has achieved a phenomenal growth over the last two decades, mainly
due to the rapid advances in integration technologies, large-scale systems design - in short,
due to the advent of VLSI. The number of applications of integrated circuits in high-
performance computing, telecommunications, and consumer electronics has been rising
steadily, and at a very fast pace. Typically, the required computational power (or, in other
words, the intelligence) of these applications is the driving force for the fast development of
this field.

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The current leading-edge technologies (such as low bit-rate video and cellular
communications) already provide the end-users a certain amount of processing power and
portability. This trend is expected to continue, with very important implications on VLSI and
systems design. One of the most important characteristics of information services is their
increasing need for very high processing power and bandwidth (in order to handle real-time
video, for example). The other important characteristic is that the information services tend to
become more and more personalized (as opposed to collective services such as broadcasting),
which means that the devices must be more intelligent to answer individual demands, and at
the same time they must be portable to allow more flexibility/mobility.
As more and more complex functions are required in various data processing and
telecommunications devices, the need to integrate these functions in a small system/package
is also increasing. The level of integration as measured by the number of logic gates in a
monolithic chip has been steadily rising for almost three decades, mainly due to the rapid
progress in processing technology and interconnect technology.
Table 1.1 shows the evolution of logic complexity in integrated circuits over the last
three decades, and marks the milestones of each era. Here, the numbers for circuit complexity
should be interpreted only as representative examples to show the order-of-magnitude. A
logic block can contain anywhere from 10 to 100 transistors, depending on the function.
State-of-the-art examples of ULSI chips, such as the DEC Alpha or the INTEL Pentium
contain 3 to 6 million transistors.
Table1.1 Evolution of logic complexity in integrated circuits
ERA
(number of logic blocks per
chip)
DATE COMPLEXITY
Single transistor 1959 Less than 1
Unit logic 1960 1
Multiple function 1962 2-4
Complex function 1964 5-20
Medium Scale Integration 1967 20-200 (MSI)
Large Scale Integration 1972 200-2000 (LSI)
Very Large Scale Integration 1978 2000-20000 (VLSI)
Ultra Large Scale Integration 1989 20000-? (ULSI)

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The most important mes1sage here is that the logic complexity per chip has been (and still is)
increasing exponentially. The monolithic integration of a large number of functions on a
single chip usually provides:
 Less area/volume and therefore, compactness
 Less power consumption
 Less testing requirements at system level
 Higher reliability, mainly due to improved on-chip interconnects
 Higher speed, due to significantly reduced interconnection length
 Significant cost savings
Figure 1.1 Evolution of integration density and minimum feature size
Therefore, the current trend of integration will also continue in the foreseeable future.
Advances in device manufacturing technology, and especially the steady reduction of
minimum feature size (minimum length of a transistor or an inter connect realizable on chip)
support this trend. Figure 1.1 shows the history and forecast of chip complexity - and
minimum feature size - over time, as seen in the early 1980s. At that time, a minimum feature
size of 0.3 microns was expected around the year 2000. The actual development of the
technology, however, has far exceeded these expectations. A minimum size of 0.25 microns
was readily achievable by the year 1995.

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DEPARTMENT OF ECE
As a direct result of this, the integration density has also exceeded previous expectations - the
first 64 Mbit DRAM, and the INTEL Pentium microprocessor chip containing more than 3
million transistors were already available by 1994, pushing the envelope of integration
density. When comparing the integration density of integrated circuits, a clear distinction
must be made between the memory chips and logic chips.
Generally speaking, logic chips such as microprocessor chips and digital signal
processing (DSP) chips contain not only large arrays of memory (SRAM) cells, but also
many different functional units. As a result, their design complexity is considered much
higher than that of memory chips, although advanced memory chips contain some
sophisticated logic functions.
The design complexity of logic chips increases almost exponentially with the number
of transistors to be integrated. This is translated into the increase in the design cycle time,
which is the time period from the start of the chip development until the mask-tape delivery
time. However, in order to make the best use of the current technology, the chip development
time has to be short enough to allow the maturing of chip manufacturing and timely delivery
to customers. As a result, the level of actual logic integration tends to fall short of the
integration level achievable with the current processing technology. Sophisticated computer-
aided design (CAD) tools and methodologies are developed and applied in order to manage
the rapidly increasing design complexity.
1.2.2 VLSI Design Flow
The design process, at various levels, is usually evolutionary in nature. It starts with a given
set of requirements. Initial design is developed and tested against the requirements. When
requirements are not met, the design has to be improved. If such improvement is either not
possible or too costly, then the revision of requirements and its impact analysis must be
considered. The Y-chart (first introduced by D. Gajski) illustrates a design flow for most
logic chips, using design activities on three different axes (domains) which resemble the letter
Y.
The Y-chart consists of three major domains, namely:
 Behavioral domain,
 Structural domain,
 Geometrical layout domain.

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The design flow starts from the algorithm that describes the behavior of the target chip. The
corresponding architecture of the processor is first defined. It is mapped onto the chip surface
by floor planning. The next design evolution in the behavioral domain defines finite state
machines (FSMs) which are structurally implemented with functional modules such as
registers and arithmetic logic units (ALUs).
These modules are then geometrically placed onto the chip surface using CAD tools
for automatic module placement followed by routing, with a goal of minimizing the inter
connects area and signal delays. The third evolution starts with a behavioral module
description. Individual modules are then implemented with leaf cells. At this stage the chip is
described in terms of logic gates (leaf cells), which can be placed and interconnected by using
a cell placement & routing program. The last evolution involves a detailed Boolean
description of leaf cells followed by a transistor level implementation of leaf cells and mask
generation. In standard-cell based design, leaf cells are already pre-designed and stored in a
library for logic design use.
Figure 1.2 provides a more simplified view of the VLSI design flow, taking into
account the various representations, or abstractions of design - behavioral, logic, circuit and
mask layout. Note that the verification of design plays a very important role in every step
during this process. The failure to properly verify a design in its early phases typically causes
significant and expensive re-design at a later stage, which ultimately increases the time-to-
market.
Figure 1.2 Simplified view of VLSI design flow

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Although the design process has been described in linear fashion for simplicity, in reality
there are many iterations back and forth, especially between any two neighboring steps, and
occasionally even remotely separated pairs. Although top-down design flow provides an
excellent design process control, in reality, there is no truly unidirectional top-down design
flow. Both top-down and bottom-up approaches have to be combined. For instance, if a chip
designer defined architecture without close estimation of the corresponding chip area, then it
is very likely that the resulting chip layout exceeds the area limit of the available technology.
In such a case, in order to fit the architecture into the allowable chip area, some
functions may have to be removed and the design process must be repeated. Such changes
may require significant modification of the original requirements. Thus, it is very important
to feed forward low-level information to higher levels (bottom up) as early as possible.
In the following, we will examine design methodologies and structured approaches
which have been developed over the years to deal with both complex hardware and software
projects. Regardless of the actual size of the project, the basic principles of structured design
will improve the prospects of success. Some of the classical techniques for reducing the
complexity of IC design are: Hierarchy, regularity, modularity and locality.
1.2.3 Design Hierarchy
The use of hierarchy or divide and conquer technique involves dividing a module into sub-
modules and then repeating this operation on the sub-modules until the complexity of the
smaller parts becomes manageable. This approach is very similar to the software case where
large programs are split into smaller and smaller sections until simple subroutines, with well-
defined functions and interfaces can be written. In Section 1.2.2, we have seen that the design
of a VLSI chip can be represented in three domains. Correspondingly, a hierarchy structure
can be described in each domain separately. However, it is important for the simplicity of
design that the hierarchies in different domains can be mapped into each other easily

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2. LITERATURE REVIEW
2.1 SPI PROTOCOL
The Serial Peripheral Interface (SPI) bus is a synchronous serial communication interface
specification used for short distance communication, primarily in embedded systems. The
interface was developed by Motorola and has become a de facto standard. Typical
applications include sensors, Secure Digital cards, and liquid crystal displays.
SPI devices communicate in full duplex mode using master-slave architecture with a
single master. The master device originates the frame for reading and writing. Multiple slave
devices are supported through selection with individual slave select (SS) lines.
Sometimes SPI is called a four-wire serial bus, contrasting with three-, two-, and one-
wire serial buses. The SPI may be accurately described as a synchronous serial interface, but
it is different from the Synchronous Serial Interface (SSI) protocol, which is also a four-wire
synchronous serial communication protocol, but employs differential signaling and provides
only a single simplex communication channel.
Figure 2.1 SPI Communication
2.2 DISADVANTAGES
 Requires more pins on IC packages , even in the three-wire variant
 No in-band addressing; out-of-band chip select signals are required on shared buses
 No hardware flow control by the slave (but the master can delay the next clock edge to
slow the transfer rate)
 No hardware slave acknowledgment (the master could be transmitting to nowhere and not
know it)
 Supports only one master device
 No error-checking protocol is defined
 Without a formal standard, validating conformance is not possible

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 Only handles short distances compared to RS-232, RS-485, or CAN-bus
 Many existing variations, making it difficult to find development tools like host adapters
that support those variations
 SPI does not support hot swapping (dynamically adding nodes).
 Interrupts must either be implemented with out-of-band signals or be faked by using
periodic polling similarly to USB 1.1 and 2.0
 Some variants like Multi I/O SPI and three-wire serial buses defined below are half-
duplex.
2.2 I2
C PROTOCOL
An Inter-IC bus is often used to communicate across circuit-board distances. Here's a primer
on the protocol. At the low end of the spectrum of communication options for "inside the
box" communication is I2C ("eye-squared-see"). The name I2C is shorthand for a standard
Inter-IC (integrated circuit) bus.
I2C provides good support for communication with various slow, on-board peripheral
devices that are accessed intermittently, while being extremely modest in its hardware
resource needs. It is a simple, low-bandwidth, short-distance protocol. Most available I2C
devices operate at speeds up to 400Kbps, with some venturing up into the low megahertz
range. I2C is easy to use to link multiple devices together since it has a built-in addressing
scheme.
Philips originally developed I2C for communication between devices inside of a TV
set. Examples of simple I2C-compatible devices found in embedded systems include
EEPROMs, thermal sensors, and real-time clocks. I2C is also used as a control interface to
signal processing devices that have separate, application-specific data interfaces. For
instance, it's commonly used in multimedia applications, where typical devices include RF
tuners, video decoders and encoders, and audio processors. In all, Philips, National
Semiconductor, Xicor, Siemens, and other manufacturers offer hundreds of I2C-compatible
devices.

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3. I
2
C Master Bus Controller
3.1 PROPOSED WORK
I2C is a two wire, bidirectional serial bus that provides effective data communication between
two devices. I2C bus supports many devices and each device is recognized by its unique
address. In Figure 3.1 data_in and addr_in are the 8 bit address given as an input. Clk and
reset are the input lines used to initiate the bus controller process. The R/ w signal is given
as an input to indicate whether master or slave acts as a transmitter in the data transmission.
data_in[7:0]
addr_in[6:0] SDA
Clk SCL
Reset
R/W‾‾
Figure 3.1 I2C Master Bus controller interfaced with slave DS1307
The physical I2C bus consists of just two wires, called SCL and SDA. SCL is the
clock line. It is used to synchronize all data transfers over the I2C bus. SDA is the data line.
The SCL and SDA lines are connected to all devices on the I2C bus. As both SCL and SDA
lines are "open drain" drivers they are pulled up using pull up resistors.The I2C bus is said to
be idle when both SCL and SDA are at logic 1 level. When the master (controller) wishes to
transmit data to a slave (DS1307) it begins by issuing a start sequence on the I2C bus,
which is a high to low transition on the SDA line while the SCL line is high as shown in
Figure 3.2.
I2C
Master
Bus
Controller
DS1307
RTC

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DEPARTMENT OF ECE
Figure 3.2 (a) “START” Sequence (b) “STOP” Sequence
The bus is considered to be busy after the START condition. After the START
condition, slave address is sent by the master. The slave device whose address matches the
address that is being sent out by the master will respond with an acknowledgement bit on the
SDA line by pulling the SDA line low. Data is transferred in sequences of 8 bits. The bits
are placed on the SDA line starting with the MSB (Most Significant Bit). For every 8 bits
transferred, the slave device receiving the data sends back an acknowledge bit, so there are
actually 9 SCL clock pulses to transfer each 8 bit byte of data this is shown in Figure 3.3.If
the receiving device sends back a low ACK bit, then it has received the data and is ready
to accept another byte. If it sends back a high then it is indicating it cannot accept any further
data and the master should terminate the transfer by sending a STOP sequence. In Figure
3.1b which shows the STOP sequence, where the SDA line is driven low while SCL line is
high. This signals the end of the transaction with the slave device.
Figure 3.3Acknowledgement on the I2C Bus

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3.2 SERIAL DATA COMMUNICATION
The I2C bus has two modes of operation: master transmitter and master receiver. The I2C
master bus initiates data transfer and can drive both SDA and SCL lines. Slave device
(DS1307) is addressed by the master. It can issue only data on the SDA line. In master
transmission mode, after the initiation of the START sequence, the master sends out a slave
address. The address byte contains the 7 bit DS1307 address, which is 1101000, followed by
the direction bit (R/ w).
After receiving and decoding the address byte the device outputs
acknowledge on the SDA line. After the DS1307 acknowledges the slave address + write bit,
the master transmits a register address to the DS1307 this will set the register pointer on
the DS1307. The master will then begin transmitting each byte of data with the DS1307
acknowledging each byte received. The master will generate a stop condition to terminate the
data write.
Figure 3.4 Master transmission mode
3.3 MAXIM DS1307
The DS1307 supports a bi-directional, 2- wire bus and data transmission protocol. The pin
assignment of DS1307 is given in Figure 3.4.The DS1307 operates as a slave on the 2- wire
bus.
Figure 3.5 Pin assignment of DS1307

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3.4 SOFTWARE IMPLEMENTATION
I2C master controller is designed using Verilog HDL based on Finite State Machine (FSM).
FSM is a sequential circuit that uses a finite number of states to keep track of its history of
operations, and based on history of operation and current input, determines the next state.
There are several states in obtaining the result.
3.5 ALGORITHM
State1 : An idle condition: I2C bus doesn’t perform any operation. (SCL and
SDA remains high).
State 2 : Start condition: master initiates data transmission by providing START (SCL
is high and SDA is from high to low).
State 3 : Slave address - write: master sends the slave address-write (11010000) to the
slave.
State 4 : If the slave address matches with the slave, it sends an acknowledgement bit
in response to the master.
State 5 : 8 Bit Register Address will be transmitted to the slave. Again
acknowledgement is sent to the master by the slave.
State 6 : Data to be transmitted is sent to the slave by the master. After receiving the
data, slave acknowledges the master.
State7 : Stop condition: Slave sends a stop bit to the master to terminate the
communication (SCL is high and SDA is from Low to high).
The flowchart for I2C master bus communication with slave device is shown in figure 3.6

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Figure 3.6 Flowchart for I2C master bus communication with slave device
3.6 TIMING DIAGRAM
1. Data Transfer is initiated with a START bit (S) signaled by SDA being pulled low
while SCL stays high.
2. SDA sets the 1st data bit level while keeping SCL low (during blue bar time.)
3. The data is sampled (received) when SCL rises (green) for the first bit (B1).
4. This process repeats, SDA transitioning while SCL is low, and the data being read
while SCL is high (B2, Bn).
5. A STOP bit (P) is signaled when SDA is pulled high while SCL is high.

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In order to avoid false marker detection, SDA is changed on the SCL falling edge and is
sampled and captured on the rising edge of SCL.
3.7 ADVANTAGES
 Only two signal lines requires
 Flexible data transmission rates
 Each device on the bus is independently addressable
 Devices have a simple Master/Slave relationship
 Capable of handling multiple master communications by providing arbitration and
communication collision detection.
3.8 APPLICATIONS
I²C is appropriate for peripherals where simplicity and low manufacturing cost are more
important than speed. Common applications of the I²C bus are:
 Reading configuration data from SPD EEPROMs on SDRAM, DDR SDRAM, DDR2
SDRAM memory sticks (DIMM) and other stacked PC boards
 Supporting systems management for PCI cards, through a SM Bus 2.0 connection.
 Accessing NVRAM chips that keep user settings.
 Accessing low speed DACs and ADCs.
 Changing contrast, hue, and color balance settings in monitors (Display Data
Channel).
 Changing sound volume in intelligent speakers.
 Controlling OLED/LCD displays, like in a cell phone.
 Reading hardware monitors and diagnostic sensors, like a CPU thermistor or fan
speed.
 Reading real-time clocks.
 Turning on and turning off the power supply of system components.

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4. OVERVIEW OF VERILOG
In the semiconductor and electronic and design industry, Verilog is a hardware description
language (HDL) used to model electronic systems. Verilog HDL, not to be confused
with VHDL (a competing language), is most commonly used in the design, verification, and
implementation of digital logic chips at the register-transfer level of abstraction. It is also
used in the verification of analog and mixed-signal circuits.
4.1 OVERVIEW
Hardware description languages such as Verilog differ from software programming
languages because they include ways of describing the propagation of time and signal
dependency (sensitivity). There are two assignment operators, a blocking assignment (=), and
a non-blocking (<=) assignment. The non-blocking assignment allows designers to describe a
state-machine update without needing to declare and use temporary storage variables (in any
general programming language we need to define some temporary storage spaces for the
operands to be operated on subsequently; those are temporary storage variables). Since these
concepts are part of Verilog's language semantics, designers could quickly write descriptions
of large circuits in a relatively compact and concise form. At the time of Verilog's
introduction (1984), Verilog represented a tremendous productivity improvement for circuit
designers who were already using graphical schematic capture software and specially-written
software programs to document and simulate electronic circuits.
The designers of Verilog wanted a language with syntax similar to the C
programming language, which was already widely used in engineering software
development. Verilog is case-sensitive, has a basic preprocessor (though less sophisticated
than that of ANSI C/C++), and equivalent control flow keywords (if/else, for, while, case,
etc.), and compatible operator precedence. Syntactic differences include variable declaration
(Verilog requires bit-widths on net/reg types), demarcation of procedural blocks (begin/end
instead of curly braces {}), and many other minor differences.
A Verilog design consists of a hierarchy of modules. Modules encapsulate design
hierarchy, and communicate with other modules through a set of declared input, output, and
bidirectional ports. Internally, a module can contain any combination of the following:
net/variable declarations (wire, reg, integer, etc.), concurrent and sequential statement blocks,
and instances of other modules (sub-hierarchies).

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Sequential statements are placed inside a begin/end block and executed in sequential order
within the block. But the blocks themselves are executed concurrently, qualifying Verilog as
a dataflow language.
Verilog's concept of 'wire' consists of both signal values (4-state: "1, 0, floating,
undefined") and strengths (strong, weak, etc.). This system allows abstract modeling of
shared signal lines, where multiple sources drive a common net. When a wire has multiple
drivers, the wire's (readable) value is resolved by a function of the source drivers and their
strengths.
A subset of statements in the Verilog language is synthesizable. Verilog modules that
conform to a synthesizable coding style, known as RTL (register-transfer level), can be
physically realized by synthesis software. Synthesis software algorithmically transforms the
(abstract) Verilog source into a net list, a logically equivalent description consisting only of
elementary logic primitives (AND, OR, NOT, flip-flops, etc.) that are available in a
specific FPGA or VLSI technology. Further manipulations to the net list ultimately lead to a
circuit fabrication blueprint (such as a photo mask set for an ASIC or a bit stream file for
an FPGA).
4.1.1 History
Beginning:
Verilog was the first modern hardware description language to be invented. It was created
by Phil Moorby and Prabhu Goel during the winter of 1983/1984. The wording for this
process was "Automated Integrated Design Systems" (later renamed to Gateway Design
Automation in 1985) as a hardware modeling language. Gateway Design Automation was
purchased by Cadence Design Systems in 1990. Cadence now has full proprietary rights to
Gateway's Verilog and the Verilog-XL, the HDL-simulator that would become the de-facto
standard (of Verilog logic simulators) for the next decade. Originally, Verilog was intended
to describe and allow simulation; only afterwards was support for synthesis added.
Verilog-95:
With the increasing success of VHDL at the time, Cadence decided to make the language
available for open standardization. Cadence transferred Verilog into the public domain under
the Open Verilog International (OVI) (now known as Accellera) organization. Verilog was
later submitted to IEEE and became IEEE Standard 1364-1995, commonly referred to as
Verilog-95.

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In the same time frame Cadence initiated the creation of Verilog-A to put standards support
behind its analog simulator Spectre. Verilog-A was never intended to be a standalone
language and is a subset of Verilog-AMS which encompassed Verilog-95.
Verilog 2001:
Extensions to Verilog-95 were submitted back to IEEE to cover the deficiencies that users
had found in the original Verilog standard. These extensions became IEEE Standard 1364-
2001 known as Verilog-2001.
Verilog-2001 is a significant upgrade from Verilog-95. First, it adds explicit support
for (2's complement) signed nets and variables. Previously, code authors had to perform
signed operations using awkward bit-level manipulations (for example, the carry-out bit of a
simple 8-bit addition required an explicit description of the Boolean algebra to determine its
correct value). The same function under Verilog-2001 can be more succinctly described by
one of the built-in operators: +, -, /, *, >>>. A generate/endgenerate construct (similar to
VHDL's generate/endgenerate) allows Verilog-2001 to control instance and statement
instantiation through normal decision operators (case/if/else). Using generate/endgenerate,
Verilog-2001 can instantiate an array of instances, with control over the connectivity of the
individual instances. File I/O has been improved by several new system tasks. And finally, a
few syntax additions were introduced to improve code readability (e.g. always @*, named
parameter override, C-style function/task/module header declaration). Verilog-2001 is the
dominant flavor of Verilog supported by the majority of commercial EDA software packages.
Verilog 2005:
Not to be confused with System Verilog, Verilog 2005 (IEEE Standard 1364-2005) consists
of minor corrections, spec clarifications, and a few new language features (such as the uwire
keyword). A separate part of the Verilog standard, Verilog-AMS, attempts to integrate analog
and mixed signal modeling with traditional Verilog.
System Verilog:
System Verilog is a superset of Verilog-2005, with many new features and capabilities to aid
design verification and design modeling. As of 2009, the System Verilog and Verilog
language standards were merged into System Verilog 2009 (IEEE Standard 1800-2009). The
advent of hardware verification languages such as Open Vera, and Versity’s language
encouraged the development of Superlog by Co-Design Automation Inc.

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Co-Design Automation Inc was later purchased by Synopsys. The foundations of Superlog
and Vera were donated to Accellera, which later became the IEEE standard P1800-2005:
System Verilog.
In the late 1990s, the Verilog Hardware Description Language (HDL) became the
most widely used language for describing hardware for simulation and synthesis. However,
the first two versions standardized by the IEEE (1364-1995 and 1364-2001) had only simple
constructs for creating tests. As design sizes outgrew the verification capabilities of the
language, commercial Hardware Verification Languages (HVL) such as Open Vera and e
were created. Companies that did not want to pay for these tools instead spent hundreds of
man-years creating their own custom tools. This productivity crisis (along with a similar one
on the design side) led to the creation of Accellera, a consortium of EDA companies and
users who wanted to create the next generation of Verilog. The donation of the Open-Vera
language formed the basis for the HVL features of System Verilog. Accellera’s goal was met
in November 2005 with the adoption of the IEEE standard P1800-2005 for System Verilog,
IEEE (2005).
The most valuable benefit of System Verilog is that it allows the user to construct
reliable, repeatable verification environments, in a consistent syntax, that can be used across
multiple projects. Some of the typical features of an HDL that distinguish it from a Hardware
Description Language such as Verilog or VHDL are
 Constrained-random stimulus generation
 Functional coverage
 Higher-level structures, especially Object Oriented Programming
 Multi-threading and inter process communication
 Support for HDL types such as Verilog’s 4-state values
 Tight integration with event-simulator for control of the design
There are many other useful features, but these allow you to create test benches at a
higher level of abstraction than you are able to achieve with an HDL or a programming
language such as C.
System Verilog provides the best framework to achieve coverage-driven verification
(CDV). CDV combines automatic test generation, self-checking test benches, and coverage
metrics to significantly reduce the time spent verifying a design.

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The purpose of CDV is to:
 Eliminate the effort and time spent creating hundreds of tests.
 Ensure thorough verification using up-front goal setting.
 Receive early error notifications and deploy run-time checking and error analysis to
simplify debugging.
Example:
A simple example of two flip-flops follows:
module toplevel(clock,reset);
input clock;
input reset;
reg flop1;
reg flop2;
always @ (posedge reset or posedge clock)
if (reset)
begin
flop1 <= 0;
flop2 <= 1;
end
else
begin
flop1 <= flop2;
flop2 <= flop1;
end
endmodule
The "<=" operator in Verilog is another aspect of its being a hardware description
language as opposed to a normal procedural language. This is known as a "non-blocking"
assignment. Its action doesn't register until the next clock cycle. This means that the order of
the assignments is irrelevant and will produce the same result: flop1 and flop2 will swap
values every clock.

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The other assignment operator, "=", is referred to as a blocking assignment. When "="
assignment is used, for the purposes of logic, the target variable is updated immediately. In
the above example, had the statements used the "=" blocking operator instead of "<=", flop1
and flop2 would not have been swapped. Instead, as in traditional programming, the compiler
would understand to simply set flop1 equal to flop2 (and subsequently ignore the redundant
logic to set flop2 equal to flop1).
4.1.2 Constants
The definition of constants in Verilog supports the addition of a width parameter. The basic
syntax is:
<Width in bits>'<base letter><number>
Examples:
 12'h123 - Hexadecimal 123 (using 12 bits)
 20'd44 - Decimal 44 (using 20 bits - 0 extension is automatic)
 4'b1010 - Binary 1010 (using 4 bits)
 6'o77 - Octal 77 (using 6 bits)
4.1.3 Synthesizable Constructs
There are several statements in Verilog that have no analog in real hardware, e.g. $display.
Consequently, much of the language cannot be used to describe hardware. The examples
presented here are the classic subset of the language that has a direct mapping to real gates.
4.1.4 Initial Vs Always
There are two separate ways of declaring a Verilog process. These are the always and
the initial keywords. The always keyword indicates a free-running process.
The initial keyword indicates a process executes exactly once. Both constructs begin
execution at simulator time 0, and both execute until the end of the block. Once
an always block has reached its end, it is rescheduled (again). It is a common misconception
to believe that an initial block will execute before an always block. In fact, it is better to think
of the initial-block as a special-case of the always-block, one which terminates after it
completes for the first time.

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//Examples:
initial
begin
a = 1; // Assign a value to reg a at time 0
#1; // Wait 1 time unit
b = a; // Assign the value of reg a to reg b
end
always @(a or b) // Any time a or b CHANGE, run the process
begin
if (a)
c = b;
else
d = ~b;
end // Done with this block, now return to the top (i.e. the @ event-control)
always @(posedge a)// Run whenever reg a has a low to high change
a <= b;
These are the classic uses for these two keywords, but there are two significant
additional uses. The most common of these is an alwayskeyword without
the @(...) sensitivity list. It is possible to use always as shown below:
always
begin // Always begins executing at time 0 and NEVER stops
clk = 0; // Set clk to 0
#1; // Wait for 1 time unit
clk = 1; // Set clk to 1
#1; // Wait 1 time unit
end // Keeps executing - so continue back at the top of the begin
The always keyword acts similar to the "C" construct while (1) {..} in the sense that it
will execute forever. The other interesting exception is the use of the initial keyword with the
addition of the forever keyword.

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4.1.5 Operators
Operator
type
Operator
symbols
Operation performed
Bitwise
~ Bitwise NOT (1's complement)
& Bitwise AND
| Bitwise OR
^ Bitwise XOR
~ ^ or ^ ~ Bitwise XNOR
Logical
! NOT
&& AND
|| OR
Reduction
& Reduction AND
~& Reduction NAND
| Reduction OR
~| Reduction NOR
^ Reduction XOR
~ ^ or ^ ~ Reduction XNOR
Arithmetic
+ Addition
- Subtraction
- 2's complement
* Multiplication
/ Division
** Exponentiation (*Verilog-2001)

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4.2 FPGA DESIGN FLOW
Relational
> Greater than
< Less than
> = Greater than or equal to
< = Less than or equal to
= = Logical equality (bit-value 1'bX is removed from
comparison)
!= Logical inequality (bit-value 1'bX is removed from
comparison)
= = = 4-state logical equality (bit-value 1'bX is taken as literal)
!= = 4-state logical inequality (bit-value 1'bX is taken as literal)
Shift
>> Logical right shift
<< Logical left shift
>>> Arithmetic right shift (*Verilog-2001)
<<< Arithmetic left shift (*Verilog-2001)
Concatenation { , } Concatenation
Replication {n{m}} Replicate value m for n times
Conditional ? : Conditional
FPGA contains a two dimensional arrays of logic blocks and interconnections between logic
blocks. Both the logic blocks and interconnects are programmable. Logic blocks are
programmed to implement a desired function and the inter connects are programmed using
the switch boxes to connect the logic blocks. To be more clear, if we want to implement a
complex design (CPU for instance), then the design is divided into small sub functions and
each sub function is implemented using one logic block.

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Figure 4.1 Internal structure of an FPGA
FPGAs, alternative to the custom ICs, can be used to implement an entire System On
one Chip (SOC). The main advantage of FPGA is ability to reprogram. User can reprogram
an FPGA to implement a design and this is done after the FPGA is manufactured. This brings
the name “Field Programmable”. Custom ICs are expensive and takes long time to design so
they are useful when produced in bulk amounts.
But FPGAs are easy to implement within a short time with the help of Computer
Aided Designing (CAD) tools (because there is no physical layout process, no mask making,
and no IC manufacturing). Some disadvantages of FPGAs are, they are slow compared to
custom ICs as they can’t handle vary complex designs and also they draw more power.
Xilinx logic block consists of one Look Up Table (LUT) and one Flip-flop.
An LUT is used to implement number of different functionality. The input lines to the
logic block go into the LUT and enable it. The output of the LUT gives the result of the logic
function that it implements and the output of logic block is registered or unregistered output
from the LUT. SRAM is used to implement a LUT.A k-input logic function is implemented
using 2^k * 1 size SRAM. Number of different possible functions for k input LUT is 2^2^k.
Now, to get our desired design (CPU), all the sub functions implemented in logic blocks must
be connected and this is done by programming inter connects. Internal structure of an FPGA
is depicted in the following Figure.5.1.

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DEPARTMENT OF ECE
Advantage of such an architecture is that it supports implementation of so many logic
functions, however the disadvantage is unusually large number of memory cells required to
implement such a logic block in case number of inputs is large. Figure 5.2 below shows a 4-
input LUT based implementation of logic block.
Figure 4.2 4-input LUT based implementation of logic block.
LUT based design provides for better logic block utilization. A k-input LUT based
logic block can be implemented in number of different ways with trade off between
performance and logic density. An n-LUT can be shown as a direct implementation of a
function truth-table. Each of the latch holds the value of the function corresponding to one
input combination. For Example: 2-LUT can be used to implement 16 types of functions like
AND ,OR, A+not B .... etc.
A B AND OR NAND ...... ....
0 0 0 0 1
0 1 0 1 1
1 0 0 1 1
1 1 1 1 0
Interconnects:
A wire segment can be described as two end points of an inter connect with no programmable
switch between them. A sequence of one or more wire segments in an FPGA can be termed
as a track.

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Typically an FPGA has logic blocks, interconnects and switch blocks (Input/Output blocks).
Switch blocks lie in the periphery of logic blocks and interconnect. Wire segments are
connected to logic blocks through switch blocks. Depending on the required design, one logic
block is connected to another and so on.
4.2.1 Design Flow
In this part of tutorial we are going to have a short intro on FPGA design flow. A simplified
version of design flow is given in the following diagram.
Figure 4.3 FPGA design flow
4.2.2 Design Entry
There are different techniques for design entry. Schematic based, Hardware Description
Language and combination of both etc. . Selection of a method depends on the design and
designer. If the designer wants to deal more with Hardware, then Schematic entry is the better
choice. When the design is complex or the designer thinks the design in an algorithmic way
then HDL is the better choice. Language based entry is faster but lag in performance and
density.
HDLs represent a level of abstraction that can isolate the designers from the details of
the hardware implementation. Schematic based entry gives designers much more visibility
into the hardware. It is the better choice for those who are hardware oriented. Another
method but rarely used is state-machines. It is the better choice for the designers who think
the design as a series of states. But the tools for state machine entry are limited. In this
documentation we are going to deal with the HDL based design entry.

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4.2.3 Synthesis
The process which translates VHDL or Verilog code into a device netlist formate. i.e a
complete circuit with logical elements( gates, flip flops, etc…) for the design.If the design
contains more than one sub designs, ex. to implement a processor, we need a CPU as one
design element and RAM as another and so on, then the synthesis process generates netlist
for each design element. Synthesis process will check code syntax and analyze the hierarchy
of the design which ensures that the design is optimized for the design architecture, the
designer has selected. The resulting netlist(s) is saved to an NGC( Native Generic Circuit)
file (for Xilinx® Synthesis Technology (XST)).
Figure 4.4 FPGA synthesis
4.2.4. Implementation
This process consists a sequence of three steps
1. Translate
2. Map
3. Place and Route
Translate:
This process combines all the input netlists and constraints to a logic design file. This
information is saved as a NGD (Native Generic Database) file. This can be done using NGD
Build program. Here, defining constraints is nothing but, assigning the ports in the design to
the physical elements (ex. pins, switches, buttons etc) of the targeted device and specifying
time requirements of the design. This information is stored in a file named UCF (User
Constraints File). Tools used to create or modify the UCF are PACE, Constraint Editor etc.

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DEPARTMENT OF ECE
Figure 4.5 FPGA translate
Map:
This process divides the whole circuit with logical elements into sub blocks such that they
can be fit into the FPGA logic blocks. That means map process fits the logic defined by the
NGD file into the targeted FPGA elements (Combinational Logic Blocks (CLB), Input
Output Blocks (IOB)) and generates an NCD (Native Circuit Description) file which
physically represents the design mapped to the components of FPGA. MAP program is used
for this purpose.
Place and Route:
PAR program is used for this process. The place and route process places the sub blocks from
the map process into logic blocks according to the constraints and connects the logic blocks.
Ex. if a sub block is placed in a logic block which is very near to IO pin, then it may save the
time but it may affect some other constraint. So trade off between all the constraints is taken
account by the place and route process. The PAR tool takes the mapped NCD file as input
and produces a completely routed NCD file as output. Output NCD file consists the routing
information.
Figure 4.6 FPGA synthesis

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4.2.5 Device Programming
Now the design must be loaded on the FPGA. But the design must be converted to a format
so that the FPGA can accept it. BITGEN program deals with the conversion. The routed
NCD file is then given to the BITGEN program to generate a bit stream (a .BIT file) which
can be used to configure the target FPGA device. This can be done using a cable. Selection of
cable depends on the design.
4.2.6 DesignVerification
Verification can be done at different stages of the process steps.
Behavioral Simulation:
(RTL Simulation) This is first of all simulation steps; those are encountered throughout the
hierarchy of the design flow. This simulation is performed before synthesis process to verify
RTL (behavioral) code and to confirm that the design is functioning as intended. Behavioral
simulation can be performed on either VHDL or Verilog designs. In this process, signals and
variables are observed, procedures and functions are traced and breakpoints are set. This is a
very fast simulation and so allows the designer to change the HDL code if the required
functionality is not met with in a short time period. Since the design is not yet synthesized to
gate level, timing and resource usage properties are still unknown.
Functional simulation:
(Post Translate Simulation) Functional simulation gives information about the logic operation
of the circuit. Designer can verify the functionality of the design using this process after the
Translate process. If the functionality is not as expected, then the designer has to made
changes in the code and again follow the design flow steps.
Static Timing Analysis:
This can be done after MAP or PAR processes Post MAP timing report lists signal path
delays of the design derived from the design logic. Post Place and Route timing report
incorporates timing delay information to provide a comprehensive timing summary of the
design.

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5. XILINX ISE 14.4 DESIGN SUITE TUTORIAL
Run the Xilinx ISE 14.4 from the desk top or from start button
Click on ok on the tip of the day window
And click on the file and select file and new project..........

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Select working directory by clicking on the button opposite to the Location tab

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Give the project name and click on next
Select the design parameters as shown below and click next

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Click on finish
Right click on the project and select new source

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Select verilog model and give file name
Give inputs and outputs of the module

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Click on finish
Now write the verilog code ...

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Save the design by using save button or ctrl+s
And click on top module.....

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Double click on check syntax
Double Click on View RTL Schematic

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Click on ok ......
Click on Add

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Now select half adder and click on create schematic.....
Double click on the half adder box to see the internal architecture

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Now click on simulation check button
Now right click on the project and select new source

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Select Verilog Test Fixture and give file name
Click on next

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Select halfadder and click on next
Click on finish

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Now the test bench file is created as follows
Now go to initial block and give the all input combinations ........

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Save the file and select halfadder_tb to see isim simulator

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Double click on the behavioral Check Syntax

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Now Double click on the Simulate Behavioural Model

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Now ISIM GUI will open
Now click on zoom to full view

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Verify for 00
Verify for 01

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Verify for 10
Verify for 11

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6. EXPERIMENTAL RESULTS
6.1 SYNTHESIS RESULTS
Figure 6.1 Block diagram of I2c master bus controller
Figure 6.2 Expanded view of I2c master bus controller

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Device utilization summary:
Selected Device : 3s500efg320-4
Number of Slices: 16 out of 4656 0%
Number of Slice Flip Flops: 13 out of 9312 0%
Number of 4 input LUTs: 28 out of 9312 0%
Number of IOs: 19
Number of bonded IOBs: 19 out of 232 8%
Number of GCLKs: 1 out of 24 4%
TIMING REPORT
Clock Information:
Clock Signal | Clock buffer(FF name) | Load |
clk | IBUF+BUFG | 13 |
Asynchronous Control Signals Information:
Control Signal | Buffer(FF name) | Load |
rst | IBUF | 12 |
Timing Summary:
Speed Grade: -4
Minimum period: 6.598ns (Maximum Frequency: 151.561MHz)
Minimum input arrival time before clock: 5.113ns
Maximum output required time after clock: 5.582ns
Maximum combinational path delay: 6.140ns
Timing Detail:
All values displayed in nanoseconds (ns)

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6.2 SIMULATION RESULTS
(a)
(b)

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(c)
Figure 6.3 Simulation results (a) for state 0 (b) for state 1, 2, 3 and 4
(c) for states 5, 6 and 7

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7. CONCLUSION &FUTURE SCOPE
7.1 CONCLUSION
This project demonstrates how I2C Master Controller (Master) transmits data to the DS 1307
(Slave). So that any low speed peripheral devices can be interfaced using I2C bus protocol as
master.
7.2 FUTURE SCOPE
In future, this can be implemented as real time clock in networks that contains multiple
masters and multiple slaves to coordinate the entire system by clock synchronization
techniques.

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REFERENCES
[1] Philips Semiconductor “I2C Bus Specification”version 2. 1, January 2000.
[2] Maxim integrated “DS1307 64 x 8, Serial, I2C Real Time Clock”, 2008.
[3] Prof. Jai Karan Singh “Design and Implementation of I2c master controller on
FPGA using VHDL,” IJET, Vol 4 No 4 Aug-Sep 2012.
[4] Raj kamal ,“Embedded system: Architecture programming and Design”,
Tata McGraw Hill,2008.
[5] Stuart Sutherland, “Verilog® HDL Quick Reference Guide”, IEEE Std 1364-
2001.
[6] Tim Wilmshurst, “Designing Embedded Systems with PIC Microcontrollers:
Principles and Applications” Elsevier Ltd publications, 2007.
[7] Xilinx “Spartan-3A/3AN FPGA Starter Kit Board User Guide,”version
1.1,2008.
[8] A.P.Godse,D.A.Godse,“Microprocessor, Microcontroller & Applications ”
Technical publications,2008.
[9] Vincent Himpe, “Mastering the I2C bus” Elektor Verlag publications, 2011.
[10] Pong P.Chu, “FPGA Prototyping By Verilog Examples:Xilinx Spartan–3
Version” Wiley,2008.
[11] Mano,Ciletti, “Digital Design”Pearson Education India,edition 4,2008.
[12] M.Morris Mano, “Digital Design” EBSCO publishing.Inc., 2002.
[13] Frank Vahid, “Digital Design with RTL Design, Verilog and VHDL”VP and
Executive

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