The router is a network device that is used to connect subnetwork and packet-switched networking by directing the data packets to the intended IP addresses. It succeeds the traffic between different systems and allows several devices to share the internet connection. The router is applicable for the effective commutation in system on chip (SoC) modules for network on chip (NoC) communication. The research paper emphasizes the design of the two dimensional (2D) router hardware chip in the Xilinx integrated system environment (ISE) 14.7 software and further logic verification using the data packets transmitted from all input/output ports. The design evaluation is done based on the pre-synthesis device utilization summary relating to different field programmable gate array (FPGA) boards such as Spartan-3E (XC3S500E), Spartan-6 (XC6SLX45), Virtex-4 (XC4VFX12), Virtex-5 (XC5VSX50T), and Virtex-7 (XC7VX550T). The 64-bit data logic is verified on the different ports of the router configuration in the Xilinx and Modelsim waveform simulator. The Virtex-7 has proven the fast-switching speed and optimal hardware parameters in comparison to other FPGAs.
Many intellectual property (IP) modules are present in contemporary system on chips (SoCs). This could provide an issue with interconnection among different IP modules, which would limit the system's ability to scale. Traditional bus-based SoC architectures have a connectivity bottleneck, and network on chip (NoC) has evolved as an embedded switching network to address this issue. The interconnections between various cores or IP modules on a chip have a significant impact on communication and chip performance in terms of power, area latency and throughput. Also, designing a reliable fault tolerant NoC became a significant concern. In fault tolerant NoC it becomes critical to identify faulty node and dynamically reroute the packets keeping minimum latency. This study provides an insight into a domain of NoC, with intention of understanding fault tolerant approach based on the XY routing algorithm for 4×4 mesh architecture. The fault tolerant NoC design is synthesized on field programmable gate array (FPGA).
Network on Chip Architecture and Routing Techniques: A surveyIJRES Journal
This document summarizes research on Network on Chip (NOC) architecture and routing techniques. It discusses NOC topology options including mesh, torus, ring and irregular networks. It also reviews router architecture, switching techniques, virtual channels, buffering, error correction, quality of service implementations, and routing algorithms. Specific NOC implementations discussed include QNOC, Ethereal NOC, and SPIN NOC. The document provides an overview of research on improving performance and efficiency in NOC design.
Design and Implementation of JPEG CODEC using NoCIRJET Journal
This document describes the design and implementation of a JPEG codec using a Network-on-Chip (NoC) structure. It aims to speed up the image transfer process and provide shorter processing times. The key steps are:
1. The JPEG encoding process includes color space conversion, downsampling, block division, discrete cosine transform, quantization, and entropy coding to compress the image.
2. A NoC is used to transmit the compressed image data packets across the chip to reduce latency during transfer.
3. The JPEG decoding process reverses the encoding steps through entropy decoding, dequantization, inverse discrete cosine transform, and image reconstruction to decompress the image for viewing.
Design of an Efficient Communication Protocol for 3d Interconnection NetworkIJMTST Journal
Three-dimensional integrated circuits (3D ICs) provide better device integration, reduced signal delay and reduced interconnect power. They additionally give better layout flexibility by permitting heterogeneous integration, by taking the advantage of intrinsic capability of reducing the wire length in 3D ICs, 3D NOC Bus Hybrid mesh layout was suggested. This layout provides an apparently significant stage to implement economical multicast routings for 3D networks-on-chip. A unique multicast partitioning and routing strategy for the 3D NOC-Bus Hybrid mesh architectures to improve the system performance and to decrease the power consumption is being proposed. The planned design exploits the useful attribute of a single-hop (bus-based) interlayer communication of the 3D stacked mesh design to supply superior hardware multicast support. Finally customized partitioning approach and an effective routing method is given to decrease the average hop count and network latency. Compared to the recently designed 3D NOC architectures being capable of supporting hardware multicasting, huge simulations with traffic profiles reveals design exploitation, which is the planned multicast routing strategy will facilitate significant performance enhancements.
This document summarizes a research paper that analyzes different network-on-chip (NoC) topologies using computer simulations. The paper compares a standard 2D mesh topology to a proposed new topology in terms of the number of links, number of hops in the longest path, end-to-end delay, and throughput. Simulation results using the ns-2 network simulator show that the proposed topology reduces the number of links by 20% and the longest path by one hop, resulting in lower end-to-end delay and higher throughput compared to the standard 2D mesh topology. The paper concludes that optimizing NoC topology can reduce power consumption while maintaining performance.
Noise Tolerant and Faster On Chip Communication Using Binoc ModelIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
A Flexible Software/Hardware Adaptive Network for Embedded Distributed Archit...csijjournal
Embedded platforms are projected to integrate hundreds of cores in the near future, and expanding the interconnection network remains a key challenge. We propose SNet, a new Scalable NETwork paradigm that extends the NoCs area to include a software/hardware dynamic routing mechanism. To design routing pathways among communicating processes, it uses a distributed, adaptive, non-supervised routing method based on the ACO algorithm (Ant Colony Optimization). A small footprint hardware unit called DMC speeds up data transfer (Direct Management of Communications). SNet has the benefit of being extremely versatile, allowing for the creation of a broad range of routing topologies to meet the needs of various applications. We provide the DMC module in this work and assess SNet performance by executing a large number of test cases.
A FLEXIBLE SOFTWARE/HARDWARE ADAPTIVE NETWORK FOR EMBEDDED DISTRIBUTED ARCHIT...csijjournal
Embedded platforms are projected to integrate hundreds of cores in the near future, and expanding the
interconnection network remains a key challenge. We propose SNet, a new Scalable NETwork paradigm
that extends the NoCs area to include a software/hardware dynamic routing mechanism. To design routing
pathways among communicating processes, it uses a distributed, adaptive, non-supervised routing method
based on the ACO algorithm (Ant Colony Optimization). A small footprint hardware unit called DMC
speeds up data transfer (Direct Management of Communications). SNet has the benefit of being extremely
versatile, allowing for the creation of a broad range of routing topologies to meet the needs of various
applications. We provide the DMC module in this work and assess SNet performance by executing a large
number of test cases.
Many intellectual property (IP) modules are present in contemporary system on chips (SoCs). This could provide an issue with interconnection among different IP modules, which would limit the system's ability to scale. Traditional bus-based SoC architectures have a connectivity bottleneck, and network on chip (NoC) has evolved as an embedded switching network to address this issue. The interconnections between various cores or IP modules on a chip have a significant impact on communication and chip performance in terms of power, area latency and throughput. Also, designing a reliable fault tolerant NoC became a significant concern. In fault tolerant NoC it becomes critical to identify faulty node and dynamically reroute the packets keeping minimum latency. This study provides an insight into a domain of NoC, with intention of understanding fault tolerant approach based on the XY routing algorithm for 4×4 mesh architecture. The fault tolerant NoC design is synthesized on field programmable gate array (FPGA).
Network on Chip Architecture and Routing Techniques: A surveyIJRES Journal
This document summarizes research on Network on Chip (NOC) architecture and routing techniques. It discusses NOC topology options including mesh, torus, ring and irregular networks. It also reviews router architecture, switching techniques, virtual channels, buffering, error correction, quality of service implementations, and routing algorithms. Specific NOC implementations discussed include QNOC, Ethereal NOC, and SPIN NOC. The document provides an overview of research on improving performance and efficiency in NOC design.
Design and Implementation of JPEG CODEC using NoCIRJET Journal
This document describes the design and implementation of a JPEG codec using a Network-on-Chip (NoC) structure. It aims to speed up the image transfer process and provide shorter processing times. The key steps are:
1. The JPEG encoding process includes color space conversion, downsampling, block division, discrete cosine transform, quantization, and entropy coding to compress the image.
2. A NoC is used to transmit the compressed image data packets across the chip to reduce latency during transfer.
3. The JPEG decoding process reverses the encoding steps through entropy decoding, dequantization, inverse discrete cosine transform, and image reconstruction to decompress the image for viewing.
Design of an Efficient Communication Protocol for 3d Interconnection NetworkIJMTST Journal
Three-dimensional integrated circuits (3D ICs) provide better device integration, reduced signal delay and reduced interconnect power. They additionally give better layout flexibility by permitting heterogeneous integration, by taking the advantage of intrinsic capability of reducing the wire length in 3D ICs, 3D NOC Bus Hybrid mesh layout was suggested. This layout provides an apparently significant stage to implement economical multicast routings for 3D networks-on-chip. A unique multicast partitioning and routing strategy for the 3D NOC-Bus Hybrid mesh architectures to improve the system performance and to decrease the power consumption is being proposed. The planned design exploits the useful attribute of a single-hop (bus-based) interlayer communication of the 3D stacked mesh design to supply superior hardware multicast support. Finally customized partitioning approach and an effective routing method is given to decrease the average hop count and network latency. Compared to the recently designed 3D NOC architectures being capable of supporting hardware multicasting, huge simulations with traffic profiles reveals design exploitation, which is the planned multicast routing strategy will facilitate significant performance enhancements.
This document summarizes a research paper that analyzes different network-on-chip (NoC) topologies using computer simulations. The paper compares a standard 2D mesh topology to a proposed new topology in terms of the number of links, number of hops in the longest path, end-to-end delay, and throughput. Simulation results using the ns-2 network simulator show that the proposed topology reduces the number of links by 20% and the longest path by one hop, resulting in lower end-to-end delay and higher throughput compared to the standard 2D mesh topology. The paper concludes that optimizing NoC topology can reduce power consumption while maintaining performance.
Noise Tolerant and Faster On Chip Communication Using Binoc ModelIJMER
International Journal of Modern Engineering Research (IJMER) is Peer reviewed, online Journal. It serves as an international archival forum of scholarly research related to engineering and science education.
A Flexible Software/Hardware Adaptive Network for Embedded Distributed Archit...csijjournal
Embedded platforms are projected to integrate hundreds of cores in the near future, and expanding the interconnection network remains a key challenge. We propose SNet, a new Scalable NETwork paradigm that extends the NoCs area to include a software/hardware dynamic routing mechanism. To design routing pathways among communicating processes, it uses a distributed, adaptive, non-supervised routing method based on the ACO algorithm (Ant Colony Optimization). A small footprint hardware unit called DMC speeds up data transfer (Direct Management of Communications). SNet has the benefit of being extremely versatile, allowing for the creation of a broad range of routing topologies to meet the needs of various applications. We provide the DMC module in this work and assess SNet performance by executing a large number of test cases.
A FLEXIBLE SOFTWARE/HARDWARE ADAPTIVE NETWORK FOR EMBEDDED DISTRIBUTED ARCHIT...csijjournal
Embedded platforms are projected to integrate hundreds of cores in the near future, and expanding the
interconnection network remains a key challenge. We propose SNet, a new Scalable NETwork paradigm
that extends the NoCs area to include a software/hardware dynamic routing mechanism. To design routing
pathways among communicating processes, it uses a distributed, adaptive, non-supervised routing method
based on the ACO algorithm (Ant Colony Optimization). A small footprint hardware unit called DMC
speeds up data transfer (Direct Management of Communications). SNet has the benefit of being extremely
versatile, allowing for the creation of a broad range of routing topologies to meet the needs of various
applications. We provide the DMC module in this work and assess SNet performance by executing a large
number of test cases.
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
Design of Tele command SOC-IP by AES Cryptographic Method Using VHDLdbpublications
The goal of this project is to implement the (AES) encryption system using Verilog. To do this, several separate sections of the algorithm will be coded to work together towards the end goal of performing the correct encryption routines. A telecommand is a command sent to control a remote system or systems i.e not directly connected (e.g. via wires) to the place from which the telecommand is sent. The telecommand word is derived from tele = remote (Greek), and command = to entrust/order (Latin). Systems that need remote measurement and reporting of information of interest to the system designer or operator, require the counterpart of telecommand, telemetry. For a telecommand (TC) to be effective, it must be compiled into a pre-arranged format (which may follow a standard structure), modulated onto a carrier wave which is then transmitted with adequate power to the remote system. The remote system will then demodulates the digital signal from the carrier, decode the telecommand, and execute it.
Performance analysis and implementation of modified sdm based noc for mpsoc o...eSAT Journals
Abstract To meet todays demanding requirements lowpower consumption, high performance while maintaing flexibility and scalability,
system-On-Chip will combine several number of processors cores and other IPs with network-On-chip. To implement NoC based
MPSoC on an FPGA, NoCs should provide guaranteed services and be run-time reconfigurable. Current TDM and SDM based
NoCs takes more area and would not support run-time reconfiguration. This paper presents modified spatial division multiplexing
based NoC on FPGA, in this we have modified complex network interface and proposed flexible network interface and efficient
SDM based NoC.This architecture explored feasibility of connection requirements from IP cores during run-time.
Keywords: NoC, MPSoC, FPGA, NoCs, SDM Based NoC
HIGH PERFORMANCE ETHERNET PACKET PROCESSOR CORE FOR NEXT GENERATION NETWORKSijngnjournal
As the demand for high speed Internet significantly increasing to meet the requirement of large data transfers, real-time communication and High Definition ( HD) multimedia transfer over IP, the IP based network products architecture must evolve and change. Application specific processors require high
performance, low power and high degree of programmability is the limitation in many general processor based applications. This paper describes the design of Ethernet packet processor for system-on-chip (SoC) which performs all core packet processing functions, including segmentation and reassembly, packetization classification, route and queue management which will speedup switching/routing performance making it
more suitable for Next Generation Networks (NGN). Ethernet packet processor design can be configured for use with multiple projects targeted to a FPGA device the system is designed to support 1/10/20/40/100 Gigabit links with a speed and performance advantage. VHDL has been used to implement and simulated the required functions in FPGA
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
APPLYING GENETIC ALGORITHM TO SOLVE PARTITIONING AND MAPPING PROBLEM FOR MESH...ijcsit
This paper presents a genetic based approach to the partitioning and mapping of multicore SoC cores over a NoC system that uses mesh topology. The proposed algorithm performs the partitioning and mapping by reducing communication cost and minimizing power consumption by placing those intercommunicated cores as close as possible together. A program developed in C++ in which the provided specification of the multicore MPSoC system captures all data dependencies before any start of the design process. Experimental results of several multimedia benchmarks demonstrates that the genetic-based approach able to find different satisfied implementations to the problem of partitioning and mapping of MPSoC cores over mesh-based NoC system that satisfies design goals.
This document summarizes a research paper that proposes applying a genetic algorithm to solve the partitioning and mapping problem for mesh network-on-chip (NoC) systems. The genetic algorithm aims to reduce communication costs and power consumption by placing intercommunicating cores close together on the mesh topology. Experimental results on multimedia benchmarks show the genetic approach finds different solutions that satisfy design goals of partitioning and mapping multicore system-on-chip cores onto a mesh-based NoC.
A Survey on System-On-Chip Bus ProtocolsIRJET Journal
This document provides an overview of various on-chip bus protocols used in system-on-chips (SoCs) for communication between devices, including Inter-Integrated Circuit (I2C), Improved Inter-Integrated Circuit (I3C), Serial Peripheral Interface (SPI), Universal Asynchronous Receiver/Transmitter (UART), and Peripheral Component Interconnect Express (PCIe). It discusses the implementation and applications of these bus protocols, as well as enhancements like I3C that improve upon I2C. The document also reviews related work analyzing the implementation and comparison of bus protocols like I2C and SPI.
An octa core processor with shared memory and message-passingeSAT Journals
Abstract This being the era of fast, high performance computing, there is the need of having efficient optimizations in the processor architecture and at the same time in memory hierarchy too. Each and every day, the advancement of applications in communication and multimedia systems are compelling to increase number of cores in the main processor viz., dual-core, quad-core, octa-core and so on. But, for enhancing the overall performance of multi processor chip, there are stringent requirements to improve inter-core synchronization. Thus, a MPSoC with 8-cores supporting both message-passing and shared-memory inter-core communication mechanisms is implemented on Virtex 5 LX110T FPGA. Each core is based on MIPS III (Microprocessor without interlocked pipelined stages) ISA, handling only integer type instructions and having six-stage pipeline with data hazard detection unit and forwarding logic. The eight processing cores and one central shared memory core are inter connected using 3x3 2-D mesh topology based Network-on-chip (NoC) with virtual channel router. The router is four stage pipelined supporting DOR X-Y routing algorithm and with round robin arbitration technique. For verification and functionality test of above fully synthesized multi core processor, matrix multiplication operation is mapped onto the above said. Partitioning and scheduling of multiple multiplications and addition for each element of resultant matrix has been done accordingly among eight cores to get maximum throughput. All the codes for processor design are written in Verilog HDL. Keywords: MPSoC, message-passing, shared memory, MIPS, ISA, wormhole router, network-on-chip, SIMD, data level parallelism, 2-D Mesh, virtual channel
System on Chip is a an IC that integrates all the components of an electronic system. This presentation is based on the current trends and challenges in the IP based SOC design.
ETHERNET PACKET PROCESSOR FOR SOC APPLICATIONcscpconf
This document describes the design of an Ethernet packet processor for system-on-chip applications. The processor performs core packet processing functions like segmentation, reassembly, classification, and queue management to improve switching and routing performance. It has been implemented on an FPGA for 10/100/1000 Ethernet links. The design includes five VHDL modules with the core functionality in an aggregate module. It can identify packet fields, extract addresses and lengths, and check the CRC for errors. This packet processor is intended to offload tasks from the processor and accelerate functions like SFD detection and CRC calculation to improve the performance of next-generation IP network products like high-speed switches and routers.
Design and Performance Analysis of 8 x 8 Network on Chip RouterIRJET Journal
This document describes a study that designed and analyzed the performance of an 8x8 network-on-chip router. The researchers implemented a 2D mesh network-on-chip router with four ports connected in each of the four directions (north, south, east, west) and a fifth port connected to a local processing element. The goal was to improve quality-of-service by employing algorithms like wormhole routing, arbitration, and crossbar switching. The router architecture and modules were designed and synthesized using Xilinx ISE to optimize for lower power consumption while maintaining high throughput and quality-of-service.
This document outlines a research proposal on developing a congestion-aware adaptive routing protocol for an on-chip network. The objectives are to minimize congestion and enhance network performance by dynamically adjusting routing paths based on real-time network conditions. The proposal will involve implementing a congestion-aware adaptive routing algorithm using Verilog, gathering performance data from conventional and proposed algorithms, and analyzing results to optimize the routing protocol and network structure. The desired outcome is to improve latency and throughput in the on-chip network at low cost by exploiting adaptive routing.
Polar codes are one of the best linear block codes that are capacity achieving and incorporating along with it a simplified encoding and decoding routines. Successive cancellation (SC) algorithm is one of the predominantly used decoding algorithms due to its low complexity. It has broad scopes for hardware architecture design and reformulation. For polar code, the trade-off among the long latency and the silicon area of the SC algorithm is a bottleneck for the design of a high throughput polar decoder. The available prior SC polar decoder designs have higher area requirements for higher block length. This paper introduces a unique reformulation of the processing element (PE) block of SC decoding. The proposed reformulation leads to two benefits: firstly, critical path and hardware complexity of the PE are meaningfully reduced by using a unified adder block. Secondly, the silicon area requirement and the power consumption were also reduced considerably without any loss in performance. The proposed PE is used to build the decoder for various block lengths. Moreover, a Gate-level analysis of the proposed decoder has revealed that the design attains an 18% area reduction and 38% reduction in power consumption over the conventional one with similar performance.
Netlist Optimization for CMOS Place and Route in MICROWINDIRJET Journal
This document discusses netlist optimization for CMOS place and route in the MICROWIND tool. It presents an algorithm to rearrange the Verilog netlist generated in DSCH to optimize the layout generated in MICROWIND. The algorithm first extracts interconnect wire nodes from the netlist and calculates fan-out of each gate. It then rearranges the netlist by placing lines with the highest fan-out wires together to minimize interconnect length. Alternatively, it can rearrange the netlist by logic gate type to group similar gates together. Experimental results on circuits like an ADC show the optimized netlists reduce total area and number of metal layers compared to the original netlist. The optimization logic aims to generate more efficient layouts in MICROW
1. The document proposes using FPGA for data offloading in cloud datacenter networks to improve quality of service. It discusses how current high-performance processors are not keeping pace with required QoS and how FPGA can help balance workloads.
2. It reviews related works in cloud datacenter networking that have not considered using FPGA for acceleration and quality of service improvement. Most have focused on topology, architecture, flow scheduling, and virtualization but not FPGA-based acceleration.
3. The document argues that an FPGA-based spine-leaf model could be an alternative to traditional network models for enterprise applications like EETACP, offering benefits like lower latency, offloading, scalability, and
Cloud Based Datacenter Network Acceleration Using FPGA for Data-Offloading Onyebuchi nosiri
Currently, the high-performance processors in Spine-Leaf, Mesh, and Router layer-3 (SLMR-3) backend server domain have multiple cores, but data offloading from processor to the peripheral is not keeping pace with the required Quality of Service (QoS) needed to balance the workload on a Warehouse Scaled Computer (WSC) running a developed Enterprise Energy Tracking Analytic Cloud Portal (EETACP) data center network. High speed with low latency interconnects between the processors and Field Programmable Gate Array (FPGA) is critical for achieving performance benefits in EETACP deployment. Most of the servers in WSC architectures are running at average utilization rates and perform well under peak processing power. These servers are good candidates for FPGA processors in cloud-based data centers owing to its acceleration coherency. This paper made a strong case for cloudbased support for EETACP. An FPGA-based Spine-Leaf model is proposed to be an alternative to traditional network models for EETACP provisioning. The paper analyzed reconfigurable FPGAs, characterized a simplified process model for hyperscale FPGA cloud design description. To validate the performance, comparisons was made with two similar networks, namely DCell and BCube for enterprise application deployments. It was concluded that FPGA-based DCN acceleration for EETACP offers acceptable QoS expectations
FPGA IMPLEMENTATION OF PRIORITYARBITER BASED ROUTER DESIGN FOR NOC SYSTEMSIAEME Publication
An efficient Priority-Arbiter based Router is designed along with 2X2 and 3X3 mesh
topology based NOC architecture are designed. The Priority –Arbiter based Router
design includes Input registers, Priority arbiter, and XY- Routing algorithm. The
Priority-Arbiter based Router and NOC 2X2 and 3X3 Router designs are synthesized
and implemented using Xilinx ISE Tool and simulated using Modelsim6.5f. The
implementation is done by Artix-7 FPGA device, and the physically debugging of the
NOC 2X2 Router design is verified using Chipscope pro tool. The performance results
are analyzed in terms of the Area (Slices, LUT’s), Timing period, and Maximum
operating frequency. The comparison of the Priority-Arbiter based Router is made
concerning previous similar architecture with improvements.
FPGA IMPLEMENTATION OF PRIORITYARBITER BASED ROUTER DESIGN FOR NOC SYSTEMSIAEME Publication
An efficient Priority-Arbiter based Router is designed along with 2X2 and 3X3 mesh
topology based NOC architecture are designed. The Priority –Arbiter based Router
design includes Input registers, Priority arbiter, and XY- Routing algorithm. The
Priority-Arbiter based Router and NOC 2X2 and 3X3 Router designs are synthesized
and implemented using Xilinx ISE Tool and simulated using Modelsim6.5f. The
implementation is done by Artix-7 FPGA device, and the physically debugging of the
NOC 2X2 Router design is verified using Chipscope pro tool. The performance results
are analyzed in terms of the Area (Slices, LUT’s), Timing period, and Maximum
operating frequency. The comparison of the Priority-Arbiter based Router is made
concerning previous similar architecture with improvements.
This document proposes an artificial intelligence enabled routing (AIER) mechanism for software defined networking (SDN) that can alleviate issues with monitoring periods in dynamic routing and provide superior route decisions using artificial neural networks (ANNs). The key aspects of the proposed AIER mechanism are:
1) It installs three additional modules in the SDN control plane: a topology discovery module, a monitoring period module, and an ANN module.
2) The ANN module is trained to learn from past routing experiences and avoid ineffective route decisions.
3) Evaluation on the Mininet simulator shows the AIER mechanism improves performance metrics like average throughput, packet loss ratio, and packet delay compared to different monitoring periods in dynamic
In this study, machine learning is examined in relation to commercial machine learning's resilience to the COVID-19 pandemic-related crisis. Two approaches are used to assess the pandemic's impact on machine learning risk, as well as a method to prioritize sectors according to the crisis's potential negative consequences. I conducted the study to determine Santander machine learning's resilience. The data mining area offers prospects for COVID-19's future. A total of 13 machine learning demos were selected for its organization. The Hellweg strategy and the technique for order preference by similarity to ideal solution (TOPSIS) technique were utilized as direct request strategies. Parametric assessment of machine learning versatility in business was based on capital sufficiency, liquidity proportion, market benefits, and share in an arrangement of openings with a perceived disability, and affectability of machine learning's credit portfolio to monetary hazard. As a result of the COVID-19 pandemic, these enterprises were ranked according to their threat. Based on the findings of the research, machine learning worked the best for the pandemic. Meanwhile, machine learning suffered the most during the downturn. It can be seen, for example, in conversations about the impact of the pandemic on developing business sector soundness and managing financial framework solidity risk.
This document presents a blockchain-based framework for improving beef processing, distribution, and food safety management in Nigeria. The framework uses radio frequency identification (RFID) sensors to register livestock, farms, abattoirs, and track the processing steps. It also provides a centralized database to trace livestock data. Test results showed the model can process over 1,100 transactions per second for 2,500 users, and over 500 transactions per second for 5,000 users. Overall, the blockchain framework is intended to improve the efficiency and effectiveness of livestock traceability systems in Nigeria.
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
Design of Tele command SOC-IP by AES Cryptographic Method Using VHDLdbpublications
The goal of this project is to implement the (AES) encryption system using Verilog. To do this, several separate sections of the algorithm will be coded to work together towards the end goal of performing the correct encryption routines. A telecommand is a command sent to control a remote system or systems i.e not directly connected (e.g. via wires) to the place from which the telecommand is sent. The telecommand word is derived from tele = remote (Greek), and command = to entrust/order (Latin). Systems that need remote measurement and reporting of information of interest to the system designer or operator, require the counterpart of telecommand, telemetry. For a telecommand (TC) to be effective, it must be compiled into a pre-arranged format (which may follow a standard structure), modulated onto a carrier wave which is then transmitted with adequate power to the remote system. The remote system will then demodulates the digital signal from the carrier, decode the telecommand, and execute it.
Performance analysis and implementation of modified sdm based noc for mpsoc o...eSAT Journals
Abstract To meet todays demanding requirements lowpower consumption, high performance while maintaing flexibility and scalability,
system-On-Chip will combine several number of processors cores and other IPs with network-On-chip. To implement NoC based
MPSoC on an FPGA, NoCs should provide guaranteed services and be run-time reconfigurable. Current TDM and SDM based
NoCs takes more area and would not support run-time reconfiguration. This paper presents modified spatial division multiplexing
based NoC on FPGA, in this we have modified complex network interface and proposed flexible network interface and efficient
SDM based NoC.This architecture explored feasibility of connection requirements from IP cores during run-time.
Keywords: NoC, MPSoC, FPGA, NoCs, SDM Based NoC
HIGH PERFORMANCE ETHERNET PACKET PROCESSOR CORE FOR NEXT GENERATION NETWORKSijngnjournal
As the demand for high speed Internet significantly increasing to meet the requirement of large data transfers, real-time communication and High Definition ( HD) multimedia transfer over IP, the IP based network products architecture must evolve and change. Application specific processors require high
performance, low power and high degree of programmability is the limitation in many general processor based applications. This paper describes the design of Ethernet packet processor for system-on-chip (SoC) which performs all core packet processing functions, including segmentation and reassembly, packetization classification, route and queue management which will speedup switching/routing performance making it
more suitable for Next Generation Networks (NGN). Ethernet packet processor design can be configured for use with multiple projects targeted to a FPGA device the system is designed to support 1/10/20/40/100 Gigabit links with a speed and performance advantage. VHDL has been used to implement and simulated the required functions in FPGA
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
APPLYING GENETIC ALGORITHM TO SOLVE PARTITIONING AND MAPPING PROBLEM FOR MESH...ijcsit
This paper presents a genetic based approach to the partitioning and mapping of multicore SoC cores over a NoC system that uses mesh topology. The proposed algorithm performs the partitioning and mapping by reducing communication cost and minimizing power consumption by placing those intercommunicated cores as close as possible together. A program developed in C++ in which the provided specification of the multicore MPSoC system captures all data dependencies before any start of the design process. Experimental results of several multimedia benchmarks demonstrates that the genetic-based approach able to find different satisfied implementations to the problem of partitioning and mapping of MPSoC cores over mesh-based NoC system that satisfies design goals.
This document summarizes a research paper that proposes applying a genetic algorithm to solve the partitioning and mapping problem for mesh network-on-chip (NoC) systems. The genetic algorithm aims to reduce communication costs and power consumption by placing intercommunicating cores close together on the mesh topology. Experimental results on multimedia benchmarks show the genetic approach finds different solutions that satisfy design goals of partitioning and mapping multicore system-on-chip cores onto a mesh-based NoC.
A Survey on System-On-Chip Bus ProtocolsIRJET Journal
This document provides an overview of various on-chip bus protocols used in system-on-chips (SoCs) for communication between devices, including Inter-Integrated Circuit (I2C), Improved Inter-Integrated Circuit (I3C), Serial Peripheral Interface (SPI), Universal Asynchronous Receiver/Transmitter (UART), and Peripheral Component Interconnect Express (PCIe). It discusses the implementation and applications of these bus protocols, as well as enhancements like I3C that improve upon I2C. The document also reviews related work analyzing the implementation and comparison of bus protocols like I2C and SPI.
An octa core processor with shared memory and message-passingeSAT Journals
Abstract This being the era of fast, high performance computing, there is the need of having efficient optimizations in the processor architecture and at the same time in memory hierarchy too. Each and every day, the advancement of applications in communication and multimedia systems are compelling to increase number of cores in the main processor viz., dual-core, quad-core, octa-core and so on. But, for enhancing the overall performance of multi processor chip, there are stringent requirements to improve inter-core synchronization. Thus, a MPSoC with 8-cores supporting both message-passing and shared-memory inter-core communication mechanisms is implemented on Virtex 5 LX110T FPGA. Each core is based on MIPS III (Microprocessor without interlocked pipelined stages) ISA, handling only integer type instructions and having six-stage pipeline with data hazard detection unit and forwarding logic. The eight processing cores and one central shared memory core are inter connected using 3x3 2-D mesh topology based Network-on-chip (NoC) with virtual channel router. The router is four stage pipelined supporting DOR X-Y routing algorithm and with round robin arbitration technique. For verification and functionality test of above fully synthesized multi core processor, matrix multiplication operation is mapped onto the above said. Partitioning and scheduling of multiple multiplications and addition for each element of resultant matrix has been done accordingly among eight cores to get maximum throughput. All the codes for processor design are written in Verilog HDL. Keywords: MPSoC, message-passing, shared memory, MIPS, ISA, wormhole router, network-on-chip, SIMD, data level parallelism, 2-D Mesh, virtual channel
System on Chip is a an IC that integrates all the components of an electronic system. This presentation is based on the current trends and challenges in the IP based SOC design.
ETHERNET PACKET PROCESSOR FOR SOC APPLICATIONcscpconf
This document describes the design of an Ethernet packet processor for system-on-chip applications. The processor performs core packet processing functions like segmentation, reassembly, classification, and queue management to improve switching and routing performance. It has been implemented on an FPGA for 10/100/1000 Ethernet links. The design includes five VHDL modules with the core functionality in an aggregate module. It can identify packet fields, extract addresses and lengths, and check the CRC for errors. This packet processor is intended to offload tasks from the processor and accelerate functions like SFD detection and CRC calculation to improve the performance of next-generation IP network products like high-speed switches and routers.
Design and Performance Analysis of 8 x 8 Network on Chip RouterIRJET Journal
This document describes a study that designed and analyzed the performance of an 8x8 network-on-chip router. The researchers implemented a 2D mesh network-on-chip router with four ports connected in each of the four directions (north, south, east, west) and a fifth port connected to a local processing element. The goal was to improve quality-of-service by employing algorithms like wormhole routing, arbitration, and crossbar switching. The router architecture and modules were designed and synthesized using Xilinx ISE to optimize for lower power consumption while maintaining high throughput and quality-of-service.
This document outlines a research proposal on developing a congestion-aware adaptive routing protocol for an on-chip network. The objectives are to minimize congestion and enhance network performance by dynamically adjusting routing paths based on real-time network conditions. The proposal will involve implementing a congestion-aware adaptive routing algorithm using Verilog, gathering performance data from conventional and proposed algorithms, and analyzing results to optimize the routing protocol and network structure. The desired outcome is to improve latency and throughput in the on-chip network at low cost by exploiting adaptive routing.
Polar codes are one of the best linear block codes that are capacity achieving and incorporating along with it a simplified encoding and decoding routines. Successive cancellation (SC) algorithm is one of the predominantly used decoding algorithms due to its low complexity. It has broad scopes for hardware architecture design and reformulation. For polar code, the trade-off among the long latency and the silicon area of the SC algorithm is a bottleneck for the design of a high throughput polar decoder. The available prior SC polar decoder designs have higher area requirements for higher block length. This paper introduces a unique reformulation of the processing element (PE) block of SC decoding. The proposed reformulation leads to two benefits: firstly, critical path and hardware complexity of the PE are meaningfully reduced by using a unified adder block. Secondly, the silicon area requirement and the power consumption were also reduced considerably without any loss in performance. The proposed PE is used to build the decoder for various block lengths. Moreover, a Gate-level analysis of the proposed decoder has revealed that the design attains an 18% area reduction and 38% reduction in power consumption over the conventional one with similar performance.
Netlist Optimization for CMOS Place and Route in MICROWINDIRJET Journal
This document discusses netlist optimization for CMOS place and route in the MICROWIND tool. It presents an algorithm to rearrange the Verilog netlist generated in DSCH to optimize the layout generated in MICROWIND. The algorithm first extracts interconnect wire nodes from the netlist and calculates fan-out of each gate. It then rearranges the netlist by placing lines with the highest fan-out wires together to minimize interconnect length. Alternatively, it can rearrange the netlist by logic gate type to group similar gates together. Experimental results on circuits like an ADC show the optimized netlists reduce total area and number of metal layers compared to the original netlist. The optimization logic aims to generate more efficient layouts in MICROW
1. The document proposes using FPGA for data offloading in cloud datacenter networks to improve quality of service. It discusses how current high-performance processors are not keeping pace with required QoS and how FPGA can help balance workloads.
2. It reviews related works in cloud datacenter networking that have not considered using FPGA for acceleration and quality of service improvement. Most have focused on topology, architecture, flow scheduling, and virtualization but not FPGA-based acceleration.
3. The document argues that an FPGA-based spine-leaf model could be an alternative to traditional network models for enterprise applications like EETACP, offering benefits like lower latency, offloading, scalability, and
Cloud Based Datacenter Network Acceleration Using FPGA for Data-Offloading Onyebuchi nosiri
Currently, the high-performance processors in Spine-Leaf, Mesh, and Router layer-3 (SLMR-3) backend server domain have multiple cores, but data offloading from processor to the peripheral is not keeping pace with the required Quality of Service (QoS) needed to balance the workload on a Warehouse Scaled Computer (WSC) running a developed Enterprise Energy Tracking Analytic Cloud Portal (EETACP) data center network. High speed with low latency interconnects between the processors and Field Programmable Gate Array (FPGA) is critical for achieving performance benefits in EETACP deployment. Most of the servers in WSC architectures are running at average utilization rates and perform well under peak processing power. These servers are good candidates for FPGA processors in cloud-based data centers owing to its acceleration coherency. This paper made a strong case for cloudbased support for EETACP. An FPGA-based Spine-Leaf model is proposed to be an alternative to traditional network models for EETACP provisioning. The paper analyzed reconfigurable FPGAs, characterized a simplified process model for hyperscale FPGA cloud design description. To validate the performance, comparisons was made with two similar networks, namely DCell and BCube for enterprise application deployments. It was concluded that FPGA-based DCN acceleration for EETACP offers acceptable QoS expectations
FPGA IMPLEMENTATION OF PRIORITYARBITER BASED ROUTER DESIGN FOR NOC SYSTEMSIAEME Publication
An efficient Priority-Arbiter based Router is designed along with 2X2 and 3X3 mesh
topology based NOC architecture are designed. The Priority –Arbiter based Router
design includes Input registers, Priority arbiter, and XY- Routing algorithm. The
Priority-Arbiter based Router and NOC 2X2 and 3X3 Router designs are synthesized
and implemented using Xilinx ISE Tool and simulated using Modelsim6.5f. The
implementation is done by Artix-7 FPGA device, and the physically debugging of the
NOC 2X2 Router design is verified using Chipscope pro tool. The performance results
are analyzed in terms of the Area (Slices, LUT’s), Timing period, and Maximum
operating frequency. The comparison of the Priority-Arbiter based Router is made
concerning previous similar architecture with improvements.
FPGA IMPLEMENTATION OF PRIORITYARBITER BASED ROUTER DESIGN FOR NOC SYSTEMSIAEME Publication
An efficient Priority-Arbiter based Router is designed along with 2X2 and 3X3 mesh
topology based NOC architecture are designed. The Priority –Arbiter based Router
design includes Input registers, Priority arbiter, and XY- Routing algorithm. The
Priority-Arbiter based Router and NOC 2X2 and 3X3 Router designs are synthesized
and implemented using Xilinx ISE Tool and simulated using Modelsim6.5f. The
implementation is done by Artix-7 FPGA device, and the physically debugging of the
NOC 2X2 Router design is verified using Chipscope pro tool. The performance results
are analyzed in terms of the Area (Slices, LUT’s), Timing period, and Maximum
operating frequency. The comparison of the Priority-Arbiter based Router is made
concerning previous similar architecture with improvements.
This document proposes an artificial intelligence enabled routing (AIER) mechanism for software defined networking (SDN) that can alleviate issues with monitoring periods in dynamic routing and provide superior route decisions using artificial neural networks (ANNs). The key aspects of the proposed AIER mechanism are:
1) It installs three additional modules in the SDN control plane: a topology discovery module, a monitoring period module, and an ANN module.
2) The ANN module is trained to learn from past routing experiences and avoid ineffective route decisions.
3) Evaluation on the Mininet simulator shows the AIER mechanism improves performance metrics like average throughput, packet loss ratio, and packet delay compared to different monitoring periods in dynamic
In this study, machine learning is examined in relation to commercial machine learning's resilience to the COVID-19 pandemic-related crisis. Two approaches are used to assess the pandemic's impact on machine learning risk, as well as a method to prioritize sectors according to the crisis's potential negative consequences. I conducted the study to determine Santander machine learning's resilience. The data mining area offers prospects for COVID-19's future. A total of 13 machine learning demos were selected for its organization. The Hellweg strategy and the technique for order preference by similarity to ideal solution (TOPSIS) technique were utilized as direct request strategies. Parametric assessment of machine learning versatility in business was based on capital sufficiency, liquidity proportion, market benefits, and share in an arrangement of openings with a perceived disability, and affectability of machine learning's credit portfolio to monetary hazard. As a result of the COVID-19 pandemic, these enterprises were ranked according to their threat. Based on the findings of the research, machine learning worked the best for the pandemic. Meanwhile, machine learning suffered the most during the downturn. It can be seen, for example, in conversations about the impact of the pandemic on developing business sector soundness and managing financial framework solidity risk.
This document presents a blockchain-based framework for improving beef processing, distribution, and food safety management in Nigeria. The framework uses radio frequency identification (RFID) sensors to register livestock, farms, abattoirs, and track the processing steps. It also provides a centralized database to trace livestock data. Test results showed the model can process over 1,100 transactions per second for 2,500 users, and over 500 transactions per second for 5,000 users. Overall, the blockchain framework is intended to improve the efficiency and effectiveness of livestock traceability systems in Nigeria.
Diabetic retinopathy (DR) is one of the most common causes of blindness. The necessity for a robust and automated DR screening system for regular examination has long been recognized in order to identify DR at an early stage. In this paper, an embedded DR diagnosis system based on convolutional neural networks (CNNs) has been proposed to assess the proper stage of DR. We coupled the power of CNN with transfer learning to design our model based on state-of-the-art architecture. We preprocessed the input data, which is color fundus photography, to reduce undesirable noise in the image. After training many models on the dataset, we chose the adopted ResNet50 because it produced the best results, with a 92.90% accuracy. Extensive experiments and comparisons with other research work show that the proposed method is effective. Furthermore, the CNN model has been implemented on an embedded target to be a part of a medical instrument diagnostic system. We have accelerated our model inference on a field programmable gate array (FPGA) using Xilinx tools. Results have confirmed that a customized FPGA system on chip (SoC) with hardware accelerators is a promising target for our DR detection model with high performance and low power consumption.
This document describes the design and evaluation of a serious game about Covid-19. The game aims to educate players on how to strengthen their immune system to fight coronavirus infection through diet. Researchers developed a prototype where the human body is represented as a castle, with the objective to defeat the coronavirus enemy before it spreads. According to a study of 80 students, 92% appreciated the scenario and game mechanics. The game was designed with learning objectives around immune system function and recommended dietary strategies to support immunity.
The need for automated speech recognition has expanded as a result of significant industrial expansion for a variety of automation and humanmachine interface applications. The speech impairment brought on by communication disorders, neurogenic speech disorders, or psychological speech disorders limits the performance of different artificial intelligencebased systems. The dysarthric condition is a neurogenic speech disease that restricts the capacity of the human voice to articulate. This article presents a comprehensive survey of the recent advances in the automatic dysarthric speech recognition (DSR) using machine learning (ML) and deep learning (DL) paradigms. It focuses on the methodology, database, evaluation metrics, and major findings from the study of previous approaches. From the literature survey it provides the gaps between exiting work and previous work on DSR and provides the future direction for improvement of DSR. The performance of the various machine and DL schemes is evaluated for the DSR on UASpeech dataset based on accuracy, precision, recall, and F1- score. It is observed that the DL based DSR schems outperforms the ML based DSR schemes.
In this work, an internet of things (IoT) sensing and monitoring box has been developed. The proposed low-cost system is a portable device for smart buildings to measure vibrations, monitor, and control noise caused by the industrial machines. We will present an instrument and a method to measure the vibration and tilt of a mechanical system (air conditioner). The primary goal is to create a signal acquisition and monitoring system that is both userfriendly and affordable, while also delivering exceptional precision. The key concept is centered around acquiring and processing signals through the Raspberry Pi. We will use for the first time as an application, which does not exist before, a conversion method to control and monitor remotely the noise generated by the machines. Once the noise reaches a high value or the air conditioner is too much tilted, the system sends an alert in the form of an email. We will use the Python language to acquire and process the signal and send the alerts. The proposed approach is straightforward to implement, and the obtained results demonstrate a high level of accuracy that is consistent with the existing literature.
The use of a convolutional neural network (CNN) to analyze and classify electroencephalogram (EEG) signals has recently attracted the interest of researchers to identify epileptic seizures. This success has come with an enormous increase in the computational complexity and memory requirements of CNNs. For the sake of boosting the performance of CNN inference, several hardware accelerators have been proposed. The high performance and flexibility of the field programmable gate array (FPGA) make it an efficient accelerator for CNNs. Nevertheless, for resource-limited platforms, the deployment of CNN models poses significant challenges. For an ease of CNN implementation on such platforms, several tools and frameworks have been made available by the research community along with different optimization techniques. In this paper, we proposed an FPGA implementation for an automatic seizure detection approach using two CNN models, namely VGG-16 and ResNet-50. To reduce the model size and computation cost, we exploited two optimization approaches: pruning and quantization. Furthermore, we presented the results and discussed the advantages and limitations of two implementation alternatives for the inference acceleration of quantized CNNs on Zynq-7000: an advanced RISC machine (ARM) software implementation-based ARM, NN, software development kit (SDK) and a software/hardware implementation-based deep learning processor unit (DPU) accelerator and DNNDK toolkit.
A number of benefits have been reported for computer-based assessments over traditional paper-based exams, both in terms of IT support for question development, reduced distribution and test administration costs, and automated support. Possible for the ranking. However, existing computerized assessment systems do not provide all kinds of questions, namely open questions that require writing solutions. To overcome the challenges of the existing, the objective of this work is to achieve an intelligent evaluation system (IES) responding to the problems identified, and which adapts to the different types of questions, especially open-ended questions of which the answer requires sentence writing or programming.
Convolutional neural networks (CNN) trained using deep learning (DL) have advanced dramatically in recent years. Researchers from a variety of fields have been motivated by the success of CNNs in computer vision to develop better CNN models for use in other visually-rich settings. Successes in image classification and research have been achieved in a wide variety of domains throughout the past year. Among the many popularized image classification techniques, the detection of plant leaf diseases has received extensive research. As a result of the nature of the procedure, image quality is often degraded and distortions are introduced during the capturing of the image. In this study, we look into how various CNN models are affected by distortions. Corn-maze leaf photos from the 4,188-image corn or maize leaf Dataset (split into four categories) are under consideration. To evaluate how well they handle noise and blur, researchers have deployed pre-trained deep CNN models like visual geometry group (VGG), InceptionV3, ResNet50, and EfficientNetB0. Classification accuracy and metrics like as recall and f1-score are used to evaluate CNN performance.
In this research, we present a low phase noise (PN) and wide tuning range 175 GHz inductors and capacitors (LC) voltage-controlled oscillator (VCO) based on a differential Colpitts oscillator that was designed using a 0.13 μm bipolar complementary metal oxide semiconductor (BiCMOS) and simulated. The square of the tank Q-factor and the square of the oscillation amplitude were both maximized to reduce PN. With an extensive examination of parasitic, mathematical analysis of load impedances, and implementation of differential design, the PN was reduced, and the output power was enhanced. Using a supply voltage of 1.6 V, the VCO consumes 41.9 mA, resulting in a total power usage of 67 mW to prevent undesirable PN deterioration, an inter-stage LC filter at the VCO-buffer interface increases the swing at the buffer input. To make a better output, a buffer is used to isolate the load from the VCO core. In addition, the VCO has a high linearity and the overall, the VCO presented in this study demonstrates excellent performance and has the potential to be used in a wide range of applications that require a high-performance, low-power VCO.
Diseases in edible and industrial plants remains a major concern, affecting producers and consumers. The problem is further exacerbated as there are different species of plants with a wide variety of diseases that reduce the effectiveness of certain pesticides while increasing our risk of illness. A timely, accurate and automated detection of diseases can be beneficial. Our work focuses on evaluating deep learning (DL) approaches using transfer learning to automatically detect diseases in plants. To enhance the capabilities of our approach, we compiled a novel image dataset containing 87,570 records encompassing 32 different plants and 74 types of diseases. The dataset consists of leaf images from both laboratory setups and cultivation fields, making it more representative. To the best of our knowledge, no such datasets have been used for DL models. Four pretrained computer vision models, namely VGG-16, VGG-19, ResNet-50, and ResNet-101 were evaluated on our dataset. Our experiments demonstrate that both VGG-16 and VGG-19 models proved more efficient, yielding an accuracy of approximately 86% and a f1-score of 87%, as compared to ResNet-50 and ResNet-101. ResNet-50 attains an accuracy and a f1-score of 46.9% and 45.6%, respectively, while ResNet-101 reaches an accuracy of 40.7% and a f1-score of 26.9%.
In this proposed work, we identified the significant research issues on lung cancer risk factors. Capturing and defining symptoms at an early stage is one of the most difficult phases for patients. Based on the history of patients records, we reviewed a number of current research studies on lung cancer and its various stages. We identified that lung cancer is one of the significant research issues in predicting the early stages of cancer disease. This research aimed to develop a model that can detect lung cancer with a remarkably high level of accuracy using the deep learning approach (convolution neural network). This method considers and resolves significant gaps in previous studies. We compare the accuracy levels and loss values of our model with VGG16, InceptionV3, and Resnet50. We found that our model achieved an accuracy of 94% and a minimum loss of 0.1%. Hence physicians can use our convolution neural network models for predicting lung cancer risk factors in the real world. Moreover, this investigation reveals that squamous cell carcinoma, normal, adenocarcinoma, and large cell carcinoma are the most significant risk factors. In addition, the remaining attributes are also crucial for achieving the best performance.
Wirelessly based security applications have exploded as a result of modern technology. To build and/or implement security access control systems, many types of wireless communication technologies have been deployed. quick response (QR code) is a contactless technology that is extensively utilised in a variety of sectors, including access control, library book tracking, supply chains, and tollgate systems, among others. This paper combines QR code technology with Arduino and Python to construct an automated QR code-based access management system. After detecting a QR code, the QR scanner at the entry collects and compares the user's unique identifier (UID) with the UID recorded in the system. The results show that this system is capable of granting or denying access to a protected environment in a timely, effective, and reliable way. Security systems can protect physical and intellectual property by preventing unauthorized persons from entering the area. Many door locks, such as mechanical and electrical locks, were created to meet basic security needs but it also helps to create a data files structure of the authorized persons.
Localization is a critical concern in many wireless sensor network (WSN) applications. Furthermore, correct information regarding the geographic placements of nodes (sensors) is critical for making the collected data valuable and relevant. Because of their benefits, such as simplicity and acceptable accuracy, the based connectivity algorithms attempt to localize multi-hop WSN. However, due to environmental factors, the precision of localisation may be rather low. This publication describes an extreme learning machine (ELM) technique for minimizing localization error in range-free WSN. In this paper, we propose a Cascade-ELM to increase localization accuracy in range-free WSNs. We tested the proposed approaches in a variety of multi-hop WSN scenarios. Our research focused on an isotropic and irregular environment. The simulation results show that the proposed Cascade-ELM algorithm considerably improves localization accuracy when compared to previous algorithms derived from smart computing approaches. When compared to previous work, isotropic environments show improved localization results.
The study evaluated interference in a dense heterogeneous network using third-generation universal mobile telecommunication systems (UMTS) and fourth-generation long term evolution (LTE) networks LTE. The UMTs/LTE heterogeneous network determines the level of interference when the two communication systems coexist and how to improve the network by migrating from UMTs to LTE, which has a faster download speed and larger capacity. Techno lite 8 on third generation (3G) and Infinix Pro 6 on fourth generation (4G) were used to measure network the received signal strength (RSS) during site investigation. UE interference was detected and traced using a spectrum analyzer. UMTS and LTE path loss exponents are 2.6 and 3.2. Shannon's capacity theorem calculated LTE and UMTS capacity. When signal to interference and noise ratio (SINR) was used as a quality of service (QoS) indicator, MATLAB channel capacity plots did not match Shannon's due to neighboring interference. UMTS had an R2 of 0.54 and LTE 0.57 for the Shannon channel capacity equation. Adjacent channel interference (ACI) user devices reduce network capacity, lowering QoS for other customers.
The course activity log is where a learning management system (LMS) like Moodle keeps track of the various learning activities. The instructor may directly examine the log or use more complex method such as data mining to conduct a quicker and more in-depth examination of the student's behaviors. Most previous studies on analyzing this log data rely on predictive analysis. Instead of predictive analysis, this study investigates cluster analysis and association analysis. Cluster analysis based on k-means++ is utilized to organize students into groups, given their engagement in the learning course module. Association analysis based on apriori is utilized to extract the relationships between various student activities. A dashboard presentation of the findings is provided to facilitate clearer comprehension. Based on the analysis findings, it can be concluded that the structure of the student cluster is medium. In contrast, the association between student activities is positively correlated and well-balanced. The subjective review of the dashboard reveals that the visualization is already sufficient, but there are some recommendations for making it even better.
The software-defined network (SDN) controller adds and removes the contents of the flow table through secure channels to determine how packets are processed and how the flow table is managed. The controller pays attention to network intelligence and becomes the middle part, where the network manages the transfer data of the aircraft delivered via the OpenFlow (OF) switch. To this end, the controller provides an interface for managing, controlling, and managing this switch flow table. Run tests to calculate controller throughput and latency levels and test using the cbance tool, which can test transmission control protocol (TCP) and user datagram protocol (UDP) protocols. The tests are run by forcing the controller to run at maximum without any additional settings (default settings) in order to use the correct information about the controller’s capabilities. Because of this need, you need to test the performance of your controller. In this study, the tests were run on three popular controllers. Test results show that flowed controllers are more stable than open network operating dystem (ONOS) and open daylight (ODL) controllers in managing switch and host loads.
This document discusses the impact of e-government implementation on achieving Saudi Arabia's vision 2030 to become an international logistics center. It focuses on four key areas: transforming Saudi Arabia into a logistics center through improving transportation infrastructure; increasing opportunities for living throughout the kingdom; promoting long-term financial sustainability; and the role of e-government in the Ministry of Transport. The document analyzes the current state of Saudi Arabia's transportation sector, including air, road, and sea transport. It also examines the elements needed to improve logistics, such as Saudi Arabia's strategic geographic location. The study finds that implementing e-government can help achieve vision 2030 goals by improving government services, engagement, and supply chain transparency in the transportation
Chronic disease (CD) such as kidney disease and causes severe challenging issues to the people all around the world. Chronic kidney disease (CKD) and diabetes mellitus (DM) are considered in this paper. Predicting the diseases in earlier stage, gives better preventive measures to the people. Healthcare domain leads to tremendous cost savings and improved health status of the society. The main objective of this paper is to develop an algorithm to predict CKD occurrence using machine learning (ML) technique. The commonly used classification algorithms namely logistic regression (LR), random forest (RF), conditional random forest (CRF), and recurrent neural networks (RNN) are considered to predict the disease at an earlier stage. The proposed algorithm in this paper uses medical code data to predict disease at an earlier stage.
Suppression of noise in noisy speech signal is required in many speech enhancement applications like signal recording and transmission from one place to other. In this paper a novel single line noise cancellation system is proposed using derivative of normalized least mean spare algorithm. The proposed system has two phases. The first phase is generation of secondary reference signal from incoming primary signal itself at initial silence period and pause between two words, which is essential while adaptive filter using as noise canceller. Second phase is noise cancellation using proposed modified error data normalized step size (EDNSS) algorithm. The performance of the proposed algorithm is compared with normalized least mean square (NLMS) algorithm and original EDNSS algorithm using standard IEEE sentence (SP23) of Noizeus data base with different types of real-world noise at different level of signal to noise ratio (SNR). The output of proposed, NLMS and EDNSS algorithm are measured with output SNR, excessive mean square error (EMSE) and misadjustment (M). The results clearly illustrates that the proposed algorithm gives improved result over conventional NLMS and EDNSS algorithm. The speed of convergence is also maintained as same conventional NLMS algorithm.
Harnessing WebAssembly for Real-time Stateless Streaming PipelinesChristina Lin
Traditionally, dealing with real-time data pipelines has involved significant overhead, even for straightforward tasks like data transformation or masking. However, in this talk, we’ll venture into the dynamic realm of WebAssembly (WASM) and discover how it can revolutionize the creation of stateless streaming pipelines within a Kafka (Redpanda) broker. These pipelines are adept at managing low-latency, high-data-volume scenarios.
Using recycled concrete aggregates (RCA) for pavements is crucial to achieving sustainability. Implementing RCA for new pavement can minimize carbon footprint, conserve natural resources, reduce harmful emissions, and lower life cycle costs. Compared to natural aggregate (NA), RCA pavement has fewer comprehensive studies and sustainability assessments.
Literature Review Basics and Understanding Reference Management.pptxDr Ramhari Poudyal
Three-day training on academic research focuses on analytical tools at United Technical College, supported by the University Grant Commission, Nepal. 24-26 May 2024
Advanced control scheme of doubly fed induction generator for wind turbine us...IJECEIAES
This paper describes a speed control device for generating electrical energy on an electricity network based on the doubly fed induction generator (DFIG) used for wind power conversion systems. At first, a double-fed induction generator model was constructed. A control law is formulated to govern the flow of energy between the stator of a DFIG and the energy network using three types of controllers: proportional integral (PI), sliding mode controller (SMC) and second order sliding mode controller (SOSMC). Their different results in terms of power reference tracking, reaction to unexpected speed fluctuations, sensitivity to perturbations, and resilience against machine parameter alterations are compared. MATLAB/Simulink was used to conduct the simulations for the preceding study. Multiple simulations have shown very satisfying results, and the investigations demonstrate the efficacy and power-enhancing capabilities of the suggested control system.
Electric vehicle and photovoltaic advanced roles in enhancing the financial p...IJECEIAES
Climate change's impact on the planet forced the United Nations and governments to promote green energies and electric transportation. The deployments of photovoltaic (PV) and electric vehicle (EV) systems gained stronger momentum due to their numerous advantages over fossil fuel types. The advantages go beyond sustainability to reach financial support and stability. The work in this paper introduces the hybrid system between PV and EV to support industrial and commercial plants. This paper covers the theoretical framework of the proposed hybrid system including the required equation to complete the cost analysis when PV and EV are present. In addition, the proposed design diagram which sets the priorities and requirements of the system is presented. The proposed approach allows setup to advance their power stability, especially during power outages. The presented information supports researchers and plant owners to complete the necessary analysis while promoting the deployment of clean energy. The result of a case study that represents a dairy milk farmer supports the theoretical works and highlights its advanced benefits to existing plants. The short return on investment of the proposed approach supports the paper's novelty approach for the sustainable electrical system. In addition, the proposed system allows for an isolated power setup without the need for a transmission line which enhances the safety of the electrical network
We have compiled the most important slides from each speaker's presentation. This year’s compilation, available for free, captures the key insights and contributions shared during the DfMAy 2024 conference.
CHINA’S GEO-ECONOMIC OUTREACH IN CENTRAL ASIAN COUNTRIES AND FUTURE PROSPECTjpsjournal1
The rivalry between prominent international actors for dominance over Central Asia's hydrocarbon
reserves and the ancient silk trade route, along with China's diplomatic endeavours in the area, has been
referred to as the "New Great Game." This research centres on the power struggle, considering
geopolitical, geostrategic, and geoeconomic variables. Topics including trade, political hegemony, oil
politics, and conventional and nontraditional security are all explored and explained by the researcher.
Using Mackinder's Heartland, Spykman Rimland, and Hegemonic Stability theories, examines China's role
in Central Asia. This study adheres to the empirical epistemological method and has taken care of
objectivity. This study analyze primary and secondary research documents critically to elaborate role of
china’s geo economic outreach in central Asian countries and its future prospect. China is thriving in trade,
pipeline politics, and winning states, according to this study, thanks to important instruments like the
Shanghai Cooperation Organisation and the Belt and Road Economic Initiative. According to this study,
China is seeing significant success in commerce, pipeline politics, and gaining influence on other
governments. This success may be attributed to the effective utilisation of key tools such as the Shanghai
Cooperation Organisation and the Belt and Road Economic Initiative.
6th International Conference on Machine Learning & Applications (CMLA 2024)ClaraZara1
6th International Conference on Machine Learning & Applications (CMLA 2024) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of on Machine Learning & Applications.
DEEP LEARNING FOR SMART GRID INTRUSION DETECTION: A HYBRID CNN-LSTM-BASED MODELgerogepatton
As digital technology becomes more deeply embedded in power systems, protecting the communication
networks of Smart Grids (SG) has emerged as a critical concern. Distributed Network Protocol 3 (DNP3)
represents a multi-tiered application layer protocol extensively utilized in Supervisory Control and Data
Acquisition (SCADA)-based smart grids to facilitate real-time data gathering and control functionalities.
Robust Intrusion Detection Systems (IDS) are necessary for early threat detection and mitigation because
of the interconnection of these networks, which makes them vulnerable to a variety of cyberattacks. To
solve this issue, this paper develops a hybrid Deep Learning (DL) model specifically designed for intrusion
detection in smart grids. The proposed approach is a combination of the Convolutional Neural Network
(CNN) and the Long-Short-Term Memory algorithms (LSTM). We employed a recent intrusion detection
dataset (DNP3), which focuses on unauthorized commands and Denial of Service (DoS) cyberattacks, to
train and test our model. The results of our experiments show that our CNN-LSTM method is much better
at finding smart grid intrusions than other deep learning algorithms used for classification. In addition,
our proposed approach improves accuracy, precision, recall, and F1 score, achieving a high detection
accuracy rate of 99.50%.
Presentation of IEEE Slovenia CIS (Computational Intelligence Society) Chapte...University of Maribor
Slides from talk presenting:
Aleš Zamuda: Presentation of IEEE Slovenia CIS (Computational Intelligence Society) Chapter and Networking.
Presentation at IcETRAN 2024 session:
"Inter-Society Networking Panel GRSS/MTT-S/CIS
Panel Session: Promoting Connection and Cooperation"
IEEE Slovenia GRSS
IEEE Serbia and Montenegro MTT-S
IEEE Slovenia CIS
11TH INTERNATIONAL CONFERENCE ON ELECTRICAL, ELECTRONIC AND COMPUTING ENGINEERING
3-6 June 2024, Niš, Serbia
ACEP Magazine edition 4th launched on 05.06.2024Rahul
This document provides information about the third edition of the magazine "Sthapatya" published by the Association of Civil Engineers (Practicing) Aurangabad. It includes messages from current and past presidents of ACEP, memories and photos from past ACEP events, information on life time achievement awards given by ACEP, and a technical article on concrete maintenance, repairs and strengthening. The document highlights activities of ACEP and provides a technical educational article for members.
1. International Journal of Informatics and Communication Technology (IJ-ICT)
Vol. 12, No. 3, December 2023, pp. 225~235
ISSN: 2252-8776, DOI: 10.11591/ijict.v12i3.pp225-235 225
Journal homepage: http://ijict.iaescore.com
2D router chip design, analysis, and simulation for effective
communication
Prateek Agarwal1
, Tanuj Kumar Garg1
, Adesh Kumar2
1
Department of Electronics and Communication Engineering, Faculty of Engineering and Technology, Gurukula Kangri (Deemed to be
University), Haridwar, India
2
Department of Electrical and Electronics Engineering, School of Engineering, University of Petroleum and Energy Studies,
Dehradun, India
Article Info ABSTRACT
Article history:
Received Oct 2, 2022
Revised Nov 28, 2022
Accepted Mar 4, 2023
The router is a network device that is used to connect subnetwork and
packet-switched networking by directing the data packets to the intended IP
addresses. It succeeds the traffic between different systems and allows
several devices to share the internet connection. The router is applicable for
the effective commutation in system on chip (SoC) modules for network on
chip (NoC) communication. The research paper emphasizes the design of the
two dimensional (2D) router hardware chip in the Xilinx integrated system
environment (ISE) 14.7 software and further logic verification using the data
packets transmitted from all input/output ports. The design evaluation is
done based on the pre-synthesis device utilization summary relating to
different field programmable gate array (FPGA) boards such as Spartan-3E
(XC3S500E), Spartan-6 (XC6SLX45), Virtex-4 (XC4VFX12), Virtex-5
(XC5VSX50T), and Virtex-7 (XC7VX550T). The 64-bit data logic is
verified on the different ports of the router configuration in the Xilinx and
Modelsim waveform simulator. The Virtex-7 has proven the fast-switching
speed and optimal hardware parameters in comparison to other FPGAs.
Keywords:
Data packets
Field programmable gate array
Network on chip router
Simulation
Xilinx integrated system
environment
This is an open access article under the CC BY-SA license.
Corresponding Author:
Adesh Kumar
Department of Electrical and Electronics Engineering, School of Engineering
University of Petroleum and Energy Studies
Dehradun, India
Email: adeshmanav@gmail.com
1. INTRODUCTION
Network on chip (NoC) [1] has grown in prominence as various communication infrastructures have
expanded. Other communication designs had been used in the past, but as core counts increased, these
architectures turned out to be a bottleneck for upcoming systems on chips (SoCs) because they limited
scalability, reusability, and difficulty. In the age of technology, the very large scale integration (VLSI)
industry found a model known as SoC [2] and later uncovered many flaws in it, including underutilization of
cores, low reusability, enormous complexity, and restricted scalability have been discovered a novel model
termed NoC addresses the shortcomings of SoC. Individual effective on-chip communication design for SoC
is called NoC. On a single chip, integrated circuits (IC) house multiple central processing unit (CPU) cores,
memory, hardware cores, and analog components. In great capacity and high-end uses like aerospace,
multimedia and defense, wireless, and wired communication schemes, these SoC are frequently employed
[3]. Additional processors are uniting on a particular die as an IC technology scales and creating
multiprocessor systems on chips (MPSoC).
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226
The MPSoC technology is used to integrate complicated heterogeneous systems into a distinct chip
and to allow on-chip communication. The processor elements of the MPSoC communicate using a variety of
bus structures and communication methods. In terms of cost, performance, frequency of operation, and power
requirements, the bus-based communication system is not a scalable architecture or a solution for future SoC
design engineers [4]. The answer to the issues facing the semiconductor industry is NoC, which can meet the
increased transistor packing density, cost, greater operating frequency, performance, and shorter time to
market.
NoC is the system version of MPSoC that has been confirmed to be a unique and effective method
for utilizing interconnections, and it inter-exchanges data among numerous nodes unified on a distinct chip.
In the design of an NoC architecture, topology, switching, and routing techniques are critical. The NoC can
be built and organized using different topologies in terms of the core and router computer architecture, as
well as the processes required to implement the flow management, switching, and routing strategy. Data flow
control is concerned with the quantity of data transportation or strength in the channels and routers. Routing
is a methodology for defining the greatest pathway for the data and messages from the communicating device
to the proposed end or the receiver. The two dimensional (2D) mesh NoC is a typical NoC architecture due to
system scalability and the use of a simple routing approach. Long-distance traffic, on the other hand, may
have severe broadcast dormancy. According to Pang et al. [5], star-type NoC has been used for long-distance
transportation to pass through a second-level network. In the design of a NoC, the routing procedure is the
content of the network layer. It is the most important factor that affects NoC network communications.
Small area communication or local area networks (LAN) are found to be suited for 2D-NoC
architecture, whereas big area networks are not. The higher number of nodes can be considered while
conducting a study as part of this ongoing endeavor. When transferring data across nodes, additional features
like data security through encryption and decryption can be used. If we can combine system safety measures
with via-node data transmission, it will be appropriate for broad communication systems and wireless data
transfer. Every electronic device nowadays, from a little mobile phone to a satellite, contains SoC. The SoC
has evolved quickly throughout time and is still processing information quickly. However, the devices are
scaling down quickly because of the tremendous growth of the semiconductor industry. As a result, today's
SoC is communication-centric. However, due to their inability to keep up with the rate at which devices are
being scaled down, the present bus designs, which consist of wires for worldwide interconnection in SoC
scheme, are experiencing proposal emergencies. NoC is a developing pattern that is quickly rising to the top
of the competition to replace traditional bus designs as a reaction to this crisis.
The difficulty of SoC communication integration on-chip die is one that the NoC design and field
programmable gate array (FPGA) implementation must overcome. With the continual reduction in chip dies
size, the likelihood of failure in NoC is rising [6]. A fixed NoC can become irregular as a result of arbitrary
placements, which may also impair the uniformity of actual topological design. Since throughput, area,
power, and latency are the four most important factors in chip design [7], the intercommunication between
the many cores and intellectual property (IP) modules on a single chip may have an impact on the device's
communication and system performance [8].
The problem statement of the work is to design the hardware chip for the 2D router for
communication using different ports and analyze the performance on different FPGAs for effective
communication. Most of the work is done to synthesize the chip parameters on the FPGA board. The
research work examines the performance of various FPGAs to assist chip designers in selecting the FPGA
that has the best hardware and timing performance. The organization of the manuscript is as follows:
section 2 details the related work, and section 3 presents the research method. The results and discussions are
given in section 4, followed by the conclusions in section 5.
2. RELATED WORK
The work on the 2D NoC router has been focused on mesh topological NoC (4×4). The NoC nodes
are addressed using the XY routing approach [9]. It is one of the most essential strategies for addressing
nodes and routing data packets between nodes or processing elements inside NoC. The NoC design was
formed with the very high-speed IC hardware description language (VHDL) programming language and
simulated with the Xilinx 14.2 and Modelsim software. The logic routing and synthesis were done on the
Virtex-5 FPGA [10] for 8-bit, 16-bit, 32-bit, 64-bit, and 128-bit data transmission across nodes in the NoC
which was properly configured and implemented. FPGA synthesis settings were assessed by the hardware
parameters and completely reported using the hardware report synthesized for the NoC chip. The 5-port
optical router was detailed [11]. The chip design was focused on mesh and ring topological network
modeling, simulation, and synthesis. The cluster size was regarded as (2×2), (4×4), (8×8), (16×16), (32×32),
(64×64), (128×128), and (256×256) for 2D NoC router design [12]. The projected design decreased the
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quantities of data frames navigated for long-distance communication, according to simulation results. The
performance was gained of 17.2% and 10.3% respectively for standard 2D mesh and level 2 mesh topologies
and provided by (12×12) star type NoC. When the network grows larger, the star-type NoC's performance
improves still more while consuming less space and power. The star-type NoC future work will be included
the development of novel routing algorithms and system designs for adaptive routing in arrange to better
balance traffic loads and get better overall performance.
Different studies have been done related to NoC design for different routing approaches, as well as a
system-based NoC simulator [13]. The core concept of the NoC simulator, design, and settings was detailed
for the test strategy of NoC system planning. The investigation was done for the additional on-chip routing
strategies, such as a novel linear programming (LP) routing strategy. The local traffic showed a significant
improvement in performance for NoC systems, according to the findings. It was identified that LP routing
can handle locality traffic without causing conflict in nearly a third of the cases. If the network system has
excessed resources for sharing, such as connections, and channels, and the immediate rate of flit production
is less than or equal to the volume for accepting flits, LP routing is more successful. The simulations of
application-specific NoC topologies for audio video (AV) benchmark, MPEG-4 decoder, and applications
demonstrated that regular NoC outperforms irregular NoC systems in the terms of performance. The
simulation was following eight digital signal processing (DSP) connectivity architectures in a chip topology.
The fundamental NoC concept and architecture are used to configure the topology structure in which distinct
routing node architecture was followed for arbitration, routing, and data packet format. Moreover, (2×4)
interconnection architecture was designed based on routing node coding, routing algorithm, and node degree
routing direction. The work was carried out using active-HDL software programming and simulation. The
data can continue to function without interruption to increase data transfer efficiency. After synthesis, the
maximum frequency can reach 268 MHz, which can be utilized as a benchmark for the next research.
Kumar et al. [14] focused on the architecture and network interface (NI) design performance examination
and evaluation. This research is based on a 2D 4×4 topology 2D mesh. On the NIRGAM simulation, we
compare the packet latency and throughput of the two algorithms using the XY and odd-even (OE) routing
algorithms, respectively. NIRGAM is a software tool based on system ‘C’ and a cycle-accurate behavior
simulator that provides the platform to realize the routing algorithms and NoC applications for different
topologies. The findings show that for the XY routing algorithm, the packet delay in the X-dimensional
direction is greater than the packet delay in the Y-dimensional direction and the X-dimensional path has
higher average throughput. The packet delay in the X-dimensional direction is lower than in the
Y-dimensional direction and the X-dimensional direction's average throughput is roughly equivalent to the
Y-dimensional direction. To determine if the algorithm is good or terrible, the average throughput to average
packet latency ratio is used. The better the performance, the higher the ratio. The results show that the OE
routing method has a ratio of 2.5358, whereas the XY routing algorithm has a ratio of 2.1126. As a result, the
OE routing method performs better in the 2D mesh topology [15].
Hardware chips are used to implement the 2D, 8×8, and 16×16 mesh topological networks. The
ability to spot faulty nodes and replace them is the programmable structure's main benefit. The X and Y axis
crossbar address generation mechanism can be used to identify problematic nodes. The device utilization
findings indicate a 2% change in the number of slices, a 1% change in the number of slice flip-flops, a 1%
change in the number of 4 input look-up tables (LUTs), and a 1% change in the number of bonded
input/output blocks (IoBs) when the NoC cluster configuration changes from an (8×8) to a (16×16) NoC. For
both networks, the amount of memory used is 58,820 kB and 71,466 kB, respectively. Small-area
communication or LAN networks are found to be suited for 2D-NoC architecture, whereas big-area networks
are not. The higher number of nodes can be considered while conducting a study as part of this ongoing
endeavor. When transferring data across nodes, additional features like data security through encryption and
decryption can be used. If we can combine network security methods with node data transfer, it will be
suitable for wireless data networks and long-distance communications [16]. In response to this dilemma, the
emergent paradigm of NoC is rapidly winning the race to supplant conventional bus designs. To address
varied chip design requirements and routing techniques, numerous NoC topologies have been created.
Regular-size processing devices can be included on a single chip with a mesh topology. Additionally,
compared to other routing protocols, it is much easier to create and implement different routing protocols into
it. Therefore, crossbar architecture has been created in VHDL and simulated in Xilinx ISE 14.1 to use the
Xilinx XC5VLX30-3 FPGA to evaluate the operation of NoC on hardware [17]. Routers are based on the
wormhole switching principle. Round-robin routing is used to create routers on FPGA platforms. The
suggested router confronts the FIFO status of input ports during each clock cycle and the priority of each
input port is constantly adjusted. The architecture described above makes sure that each input port is treated
fairly. Utilizing Xilinx tools, the proposed architecture was created in VHDL. The design's functionality has
been confirmed and its implementation in ISE design suite 14.1 has been completed.
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228
The flat tree NoC architecture, supported by eight nodes at the root, was reported in the study. The
performance of the system was assessed using the Virtex-5 FPGA, xc5vlx20t-2-ff323 device. Several test
cases are used to experience the design. The data flow for the same cluster setup is seen on the Modelsim
waveform. Additionally, the FPGA's timing and hardware support settings are examined. The architecture is
scalable and modular in design. It can be used to create a massive tree in which several nodes can
communicate with each other through their parents and root nodes [18]. The upcoming study may focus on
network security techniques and their integration with NoC configurations for big clusters [19]. When the
rotator on chip (RoC) or ring NoC chip has been created and modeled in Xilinx 14.2 software, Modelsim
10.1 b software is used to functionally simulate it. A data packet's intercommunication is confirmed when it
reaches its destination and the NoC chip can link to up to 6,553 nodes. With FIFO logic integrated, a token
ring concept is used to indicate the priority of communicating nodes at the same instance. Node addresses are
utilized to identify the nodes and Xilinx synthesis results are used to determine hardware attributes such as
the number of logic gates, LUTs, memory use, and the minimum-maximum times required to route packets
[20]. The Virtex-5 FPGA is used to validate the results through data transfer between nodes. The outcomes
show a superior option to currently used ring setup up structures. To create a ring topological network's
programmable and adaptable structure, a large amount of work has been put into NoC design and FPGA
synthesis. Future configurations of the same structure could include more nodes. Additionally, the concept of
cryptographic techniques for encryption and decryption can be used to move data between nodes. Modelsim
10.0 software with 8, 16, 32, 64, and 128-bit data transfer successfully replicates the functionality of the 3D
multilayer mesh NoC design produced in Xilinx 14.2 using VHDL. The performance hardware and time
parameters are also assessed for mesh nodes with cluster sizes of (2×2×2), (3×3×3), and (4×4×4). The
selection of the node effectively utilizes XYZ routing and addressing. The created chip works at a
735.00 MHz frequency. For larger networks like wireless sensor networks, the scalable design establishes
inter-node communication. It is also concentrated on the integration of network security into hierarchical
NoC architectures with multilayer systems environments.
Machine learning models [21] for multiple NoC topologies synthesized on Vitex-5 FPGA for
various cluster configurations are constructed and validated. The described NoC structure may be
advantageous for future MPSoC that seek high performance and fault tolerance from their communication
topology. The programmable structure is a reconfigurable MPSoC solution that permits online configuration
and guarantees that minute faults do not affect system performance. Mesh NoC is scalable and based on XY
routing [22]. When comparing the two, the ring NoC has wider coverage. The parent-child (root) memory
architecture and optimal routing technique form the basis of the tree NoC architecture. The design is more
reliable for NoC and reconfigurable telecommunication networks and more suited for mobile signaling
technologies like SS7. Modelsim 10.1b is used to verify data transfer while the resulting design is tested on
an FPGA for the various test scenarios. Data on hardware usage, such as the number of slices, flip-flops,
input LUTs, bounded IoBs, and gated clocks (GCLKs) used to implement the design, are included in the
synthesis report that is generated. In Xilinx ISE 14.7 and Modelsim 10.0, the study project effectively builds
2D mesh (4×4) and 3D mesh (3×3×3) NoCs. The nodes in the 2D and 3D mesh NoC are addressed using the
XY and XYZ routing. FPGA is a scalable device that offers a synthesis environment with various NoC
cluster sizes. The FPGA is set up with a mesh topology structure that allows 2D mesh (16×16) and
three dimensional (3D) mesh (8×8×8) designs with 256 nodes capable of communication (N=2, 4, 8, 16, 32,
64, and 128, respectively). Timing parameters and hardware resource usage are crucial factors for
semiconductor businesses. The simulation work presented in the manuscript, will help NoC designer to
estimate the resources utilization before developing the actual device by taking into consideration the known
hardware design aspects, memory utilization, and timing factors to produce large-scale NoC.
3. RESEARCH METHOD
The data packets are transferred and communicated by the router. It is happening using the
networking device that performs the traffic direction over the communication network. The data packets are
sent over the networks to get effective communication such as in optical fibers, telecommunication, and
high-speed switching [23]. The design of a 2D network route is shown in Figure 1 in which the 2D router is
configured using the East_data_input, West_data_input, North_data_input, South_data_input, and
Local_data_input. The corresponding outputs are East_data_output, West_data_output, North_data_output,
South_data_output, and Local_data_output respectively for the inputs.
The data flow in packets is shown in Figure 2. This is bidirectional communication and the data
communication mechanism is based on packet switching [24] and the flow control for NoC applications [25].
The data input to the crossbar switch is through all 5 ports defined for east, west, north, south, and local
direction and corresponding outputs using the control module. The objective of the flow control is to use the
5. Int J Inf & Commun Technol ISSN: 2252-8776
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229
effective reasons for the maximum throughput and good performance that depends on the channel bandwidth
and buffering capacity for the allocated network. In switching the flow control is maintained as bufferless
using several ports. The quality of the source is maintained by the throughput of the network. The arbiter is
also used to decide which switch port needs the process in the crossbar switch [26]. The router is used in
different sensor networks [27] and wireless communication technologies such as ZigBee [28] technology.
Figure 1. 2D NoC router [23]
Figure 2. NoC router data packets transmission
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4. RESULTS AND DISCUSSION
The chip design of the 2D-NoC router is done in Xilinx ISE 14.7 and depicted in Figure 3. The
register transfer level (RTL) detail and pins functionality is given in Table 1 which provides the compressive
use and application in the design strategy. The internal schematics of the design are also given in Figure 4.
The Modelsim simulation waveform for the router functionality of 64-bit data communication is verified for
the test inputs given. Figure 5 shows the router's waveform simulation using different binary ports. Figure 6
shows the waveform simulation of the router using different ports in hexadecimal. Figure 7 shows the
waveform simulation of the router using different ports in the American standard code for information
interchange (ASCII).
Figure 3. RTL of the chip design
Table 1. Pin functions of the chip design
Pins Function
East_data_in <63:0> It uses the input port to offer 64-bit data packets input (east direction)
West_data_in <63:0> It uses the input port to offer 64-bit data packets input (west direction)
North_data_in <63:0> It uses the input port to offer 64-bit data packets input (north direction)
South_data_in <63:0> It uses the input port to offer 64-bit data packets input (south direction)
Local_data_in <63:0> It uses the input port to offer 64-bit data packets input (local direction)
Clk (1-bit) It uses the 50% duty cycle clock input signal to provide the rising edge of the
clock
reset (1-bit) It provides the input signal to reset the data input/output port values and
corresponding latches
East_data_out <63:0> It uses the output port to offer 64-bit data packets output (east direction)
West_data_out <63:0> It uses the output port to offer 64-bit data packets output (west direction)
North_data_out <63:0> It uses the output port to offer 64-bit data packets output (north direction)
South_data_out <63:0> It uses the output port to offer 64-bit data packets output (south direction)
Local_data_out <63:0> It uses the output port to offer 64-bit data packets output (local direction)
Read_logic (1-bit) It is the control input used to write the contents from different ports into registers
Write_logic (1-bit) It is the control input used to read the contents of different registers into ports
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Figure 4. The internal schematic in Xilinx of the 2D router design
Figure 5. Waveform simulation of the router using different ports (in binary)
Figure 6. Waveform simulation of the router using different ports (in hexadecimal)
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232
Figure 7. Waveform simulation of the router using different ports (in ASCII)
The simulation input and outputs in the waveforms are East_data_in <63:0>=01010000 01110010
01100001 01110100 01100101 01100101 01101101 (binary)=1’h5072617465656B (hex), West_data_in
<63:0>=01010000 01110010 01100001 01110100 01100101 01100101 01101101
(binary)=1’h5072617465656B (hex), North_data_in <63:0>=01010000 01110010 01100001 01110100
01100101 01100101 01101101 (binary)=1’h5072617465656B (hex), South_data_in <63:0>=01010000
01110010 01100001 01110100 01100101 01100101 01101101(binary)=1’h5072617465656B (hex),
Local_data_in <63:0>=01010000 01110010 01100001 01110100 01100101 01100101
01101101(binary)=1’h5072617465656B (hex), write_logic=‘1’, read_logic=‘0’, the selection_logic changes
from “000”, “001”, “010”, “011”, and “100” for different ports respectively. The output of the ports is
obtained when write_logic=‘0’, and read_logic=‘1’. The data on the ports is verified as East_data_out
<63:0>=01010000 01110010 01100001 01110100 01100101 01100101 01101101
(binary)=1’h5072617465656B (hex), West_data_out <63:0>=01010000 01110010 01100001 01110100
01100101 01100101 01101101 (binary)=1’h5072617465656B (hex), North_data_out <63:0>=01010000
01110010 01100001 01110100 01100101 01100101 01101101 (binary)=1’h5072617465656B (hex),
South_data_out <63:0>=01010000 01110010 01100001 01110100 01100101 01100101
01101101(binary)=1’h5072617465656B (hex), Local_data_out <63:0>=01010000 01110010 01100001
01110100 01100101 01100101 01101101(binary)=1’h5072617465656B (hex).
The hardware parameters summary on different FPGAs is listed in Table 2. The timing values of the
design on different FPGAs are listed in Table 3. Figures 8 and 9 show the variations against the obtained
results of the FPGA resources for hardware and timing utilization.
Table 2. Different FPGA resources as hardware parameters summary
Hardware
parameter
Spartan-3E
(XC3S500E)
Spartan-6
(XC6SLX45)
Virtex-4
(XC4VFX12)
Virtex-5
(XC5VSX50T)
Virtex-7
(XC7VX550T)
Slices 368 184 368 184 184
Slice flip flops 640 320 640 320 320
LUTs 326 10 326 326 10
IOBs 647 647 647 647 647
GCLKs 5 0 5 5 0
Table 3. Different FPGA summary in terms of timing parameters
Timing parameter
Spartan-3E
(XC3S500E)
Spartan-6
(XC6SLX45)
Virtex-4
(XC4VFX12)
Virtex-5
(XC5VSX50T)
Virtex-7
(XC7VX550T)
Minimum period (ns) 1.894 0.951 0.971 1.187 0.170
Minimum input arrival
time before clock (ns)
4.502 1.838 4.471 1.969 0.339
Maximum output required
time after clock (ns)
4.137 3.648 3.892 3.044 0.669
Maximum combinational
path delay (ns)
6.031 4.600 4.863 4.231 1.178
Maximum frequency
(MHz)
50.00 275.00 400.00 290.00 515.00
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Figure 8. FPGA resources utilization summary
Figure 9. FPGA timing parameters utilization summary
5. CONCLUSION
The router transmits the data over the network. Routers use data packets, which can contain a variety
of messages, files, data types, and simple transfers like online engagement, to route and guide network data.
The hardware chip design and simulation of the 2D router are done successfully in Xilinx ISE 14.7 and
Modelsim software. The chip design is verified using the different test inputs in which the 64-bit and
0
100
200
300
400
500
600
700
Slices Slice Flip Flops LUTs IOBs
Hardware
Utilization
Parameters
FPGA Resources Utilization
Spartan-3E
Spartan-6
Virtex-4
Virtex-5
Virtex-7
0
1
2
3
4
5
6
7
Minimum
Period(ns)
Minimum Input
arrival time before
clock(ns)
Maximum output
required time after
clock(ns)
Maximum
combinational path
delay(ns)
Time
(ns)
Parameters
Timing Parameters
Spartan-3E
Spartan-6
Virtex-4
Virtex-5
Virtex-7
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communication are verified using test cases on different input/output ports of the router. The behavior is
verified on the different FPGA hardware such as Spartan-3E (XC3S500E), Spartan-6 (XC6SLX45), Virtex-4
(XC4VFX12), Virtex-5 (XC5VSX50T), and Virtex-7 (XC7VX550T). The comparative study presents that
slices are 368, 184, 368, 184, and 184 respectively for different FPGAs. The slice flip-flops are 640, 320,
640, 320, and 320 respectively for different FPGAs. The number of LUTs is 360, 10, 326, 326, and 10
respectively for different FPGAs. It has been identified that the frequency support for different FPGAs is
Spartan-3E (50.00 MHz), Spartan-6 (275.00 MHz), Virtex-4 (400.00 MHz), Virtex-5 (290.00 MHz), and
Virtex-7 (515.00 MHz). The mining values indicate that the Virtex-7 FPGA has the optimal timing values in
comparison to other FPGAs and Virtex-7 shows maximum frequency support for the router chip design.
ACKNOWLEDGEMENTS
Thankful to the VLSI Design Lab, University of Petroleum and Energy Studies, Dehradun, India for
providing the simulation facility.
REFERENCES
[1] D. Bertozzi and L. Benini, “Xpipes: a network-on-chip architecture for gigascale systems-on-chip,” IEEE Circuits and Systems
Magazine, vol. 4, no. 2, pp. 18–31, 2004, doi: 10.1109/MCAS.2004.1330747.
[2] V. F. Pavlidis and E. G. Friedman, “3-D topologies for networks-on-chip,” IEEE Transactions on Very Large Scale Integration
(VLSI) Systems, vol. 15, no. 10, pp. 1081–1090, 2007, doi: 10.1109/TVLSI.2007.893649.
[3] J. D. Owens, W. J. Dally, R. Ho, D. N. Jayashima, S. W. Keckler, and L. S. Peh, “Research challenges for on-chip interconnection
networks,” IEEE Micro, vol. 27, no. 5, pp. 96–108, 2007, doi: 10.1109/MM.2007.4378787.
[4] G. Ascia, V. Catania, M. Palesi, and D. Patti, “Implementation and analysis of a new selection strategy for adaptive routing in
networks-on-chip,” IEEE Transactions on Computers, vol. 57, no. 6, pp. 809–820, 2008, doi: 10.1109/TC.2008.38.
[5] K. Pang, V. Fresse, S. Yao, and O. A. D. Lima, “Task mapping and mesh topology exploration for an FPGA-based network on
chip,” Microprocessors and Microsystems, vol. 39, no. 3, pp. 189–199, 2015, doi: 10.1016/j.micpro.2015.03.006.
[6] R. Mishra, P. Kuchhal, and A. Kumar, “Effect of height of the substrate and width of the patch on the performance characteristics
of microstrip antenna,” International Journal of Electrical and Computer Engineering, vol. 5, no. 6, pp. 1441–1445, 2015, doi:
10.11591/ijece.v5i6.pp1441-1445.
[7] A. S. Rawat, A. Rana, A. Kumar, and A. Bagwari, “Application of multi layer artificial neural network in the diagnosis system: a
systematic review,” IAES International Journal of Artificial Intelligence, vol. 7, no. 3, pp. 138–142, 2018, doi:
10.11591/ijai.v7.i3.pp138-142.
[8] K. Suriyan, N. Ramaingam, S. Rajagopal, J. Sakkarai, B. Asokan, and M. Alagarsamy, “Performance analysis of peak signal-to-
noise ratio and multipath source routing using different denoising method,” Bulletin of Electrical Engineering and Informatics,
vol. 11, no. 1, pp. 286–292, 2022, doi: 10.11591/eei.v11i1.3332.
[9] N. Agrawal, A. Jain, and A. Agarwal, “Simulation of network on chip for 3D router architecture,” International Journal of Recent
Technology and Engineering, vol. 8, no. 1, pp. 58–62, 2019.
[10] X. Ju and L. Yang, “NoC research and practice: design and implementation of 2×4 2D-torus topology,” International Journal of
Information Technology and Computer Science, vol. 3, no. 4, pp. 50–56, 2011, doi: 10.5815/ijitcs.2011.04.08.
[11] R. Ji, J. Xu, and L. Yang, “Five-port optical router based on microring switches for photonic networks-on-chip,” IEEE Photonics
Technology Letters, vol. 25, no. 5, pp. 492–495, 2013, doi: 10.1109/LPT.2013.2243427.
[12] G. Verma, H. Agarwal, S. Singh, S. N. Khanam, P. K. Gupta, and V. Jain, “Design and implementation of router for NOC on
FPGA,” International Journal of Future Generation Communication and Networking, vol. 9, no. 12, pp. 263–272, 2016, doi:
10.14257/ijfgcn.2016.9.12.24.
[13] J. Y. V. M. Kumar, A. K. Swain, K. Mahapatra, and S. P. M. Verify, “Fortified-NoC: a robust approach for trojan-resilient
network-on-chips to fortify multicore-based consumer electronics,” IEEE Transactions on Consumer Electronics, vol. 68, no. 1,
pp. 57–68, 2022, doi: 10.1109/TCE.2021.3129155.
[14] A. Kumar, L. Baruah, and A. Sabu, “Rotator on chip (RoC) design based on ring topological NoC,” Procedia Computer Science,
vol. 45, pp. 540–548, 2015, doi: 10.1016/j.procs.2015.03.099.
[15] J. Lai, J. Cai, and J. Chu, “A congestion-aware hybrid SRAM and STT-RAM buffer design for network-on-chip router,” IEICE
Electronics Express, vol. 20, no. 2, pp. 20220078–20220078, 2023, doi: 10.1587/elex.19.20220078.
[16] A. Kumar, G. Verma, M. K. Gupta, M. Salauddin, B. K. Rehman, and D. Kumar, “3D multilayer mesh NoC communication and
FPGA synthesis,” Wireless Personal Communications, vol. 106, no. 4, pp. 1855–1873, 2019, doi: 10.1007/s11277-018-5724-3.
[17] T. Patil, A. Sandi, D. M. D. Raj, S. Chandragandhi, and D. M. Teressa, “A minimal buffer router with level encoded dual rail-
based design of network-on-chip architecture,” Wireless Communications and Mobile Computing, vol. 2022, pp. 1–6, 2022, doi:
10.1155/2022/6180153.
[18] D. Jiang, X. Wang, Z. Huang, Y. Yang, and E. Yao, “A network-on-chip-based annealing processing architecture for large-scale
fully connected ising model,” IEEE Transactions on Circuits and Systems I: Regular Papers, pp. 1–13, 2023, doi:
10.1109/TCSI.2023.3263923.
[19] A. Jain et al., “Smart communication using 2D and 3D mesh network-on-chip,” Intelligent Automation and Soft Computing, vol.
34, no. 3, pp. 2007–2021, 2022, doi: 10.32604/iasc.2022.024770.
[20] C. Killian, C. Tanougast, F. Monteiro, and A. Dandache, “Smart reliable network-on-chip,” IEEE Transactions on Very Large
Scale Integration (VLSI) Systems, vol. 22, no. 2, pp. 242–255, 2014, doi: 10.1109/TVLSI.2013.2240324.
[21] N. Gupta, K. S. Vaisla, A. Jain, A. Kumar, and R. Kumar, “Performance analysis of AODV routing for wireless sensor network in
FPGA hardware,” Computer Systems Science and Engineering, vol. 40, no. 3, pp. 1073–1084, 2021, doi:
10.32604/CSSE.2022.019911.
[22] Y. Liu, R. Guo, C. Xu, X. Weng, and Y. Yang, “A Q-learning-based fault-tolerant and congestion-aware adaptive routing
algorithm for networks-on-chip,” IEEE Embedded Systems Letters, vol. 14, no. 4, pp. 203–206, 2022, doi:
11. Int J Inf & Commun Technol ISSN: 2252-8776
2D router chip design, analysis, and simulation for effective communication (Prateek Agarwal)
235
10.1109/LES.2022.3176233.
[23] N. B. Jadhav and B. S. Chaudhari, “Efficient non-blocking optical router for 3D optical network-on-chip,” Optik, vol. 266, 2022,
doi: 10.1016/j.ijleo.2022.169563.
[24] R. Min, R. Ji, Q. Chen, L. Zhang, and L. Yang, “A universal method for constructing N-port nonblocking optical router for
photonic networks-on-chip,” Journal of Lightwave Technology, vol. 30, no. 23, pp. 3736–3741, 2012, doi:
10.1109/JLT.2012.2227945.
[25] F. Mehmood et al., “An efficient and cost effective application mapping for network-on-chip using Andean condor algorithm,”
Journal of Network and Computer Applications, vol. 200, 2022, doi: 10.1016/j.jnca.2021.103319.
[26] S. Sikandar, N. K. Baloch, F. Hussain, W. Amin, Y. B. Zikria, and H. Yu, “An optimized nature-inspired metaheuristic algorithm
for application mapping in 2D-NoC,” Sensors, vol. 21, no. 15, pp. 1–21, 2021, doi: 10.3390/s21155102.
[27] A. N. Rao, B. R. Naik, and L. N. Devi, “An efficient coverage and maximization of network lifetime in wireless sensor networks
through metaheuristics,” International Journal of Informatics and Communication Technology (IJ-ICT), vol. 10, no. 3, pp. 159–
170, 2021, doi: 10.11591/ijict.v10i3.pp159-170.
[28] C. V. Nguyen et al., “ZigBee based data collection in wireless sensor networks,” International Journal of Informatics and
Communication Technology (IJ-ICT), vol. 10, no. 3, pp. 212–224, 2021, doi: 10.11591/ijict.v10i3.pp212-224.
BIOGRAPHIES OF AUTHORS
Mr. Prateek Agarwal is B.Tech. in Electronics and Communication Engineering
from Uttar Pradesh institute of Technology, (UPTU), Lucknow India in 2006. M.E. in
Electronics and Communication, Thapar University (TU), Patiala India in 2008. Pursuing
Ph.D (Electronics and Communication Engineering) in the domain of VLSI design. His areas
of interest are VLSI design and digital communication. He has published 5 research papers in
international and national conferences. He can be contacted at email:
prateek.aggrawal@gkv.ac.in.
Dr. Tanuj Kumar Garg received B.Tech. in Electronics and Communication
Engineering from G.B.P.U.A.T, Pantnagar, Uttarakhand in 2000, M.E from Delhi College of
Engineering, Delhi in 2001 and Ph.D. from Uttarakhand Technical University, Dehradun,
Uttarakhand. He is currently working as Assistant Professor in Department of Electronics and
Communication Engineering, Faculty of Engineering and Technology, Gurukula Kangri
(Deemed to be University). His research interest includes microstrip antennas, reconfigurable
antennas, metamaterials, metamaterial antennas, tunable antennas, leaky wave antennas, and
VLSI design. He can be contacted at email: tanujkgarg@rediffmail.com.
Dr. Adesh Kumar is working as a senior associate professor in the Department
of Electrical and Electronics, Engineering ‘‘University of Petroleum and Energy Studies,
Dehradun, India. He is B.Tech. in Electronics and Communication Engineering from Uttar
Pradesh Technical University Lucknow, India in 2006. M.Tech (Hons) in Embedded Systems
Technology, from SRM University, Chennai in 2008. Ph.D. (Electronics Engineering) form
University of Petroleum and Energy Studies (UPES), Dehradun India in 2014. He has also
worked as senior engineer in TATA ELXSI LIMITED Bangalore and faculty member in
ICFAI University, Dehradun. His areas of interest are VLSI design, embedded systems design,
telecommunications, and signal processing, He has published more than 100+ research papers
in international peer-reviewed journals (SCI/Scopus) and conferences. He is the reviewer of
many SCI/SCIE and Scopus journals such as IEEE Transactions of Industrial Electronics,
Wireless Personal Communications, Microsystem, Technologies, 3D research, Springer,
Journal of Electronic Science and Technology, Journal of Visual Languages and Computing,
Elsevier, World Journal of Engineering, and Emerald are few of them. He has supervised 7
PhD scholars and 5 candidates are doing research under his supervision. He has chaired more
than 10 sessions at international conferences and is involved in the Ph.D. evaluation
committee at UPES, India. Guest Editor: Special Issue-"Intelligent devices and computing
applications" in Computer Systems Science & Engineering, Journal, Tech Science, 2022 (SCI
Indexed). Guest Editor: Special Issue-"Intelligent communication and smart grid automation
applications" in Intelligent Automation & Soft Computing, Journal, Tech Science, 2021 (SCI
Indexed). Editor: Proceedings of intelligent communication, control, and devices in advances
in intelligent system and computing (AISC), book series, Springer, vol. 989, 2020 (Scopus
Indexed). He can be contacted at email: adeshmanav@gmail.com.