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TRI GATE TRANSISTOR
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- 5. Delivered Performance = Frequency* Instructions Per Cycle (IPC) Goal is higher performance and lower power efficiency: the ratio of the output of a machine, engine, device etc., to the energy supplied to it.. Higher IPC usually results in wider data paths and/or more Performance Leakage current and the ability to move charge through the channel have an impact on power
- 6. Silicon Technology Intel Execution On-Time2 Year Cycle 90 nm 2003 180 nm 1999 130 nm 2001 65 nm 2005 45 nm 2007 22 nm 2011 On Track 32 nm 2009
- 8. Microscopic view of32nm transistor
- 10. Reduction in power dissipation Increased pathway for electricalsignals Drives 20% more current than traditional planar transistors High switching speed High performance with reduced size Better control over leakage current due to 3D structure
- 11. Dramatic performance gainat low operating voltage , better than Bulk, PDSOI,FDSOI 37% performance increase at low voltage 50% power reduction at constant performance Improved switching characteristics Higher drive current for a given transistor Only 2 – 3% cost adder
- 12. Will it bethe end of Processor era??? …Surely not!!!!!! Because a new material is all set to replace semiconductors…
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Editor's Notes
- #6 So here it is…. An equation…. In fact two equations. The reason I have taken the risk of committing presentational suicidal by turning everyone who is not a design engineer off, is that these two relationships are the best representation of the issues facing the microprocessor vendor that I can find. The fundamental driving force behind mainstream computing over the last 15 years has been to increase performance. This is represented by the top equation which basically says that the computing performance you get out of a microprocessor is equal to the number of instructions you can crunch per clock cycle, multiplied by the number of clock cycles per second…. or in other words, the frequency you run the thing at. Most of you will recognise this and be familiar with the frequency race of the late 90’s and early 00’s. This issue here, however, is represented by the bottom relationship which states that the power consumed by a microprocessor is proportional to the square of Voltage it operates at, the frequency and this thing called dynamic capacitance. It’s actually a little worse that this since there is also a relationship between Voltage and Frequency which means that by increasing frequency you actually increase power at a faster rate than you increase performance. The other element here is Dynamic capacitance….. Which sounds very complicated but is fairly simple in that it is directly related to the number of bits you toggle inside the device…….. The problem is that in order to crunch more instructions in any particular clock cycle and increase performance through the IPC route, we tend to do things like increase the width of buses inside the chip, and to increase the length of pipelines where we process the instructions ahead of time…. Just in case…. This effectively means that for any clock cycle, more is happening inside the chip, which in turn leads to an increase in power. So this is a bit of a double whammy…. as they say…. And the basic fact is that unless you start to get pretty smart then you have this mutually exclusive relationship between power consumption and processing effort. For a long time in mainstream computing this didn’t matter, we had enough headroom in terms of cooling solutions and market acceptance to pursue processing power while not worrying too much about the wall socket power. So we now get to the point I’m trying to make….. Which is that this is no longer acceptable, and actually no longer viable to continue on the old vector of increasing performance without paying an equal level of attention to the power consumed. Leaving aside the environmental aspects which are compelling in themselves….. From a purely technical and business perspective, a change in direction became inevitable and necessary. Firstly from the technical perspective, you may have noticed that the frequency race stopped……. This is not because it couldn’t be done,….. in fact the over-clocking community shows us continually that it is possible to get fantastic speeds out of these chips….. The fact is that the cooling solutions needed are so complex that it becomes unviable to do this as a mainstream high volume product. Our CTO memorably said several years ago now that if we continue on our frequency vector, the thermal density at the silicon would be equivalent to that of a rocket nozzle….. So there are technical issues……. We needed, and still need, to find ways of increasing performance, while reducing costs and maintaining or decreasing the power consumption. The rest of this talk outlines at a high level some of the things being done to pursue these competing objectives.
- #9 Intel's tri-gate transistor employs a novel 3-D structure, like a raised, flat plateau with vertical sides, which allows electronic signals to be sent along the top of the transistor and along both vertical sidewalls as well. This effectively triples the area available for electrical signals to travel,