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Nanoscale Power Delivery & PI 
Overview 
Raj Nair, Anasim Corp. 
Aug. 21, 2013 (Updated) 
The Power Integrity (PI) Wall 
PI Analysis 
Management & Innovation Potential 
Publications & Discussion
Power Integrity & the PI Wall 
PI degradation with scaling* ~= 1 
For constant power density (CPD) or constant power (CP) scaling, 
where k is the process scaling factor, typically 0.7 
Classical CPD/CP scaling → ~70% degradation in PI 
· 20nm SoC to 16nm FinFET transition 
k √ k 
· Appears Constant Power and Constant Power Density, higher cost 
· ~40% PI degradation; with k = 0.8 and the inverse k-root-k metric 
· 16nm to 10nm 
· Scale factor 0.625, leads to > 2X (> 100%) degradation in PI!! 
· We have seen PI-related product failures (FMAX, INRUSH I) in the 
past and the present. Business as usual NOT an option. 
08/21/13 Anasim Confidential 2 
* “Power Integrity Analysis and Management for ICs”, Prentice-Hall, May 2010
PI analysis prior art (Droop, IR Drop) 
W i t h D i e C a p s 
W i t h o u t D i e C a p s 
· Lumped and Polygonal Þ Not True-Physical and Spatio-Temporal, eliminates 
spatial variance and temporal coincidence 
· Not wideband, and leads to pessimistic, non-optimal chip/pkg/board 
design. Loses local resonances, constructive/destructive noise interference 
08/21/13 Anasim Confidential 3
Differential¹ modeling & design 
Grids, transmission lines/planes 
Abstract, system level, continuous² 
No freq/time domain discontinuities 
08/21/13 Anasim Confidential 4 
² “Power Integrity Analysis and Management for ICs”, Prentice-¹ Integrity learning from the SI world and from fundamentals Hall, May 2010
PI: How do droops REALLY look? 
Supply differential 
True-physical power grid noise (π-fp); droops and propagation 
08/21/13 Anasim Confidential 5
Continuum³ analysis insight 
True-physical noise wave propagation (rlcsim) 
08/21/13 Anasim Confidential 6 
³ “Power Delivery, Integrity Analysis and Management for SoC's”, SoC 2007, FI
PI mngmnt: Fundamental methods 
1.6E-06 
1.4E-06 
1.2E-06 
1.0E-06 
8.0E-07 
6.0E-07 
4.0E-07 
2.0E-07 
0.0E+00 
 
 
 
1.5 
~130nm process 
-2 -1 0 1 2 
Vg [V] 
C [f/cm^2) 
 On-die capacitance 
- Quantity 
- Type (fixed/variable) 
- Degradation in deep 
nanoscale (Q, leak) 
- Placement and 
distribution 
VCC 
1 nS 
A 
100 
DV= 50mV 
1 nS 
V 
1 
Can a fine-grain distribution of de-coupling capacitors minimize the di/dt problem? 
08/21/13 Anasim Confidential 7
PI management: Power Grid Design 
Differential grid architecture 
Novel simulation algo.  IP* 
What-if analysis in minutes... 
08/21/13 Anasim Confidential 8 
* “Power Integrity Analysis and Management for ICs”, Prentice-Hall, May 2010
PI management: Power Grid Sims 
08/21/13 Anasim Confidential 9 
Anasim Corp., Power Integrity Aware Methodology
PI Management: Package Cap Loop-L4 
ö 
æ 
÷ L 
V ÷ 
= V - D I p 
s i n (w ) -a - 1 
f i t e I r 
p 
C 
1 
L D V = k V = D I 1 
= 
v i k C V f 
1 1 1 C 
Load-shift induced noise 
- Transient  DC 
- Package dependency 
2 
L D V = k V = D I 2 
= 
v i k C V f 
2 2 2 C 
1 
c f 
S = 
1 0 
1 
0 . 1 
08/21/13 Anasim Confidential 10 
4 “Power Delivery, Integrity Analysis and Management for SoC's”, SoC 2007, FI 
s 
t 
d 
C 
ø 
ç ç 
è 
d 
L 
D V = D I 
1 
1 
1 
2 
1 1 
1 
L 
V 
C 
2 
2 
1 
2 
2 2 
2 
L 
V 
C 
2 
l S S 
Q u in t u p le t a n d T r ip le t lo o p - L s c a lin g 
0 . 0 1 
P 8 5 8 P 8 6 0 P 1 2 6 2 P 1 2 6 4 
P r o c e s s 
l o o p - L , p H 
Q - s c a l in g T - s c a l i n g 
Scaling challenge 
- Exponent of scale 
factor 
- Pkg. caps help, but...
PI management: Fast Regulation 
· Simulation (0.18μm) 
· Idealized parasitics 
· 4:1 ESL ratio between 
grids 
· Capacitance evenly 
distributed 
· N-Series-Pass 
· Inherently stable 
· Fast response 
· Charge Valve benefits 
· ~25% VCC droop 
reduction in sim 
· Apparently kicks in 
within 50pS 
LVDCAP and HVDCAP were 5pF 
each in the active configuration and 
10pF, 0pF in the inactive mode. 
65mV droop 
Sub-50pS response 
88mV droop 
08/21/13 Anasim Confidential 11 
Raj Nair, “Distributed charge Valves”, research conducted in late 1999 at Intel Labs, Oregon
PI mngmnt: Active Noise Regulation* 
Tested in lumped (b/w) and continuum (π-fp) model simulations 
08/21/13 Anasim Confidential 12 
*Raj Nair, “Active Noise Regulators”, US Patent 7291896,http://www.anasim.com/active-noise-regulation/
Distributed Local Voltage Regulation5 
 Split, distribute lumped 
regulator components 
- Switches 
- Inductors, CAPs 
- Reducing IL per 
branch 
 Increases Bandwidth 
- LC α (1/f2) 
- Reducing CAP need 
 And Efficiency 
- I2R losses reduced 
significantly (ind.) 
Modular design 
- Flexible form factor 
- Distributes power and 
heat dissipation 
Transient-suppressing high-BW regulation6 
08/21/13 Anasim Confidential 13 
5 “Power Delivery, Integrity Analysis and Management for 6 Nair, US patent appl. pub. US 2005/0168890 A1, filed Jan. 24, 2004 SoC's”, SoC 2007, FI
PI mngmnt. innovation opportunities 
· Board, package, and chip-level 
· Regulation, form-factor dependent 
· Hybrid regulation 
· Active noise regulation 
· Distributed voltage regulation 
· Integration (on-die, on-pkg...) 
· Tools  Methodology (Architecture, Design, Verification...) 
References 
Power Integrity Analysis and Management for Integrated Circuits 
Raj Nair  Donald Bennett 
Prentice-Hall, Publication Date: May 17, 2010 | ISBN-10: 0137011229 | ISBN-13: 978-0137011223 | Edition: 1 
http://www.amazon.com/Integrity-Analysis-Management-Integrated-Circuits/dp/0137011229/ 
Power Integrity for Nanoscale Integrated Systems 
Masanori Hashimoto  Raj Nair 
McGraw-Hill, Publication Date: December 22, 2013 | ISBN-10: 0071787763 | ISBN-13: 978-0071787765 | Edition: 1 
http://www.amazon.com/Power-Integrity-Nanoscale-Integrated-Systems/dp/0071787763/ 
08/21/13 Anasim Confidential 14
Backup slides 
C P U 
A c t i v e d e v i c e C a p s A c t i v e d e v i c e 
08/21/13 Anasim Confidential 15
Lumped simulation model with ANR 
A N R S c h e m a t ic  t h e P S C P O R M o d e l: I llu s t r a t io n s 
1 8 n 
L 1 
3 0 m 
R 1 6 m 
B o a r d 
5 4 p 
L m b 
0 . 4 2 m 
R m b 
5 
V 1 
6 m / n _ o s c 
R o s c 
v i d R m l c c 
V v r 
3 . 3 n / n _ o s c 
L o s c 
5 0 4 u * n _ o s c 
C o s c 
3 8 5 p 
L 4 
R e s e r v o ir C A P 
3 . 5 p 
L p k g 
4 m 
R 4 
A N R C o m p o n e n t 
P a c k a g e c o n n . 
2 2 u 
C 2 
0 . 2 6 m 
R p k g 4 0 p s / 1 8 8 n 
6 . 5 m / n _ 2 t 
R 2 t 
3 8 5 p / n _ 2 t 
L 2 t 
1 0 u * n _ 2 t 
C 2 t 
R d i e 
V 2 
T r a c e 
2 0 m 
R 3 
6 n 
L 3 
R 2 
3 . 3 n 
L 2 
5 0 4 u 
C 1 
Q 1 
1 
G 1 
1 8 8 n 
C d i e 
6 . 5 m / n _ i d c 
R i d c 
6 0 p / n _ i d c 
L i d c 
2 . 2 u * n _ i d c 
C i d c 
0 . 2 2 m 
R s o c k 
1 8 p 
L s o c k 
3 . 5 m / n _ m l c c 
1 . 2 n / n _ m l c c 
L m l c c 
2 0 u * n _ m l c c 
C m l c c 
08/21/13 Anasim Confidential 16
PRESCOTT Pre-ANR 
08/21/13 Anasim Confidential 17
PRESCOTT Post-ANR 
08/21/13 Anasim Confidential 18

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Nano_PI_rvw

  • 1. Nanoscale Power Delivery & PI Overview Raj Nair, Anasim Corp. Aug. 21, 2013 (Updated) The Power Integrity (PI) Wall PI Analysis Management & Innovation Potential Publications & Discussion
  • 2. Power Integrity & the PI Wall PI degradation with scaling* ~= 1 For constant power density (CPD) or constant power (CP) scaling, where k is the process scaling factor, typically 0.7 Classical CPD/CP scaling → ~70% degradation in PI · 20nm SoC to 16nm FinFET transition k √ k · Appears Constant Power and Constant Power Density, higher cost · ~40% PI degradation; with k = 0.8 and the inverse k-root-k metric · 16nm to 10nm · Scale factor 0.625, leads to > 2X (> 100%) degradation in PI!! · We have seen PI-related product failures (FMAX, INRUSH I) in the past and the present. Business as usual NOT an option. 08/21/13 Anasim Confidential 2 * “Power Integrity Analysis and Management for ICs”, Prentice-Hall, May 2010
  • 3. PI analysis prior art (Droop, IR Drop) W i t h D i e C a p s W i t h o u t D i e C a p s · Lumped and Polygonal Þ Not True-Physical and Spatio-Temporal, eliminates spatial variance and temporal coincidence · Not wideband, and leads to pessimistic, non-optimal chip/pkg/board design. Loses local resonances, constructive/destructive noise interference 08/21/13 Anasim Confidential 3
  • 4. Differential¹ modeling & design Grids, transmission lines/planes Abstract, system level, continuous² No freq/time domain discontinuities 08/21/13 Anasim Confidential 4 ² “Power Integrity Analysis and Management for ICs”, Prentice-¹ Integrity learning from the SI world and from fundamentals Hall, May 2010
  • 5. PI: How do droops REALLY look? Supply differential True-physical power grid noise (π-fp); droops and propagation 08/21/13 Anasim Confidential 5
  • 6. Continuum³ analysis insight True-physical noise wave propagation (rlcsim) 08/21/13 Anasim Confidential 6 ³ “Power Delivery, Integrity Analysis and Management for SoC's”, SoC 2007, FI
  • 7. PI mngmnt: Fundamental methods 1.6E-06 1.4E-06 1.2E-06 1.0E-06 8.0E-07 6.0E-07 4.0E-07 2.0E-07 0.0E+00 1.5 ~130nm process -2 -1 0 1 2 Vg [V] C [f/cm^2)  On-die capacitance - Quantity - Type (fixed/variable) - Degradation in deep nanoscale (Q, leak) - Placement and distribution VCC 1 nS A 100 DV= 50mV 1 nS V 1 Can a fine-grain distribution of de-coupling capacitors minimize the di/dt problem? 08/21/13 Anasim Confidential 7
  • 8. PI management: Power Grid Design Differential grid architecture Novel simulation algo. IP* What-if analysis in minutes... 08/21/13 Anasim Confidential 8 * “Power Integrity Analysis and Management for ICs”, Prentice-Hall, May 2010
  • 9. PI management: Power Grid Sims 08/21/13 Anasim Confidential 9 Anasim Corp., Power Integrity Aware Methodology
  • 10. PI Management: Package Cap Loop-L4 ö æ ÷ L V ÷ = V - D I p s i n (w ) -a - 1 f i t e I r p C 1 L D V = k V = D I 1 = v i k C V f 1 1 1 C Load-shift induced noise - Transient DC - Package dependency 2 L D V = k V = D I 2 = v i k C V f 2 2 2 C 1 c f S = 1 0 1 0 . 1 08/21/13 Anasim Confidential 10 4 “Power Delivery, Integrity Analysis and Management for SoC's”, SoC 2007, FI s t d C ø ç ç è d L D V = D I 1 1 1 2 1 1 1 L V C 2 2 1 2 2 2 2 L V C 2 l S S Q u in t u p le t a n d T r ip le t lo o p - L s c a lin g 0 . 0 1 P 8 5 8 P 8 6 0 P 1 2 6 2 P 1 2 6 4 P r o c e s s l o o p - L , p H Q - s c a l in g T - s c a l i n g Scaling challenge - Exponent of scale factor - Pkg. caps help, but...
  • 11. PI management: Fast Regulation · Simulation (0.18μm) · Idealized parasitics · 4:1 ESL ratio between grids · Capacitance evenly distributed · N-Series-Pass · Inherently stable · Fast response · Charge Valve benefits · ~25% VCC droop reduction in sim · Apparently kicks in within 50pS LVDCAP and HVDCAP were 5pF each in the active configuration and 10pF, 0pF in the inactive mode. 65mV droop Sub-50pS response 88mV droop 08/21/13 Anasim Confidential 11 Raj Nair, “Distributed charge Valves”, research conducted in late 1999 at Intel Labs, Oregon
  • 12. PI mngmnt: Active Noise Regulation* Tested in lumped (b/w) and continuum (π-fp) model simulations 08/21/13 Anasim Confidential 12 *Raj Nair, “Active Noise Regulators”, US Patent 7291896,http://www.anasim.com/active-noise-regulation/
  • 13. Distributed Local Voltage Regulation5  Split, distribute lumped regulator components - Switches - Inductors, CAPs - Reducing IL per branch  Increases Bandwidth - LC α (1/f2) - Reducing CAP need  And Efficiency - I2R losses reduced significantly (ind.) Modular design - Flexible form factor - Distributes power and heat dissipation Transient-suppressing high-BW regulation6 08/21/13 Anasim Confidential 13 5 “Power Delivery, Integrity Analysis and Management for 6 Nair, US patent appl. pub. US 2005/0168890 A1, filed Jan. 24, 2004 SoC's”, SoC 2007, FI
  • 14. PI mngmnt. innovation opportunities · Board, package, and chip-level · Regulation, form-factor dependent · Hybrid regulation · Active noise regulation · Distributed voltage regulation · Integration (on-die, on-pkg...) · Tools Methodology (Architecture, Design, Verification...) References Power Integrity Analysis and Management for Integrated Circuits Raj Nair Donald Bennett Prentice-Hall, Publication Date: May 17, 2010 | ISBN-10: 0137011229 | ISBN-13: 978-0137011223 | Edition: 1 http://www.amazon.com/Integrity-Analysis-Management-Integrated-Circuits/dp/0137011229/ Power Integrity for Nanoscale Integrated Systems Masanori Hashimoto Raj Nair McGraw-Hill, Publication Date: December 22, 2013 | ISBN-10: 0071787763 | ISBN-13: 978-0071787765 | Edition: 1 http://www.amazon.com/Power-Integrity-Nanoscale-Integrated-Systems/dp/0071787763/ 08/21/13 Anasim Confidential 14
  • 15. Backup slides C P U A c t i v e d e v i c e C a p s A c t i v e d e v i c e 08/21/13 Anasim Confidential 15
  • 16. Lumped simulation model with ANR A N R S c h e m a t ic t h e P S C P O R M o d e l: I llu s t r a t io n s 1 8 n L 1 3 0 m R 1 6 m B o a r d 5 4 p L m b 0 . 4 2 m R m b 5 V 1 6 m / n _ o s c R o s c v i d R m l c c V v r 3 . 3 n / n _ o s c L o s c 5 0 4 u * n _ o s c C o s c 3 8 5 p L 4 R e s e r v o ir C A P 3 . 5 p L p k g 4 m R 4 A N R C o m p o n e n t P a c k a g e c o n n . 2 2 u C 2 0 . 2 6 m R p k g 4 0 p s / 1 8 8 n 6 . 5 m / n _ 2 t R 2 t 3 8 5 p / n _ 2 t L 2 t 1 0 u * n _ 2 t C 2 t R d i e V 2 T r a c e 2 0 m R 3 6 n L 3 R 2 3 . 3 n L 2 5 0 4 u C 1 Q 1 1 G 1 1 8 8 n C d i e 6 . 5 m / n _ i d c R i d c 6 0 p / n _ i d c L i d c 2 . 2 u * n _ i d c C i d c 0 . 2 2 m R s o c k 1 8 p L s o c k 3 . 5 m / n _ m l c c 1 . 2 n / n _ m l c c L m l c c 2 0 u * n _ m l c c C m l c c 08/21/13 Anasim Confidential 16
  • 17. PRESCOTT Pre-ANR 08/21/13 Anasim Confidential 17
  • 18. PRESCOTT Post-ANR 08/21/13 Anasim Confidential 18