International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Sub-Threshold Leakage Current Reduction Techniques In VLSI Circuits -A SurveyIJERA Editor
There is an increasing demand for portable devices powered up by battery, this led the manufacturers of
semiconductor technology to scale down the feature size which results in reduction in threshold voltage and
enables the complex functionality on a single chip. By scaling down the feature size the dynamic power
dissipation has no effect but the static power dissipation has become equal or more than that of Dynamic power
dissipation. So in recent CMOS technologies static power dissipation i.e. power dissipation due to leakage
current has become a challenging area for VLSI chip designers. In order to prolong the battery life and maintain
reliability of circuit, leakage current reduction is the primary goal. A basic overview of techniques used for
reduction of sub-threshold leakages is discussed in this paper. Based on the surveyed techniques, one would be
able to choose required and apt leakage reduction technique.
Design of complex arithmetic logic circuits considering ground noise, leakage current, active power and area is a challenging task in VLSI circuits. In this paper, a comparative analysis of high performance power gating schemes is done which minimizes the leakage power and provides a way to control the ground noise. The innovative power gating schemes such as stacking power gating , diode based stacking power gating are analyzed which minimizes the peak of ground noise in transition mode for deep submicron circuits. Further to evaluate the efficiency, the simulation has been done using such high performance power gating schemes. Leakage current comparison of NAND gate without power gating and with power gating scheme is done. Finally it is observed that the leakage current in standby mode is reduced by 80% over the conventional power gating. It is also found that in stacking power gating, the ground noise has been reduced by a small extent over the conventional power gating scheme. We have performed simulations using Tanner in a 180nm standard CMOS technology at room temperature with supply voltage of 2.5 V. Finally, a detailed comparative analysis has been carried out to measure the design efficiency of high performance power gating schemes. This analysis provides an effective road map for high performance digital circuit designers who are interested to work with low power application in deep submicron circuits.
High performance novel dual stack gating technique for reduction of ground bo...eSAT Journals
Abstract The development of digital integrated circuits is challenged by higher power consumption. The combination of higher clock speeds, greater functional integration, and smaller process geometries has contributed to significant growth in power density. Today leakage power has become an increasingly important issue in processor hardware and software design. So to reduce the leakages in the circuit many low power strategies are identified and experiments are carried out. But the leakage due to ground connection to the active part of the circuit is very higher than all other leakages. As it is mainly due to the back EMF of the ground connection we are calling it as ground bounce noise. To reduce this noise, different methodologies are designed. In this paper, a number of critical considerations in the sleep transistor design and implementation includes header or footer switch selection, sleep transistor distribution choices and sleep transistor gate length, width and body bias optimization for area, leakage and efficiency. Novel dual stack technique is proposed that reduces not only the leakage power but also dynamic power. The previous techniques are summarized and compared with this new approach and comparison of both the techniques is done with the help of Digital Schematic( DSCH ) and Microwind low power tools. Stacking power gating technique has been analyzed and the conditions for the important design parameters (Minimum ground bounce noise) have been derived. The Monte-Carlo simulation is performed in Microwind to calculate the values of all the needed parameters for comparison. Index Terms: Ground Bounce Noise ,Power gating schemes ,Static power dissipation, Dynamic power dissipation, Power gating parameters, Sleep transistors, Novel dual stack approach, Transistor leakage power
Low power is one of the key research area in today’s electronic industry. Need of low power has created a major pattern shift in the field of electronics where power dissipation is equally important as area, performance etc. Several low power portable electronic equipments, low voltage design techniques have been developed and have driven analog designers to create techniques eg. Self cascode mosfet and stacking technique. For this aim in mind we designed a Folded Cascode using low power techniques and analyzed its various properties through the Spice simulations for 0.13 micron CMOS technology from TSMC and the supply voltage 1.8V.
The low power has been the main concern for the VLSI industry with the technology scaling in CMOS process from 130 nm to 22nm. The presentation here gives a brief idea about the several low power VLSI techniques being used in VLSI circuits to reduce the power and delay. for any query feel free to visit us at: http://www.siliconmentor.com/
Sub-Threshold Leakage Current Reduction Techniques In VLSI Circuits -A SurveyIJERA Editor
There is an increasing demand for portable devices powered up by battery, this led the manufacturers of
semiconductor technology to scale down the feature size which results in reduction in threshold voltage and
enables the complex functionality on a single chip. By scaling down the feature size the dynamic power
dissipation has no effect but the static power dissipation has become equal or more than that of Dynamic power
dissipation. So in recent CMOS technologies static power dissipation i.e. power dissipation due to leakage
current has become a challenging area for VLSI chip designers. In order to prolong the battery life and maintain
reliability of circuit, leakage current reduction is the primary goal. A basic overview of techniques used for
reduction of sub-threshold leakages is discussed in this paper. Based on the surveyed techniques, one would be
able to choose required and apt leakage reduction technique.
Design of complex arithmetic logic circuits considering ground noise, leakage current, active power and area is a challenging task in VLSI circuits. In this paper, a comparative analysis of high performance power gating schemes is done which minimizes the leakage power and provides a way to control the ground noise. The innovative power gating schemes such as stacking power gating , diode based stacking power gating are analyzed which minimizes the peak of ground noise in transition mode for deep submicron circuits. Further to evaluate the efficiency, the simulation has been done using such high performance power gating schemes. Leakage current comparison of NAND gate without power gating and with power gating scheme is done. Finally it is observed that the leakage current in standby mode is reduced by 80% over the conventional power gating. It is also found that in stacking power gating, the ground noise has been reduced by a small extent over the conventional power gating scheme. We have performed simulations using Tanner in a 180nm standard CMOS technology at room temperature with supply voltage of 2.5 V. Finally, a detailed comparative analysis has been carried out to measure the design efficiency of high performance power gating schemes. This analysis provides an effective road map for high performance digital circuit designers who are interested to work with low power application in deep submicron circuits.
High performance novel dual stack gating technique for reduction of ground bo...eSAT Journals
Abstract The development of digital integrated circuits is challenged by higher power consumption. The combination of higher clock speeds, greater functional integration, and smaller process geometries has contributed to significant growth in power density. Today leakage power has become an increasingly important issue in processor hardware and software design. So to reduce the leakages in the circuit many low power strategies are identified and experiments are carried out. But the leakage due to ground connection to the active part of the circuit is very higher than all other leakages. As it is mainly due to the back EMF of the ground connection we are calling it as ground bounce noise. To reduce this noise, different methodologies are designed. In this paper, a number of critical considerations in the sleep transistor design and implementation includes header or footer switch selection, sleep transistor distribution choices and sleep transistor gate length, width and body bias optimization for area, leakage and efficiency. Novel dual stack technique is proposed that reduces not only the leakage power but also dynamic power. The previous techniques are summarized and compared with this new approach and comparison of both the techniques is done with the help of Digital Schematic( DSCH ) and Microwind low power tools. Stacking power gating technique has been analyzed and the conditions for the important design parameters (Minimum ground bounce noise) have been derived. The Monte-Carlo simulation is performed in Microwind to calculate the values of all the needed parameters for comparison. Index Terms: Ground Bounce Noise ,Power gating schemes ,Static power dissipation, Dynamic power dissipation, Power gating parameters, Sleep transistors, Novel dual stack approach, Transistor leakage power
Low power is one of the key research area in today’s electronic industry. Need of low power has created a major pattern shift in the field of electronics where power dissipation is equally important as area, performance etc. Several low power portable electronic equipments, low voltage design techniques have been developed and have driven analog designers to create techniques eg. Self cascode mosfet and stacking technique. For this aim in mind we designed a Folded Cascode using low power techniques and analyzed its various properties through the Spice simulations for 0.13 micron CMOS technology from TSMC and the supply voltage 1.8V.
The low power has been the main concern for the VLSI industry with the technology scaling in CMOS process from 130 nm to 22nm. The presentation here gives a brief idea about the several low power VLSI techniques being used in VLSI circuits to reduce the power and delay. for any query feel free to visit us at: http://www.siliconmentor.com/
Leakage Power Reduction Techniques Revisited in a CMOS Inverter Circuit at De...idescitation
As CMOS Technology is aiming at miniaturization
of MOS devices, a trend of increase in the static power
consumption is being observed. The main sources of static
power consumption are sub-threshold current and gate oxide
leakage current. In this work, we discuss the major sources of
power consumption, various techniques to reduce leakage
power and their trade-offs in a CMOS inverter logic circuit at
90nm. Three most popular leakage current reduction
techniques are studied with respect to a conventional inverter
circuit. It is seen that the main trade-off is between the area
and the static leakage current. This paper aims to reduce the
static power dissipation with a small compromise in area.
A Study on Protection of Cables by Solkor Differential Protection Relay with ...IJERA Editor
This paper intends to briefly compare the protection of buried three phase high voltage cable with Solkordifferential protection relay using metallic pilot wires orfibre optic pilot wires. Dielectric property of the fiber optic provides complete electrical isolation as well as interference free signaling. This provides total immunity from GPR (ground potential rise), longitudinal induction, and differential mode noise coupling andhigh-voltage hazards to personnel safety. So Fibre optic provides great advantage for Solkor differential protection relaying.
LOW POWER SI CLASS E POWER AMPLIFIER AND RF SWITCH FOR HEALTH CAREieijjournal
This research was to design a 2.4 GHz class E Power Amplifier (PA) for health care, with 0.18um
Semiconductor Manufacturing International Corporation CMOS technology by using Cadence software.
And also RF switch was designed at cadence software with power Jazz 180nm SOI process. The ultimate
goal for such application is to reach high performance and low cost, and between high performance and
low power consumption design. This paper introduces the design of a 2.4GHz class E power amplifier and RF switch design. PA consists of cascade stage with negative capacitance. This power amplifier can transmit 16dBm output power to a 50Ω load. The performance of the power amplifier and switch meet the specification requirements of the desired.
Combined Defence Services Examination (II) - 2014Performance analysis of swcn...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
NOVEL SLEEP TRANSISTOR TECHNIQUES FOR LOW LEAKAGE POWER PERIPHERAL CIRCUITSVLSICS Design
Static power consumption is a major concern in nanometre technologies. Along with technology scaling down and higher operating speeds of CMOS VLSI circuits, the leakage power is getting enhanced. As process geometries are becoming smaller, device density increases and threshold voltage as well as oxide thickness decrease to keep pace with performance. Two novel circuit techniques for leakage current reduction in inverters with and without state retention property are presented in this work. The power dissipation during inactive (standby) mode of operation can be significantly reduced compared to traditional power gating methods by these circuit techniques. The proposed circuit techniques are applied to inverters and the results are compared with earlier inverter leakage minimization techniques. Inverter
buffer chains are designed using new state retention low leakage technique and found to be dissipating lower power with state retention. All low leakage inverters are designed and simulated in cadence design environment using 90 nm technology files. The leakage power during sleep mode is found to be better by X 63 times for novel method. The total power dissipation has also reduced by a factor of X 3.5, compared to earlier sleepy keeper technique. The state retention feature is also good compared to earlier leakage power reduction methodologies.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Analysis of CMOS and MTCMOS Circuits Using 250 Nano Meter Technology csandit
The low-power consumption with less delay time has become an important issue in the recent
trends of VLSI. In these days, the low power systems with high speed are highly preferable
everywhere. Designers need to understand how low-power techniques affect performance
attributes, and have to choose a set of techniques that are consistent with these attributes .The
main objective of this paper is to describe, how to achieve low power consumption with
approximately same delay time in a single circuit. In this paper, we make circuits with CMOS
and MTCMOS techniques and check out its power and delay characteristics. The circuits
designed using MTCMOS technique gives least power consumption.
All the pre-layout simulations have been performed at 250nm technology on tanner EDA tool.
A 3-6 GHZ CURRENT REUSE NOISE CANCELLING LOW NOISE AMPLIFIER FOR WLAN AND WPA...IAEME Publication
In these paper CMOS LNA is designed for 3-6 GHz frequency range. These proposed LNA has the maximum flat gain to over all frequency range. These LNA has three stage at first stage to reduce noise with current reuse technique is used to increase the linearity at the first stage. At second stage cascaded common source is used to increase the gain with minimum noise figure. At third stage buffer is used because of its low noise figure. All these circuit can be analysed in ADS tool with 130 nm process with a 1.8V supply voltage.
It contains POWER MOSFET INTRODUCTION, POWER MOSFET STRUCTURE, types of power MOSFET, symbols, output characteristics , applications etc. https://amzn.to/3x56Qro click here to buy GATE 2022 Electronics & Communication Engineering - 35 Years Topic-wise Previous Solved Papers
A LOW POWER, LOW PHASE NOISE CMOS LC OSCILLATORIJEEE
In this paper a Double Cross Coupled Inductor capacitor based Voltage Control Oscillator (LC-VCO) is designed. In the proposed circuit the phase noise, tuning range with respect to control voltage, output power and the power dissipation of the circuit is analysed. Phase noise of approximate -96 dBc/Hz at frequency of 1MHz, frequency tuning range of 4.8 to 8.3 GHz (corresponding to 53.0% tuning range) obtained by varying the control voltage from 0 to 2.0 V, Output power of circuit -8.92 dBm at 50 Ohm resistance terminal and the power consumption of Circuit is 3.8 mW. This VCO are designed for 5.5 GHz. The circuit is designed on the UMC 180nm CMOS technology and all the simulation results are obtained using cadence SPECTRE Simulator.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Leakage Power Reduction Techniques Revisited in a CMOS Inverter Circuit at De...idescitation
As CMOS Technology is aiming at miniaturization
of MOS devices, a trend of increase in the static power
consumption is being observed. The main sources of static
power consumption are sub-threshold current and gate oxide
leakage current. In this work, we discuss the major sources of
power consumption, various techniques to reduce leakage
power and their trade-offs in a CMOS inverter logic circuit at
90nm. Three most popular leakage current reduction
techniques are studied with respect to a conventional inverter
circuit. It is seen that the main trade-off is between the area
and the static leakage current. This paper aims to reduce the
static power dissipation with a small compromise in area.
A Study on Protection of Cables by Solkor Differential Protection Relay with ...IJERA Editor
This paper intends to briefly compare the protection of buried three phase high voltage cable with Solkordifferential protection relay using metallic pilot wires orfibre optic pilot wires. Dielectric property of the fiber optic provides complete electrical isolation as well as interference free signaling. This provides total immunity from GPR (ground potential rise), longitudinal induction, and differential mode noise coupling andhigh-voltage hazards to personnel safety. So Fibre optic provides great advantage for Solkor differential protection relaying.
LOW POWER SI CLASS E POWER AMPLIFIER AND RF SWITCH FOR HEALTH CAREieijjournal
This research was to design a 2.4 GHz class E Power Amplifier (PA) for health care, with 0.18um
Semiconductor Manufacturing International Corporation CMOS technology by using Cadence software.
And also RF switch was designed at cadence software with power Jazz 180nm SOI process. The ultimate
goal for such application is to reach high performance and low cost, and between high performance and
low power consumption design. This paper introduces the design of a 2.4GHz class E power amplifier and RF switch design. PA consists of cascade stage with negative capacitance. This power amplifier can transmit 16dBm output power to a 50Ω load. The performance of the power amplifier and switch meet the specification requirements of the desired.
Combined Defence Services Examination (II) - 2014Performance analysis of swcn...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
NOVEL SLEEP TRANSISTOR TECHNIQUES FOR LOW LEAKAGE POWER PERIPHERAL CIRCUITSVLSICS Design
Static power consumption is a major concern in nanometre technologies. Along with technology scaling down and higher operating speeds of CMOS VLSI circuits, the leakage power is getting enhanced. As process geometries are becoming smaller, device density increases and threshold voltage as well as oxide thickness decrease to keep pace with performance. Two novel circuit techniques for leakage current reduction in inverters with and without state retention property are presented in this work. The power dissipation during inactive (standby) mode of operation can be significantly reduced compared to traditional power gating methods by these circuit techniques. The proposed circuit techniques are applied to inverters and the results are compared with earlier inverter leakage minimization techniques. Inverter
buffer chains are designed using new state retention low leakage technique and found to be dissipating lower power with state retention. All low leakage inverters are designed and simulated in cadence design environment using 90 nm technology files. The leakage power during sleep mode is found to be better by X 63 times for novel method. The total power dissipation has also reduced by a factor of X 3.5, compared to earlier sleepy keeper technique. The state retention feature is also good compared to earlier leakage power reduction methodologies.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Analysis of CMOS and MTCMOS Circuits Using 250 Nano Meter Technology csandit
The low-power consumption with less delay time has become an important issue in the recent
trends of VLSI. In these days, the low power systems with high speed are highly preferable
everywhere. Designers need to understand how low-power techniques affect performance
attributes, and have to choose a set of techniques that are consistent with these attributes .The
main objective of this paper is to describe, how to achieve low power consumption with
approximately same delay time in a single circuit. In this paper, we make circuits with CMOS
and MTCMOS techniques and check out its power and delay characteristics. The circuits
designed using MTCMOS technique gives least power consumption.
All the pre-layout simulations have been performed at 250nm technology on tanner EDA tool.
A 3-6 GHZ CURRENT REUSE NOISE CANCELLING LOW NOISE AMPLIFIER FOR WLAN AND WPA...IAEME Publication
In these paper CMOS LNA is designed for 3-6 GHz frequency range. These proposed LNA has the maximum flat gain to over all frequency range. These LNA has three stage at first stage to reduce noise with current reuse technique is used to increase the linearity at the first stage. At second stage cascaded common source is used to increase the gain with minimum noise figure. At third stage buffer is used because of its low noise figure. All these circuit can be analysed in ADS tool with 130 nm process with a 1.8V supply voltage.
It contains POWER MOSFET INTRODUCTION, POWER MOSFET STRUCTURE, types of power MOSFET, symbols, output characteristics , applications etc. https://amzn.to/3x56Qro click here to buy GATE 2022 Electronics & Communication Engineering - 35 Years Topic-wise Previous Solved Papers
A LOW POWER, LOW PHASE NOISE CMOS LC OSCILLATORIJEEE
In this paper a Double Cross Coupled Inductor capacitor based Voltage Control Oscillator (LC-VCO) is designed. In the proposed circuit the phase noise, tuning range with respect to control voltage, output power and the power dissipation of the circuit is analysed. Phase noise of approximate -96 dBc/Hz at frequency of 1MHz, frequency tuning range of 4.8 to 8.3 GHz (corresponding to 53.0% tuning range) obtained by varying the control voltage from 0 to 2.0 V, Output power of circuit -8.92 dBm at 50 Ohm resistance terminal and the power consumption of Circuit is 3.8 mW. This VCO are designed for 5.5 GHz. The circuit is designed on the UMC 180nm CMOS technology and all the simulation results are obtained using cadence SPECTRE Simulator.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Regular Expressions, most often known as “RegEx” is one of the most popular and widely accepted technology used for parsing the specific data contents from large text.
Power Gating Based Ground Bounce Noise ReductionIJERA Editor
As low power circuits are most popular the decrease in supply voltage leads to increase in leakage power with respect to the technology scaling. So for removing this kind of leakages and to provide a better power efficiency many power gating techniques are used. But the leakage due to ground connection to the active part of the circuit is very high rather than all other leakages. As it is mainly due to the back EMF of the ground connection it was called it as ground bounce noise. To reduce this noise different methodologies are designed. In this paper the design of such an efficient technique related to ground bounce noise reduction using power gating circuits and comparing the results using DSCH and Microwind low power tools. In this paper the analysis of adders such as full adders using different types of power gated circuits using low power VLSI design techniques and to present the comparison results between different power gating methods.
Static power optimization using dual sub threshold supply voltages in digital...VLSICS Design
Power dissipation in high performance systems requi
res more expensive packaging. In this situation, lo
w
power VLSI design has assumed great importance as a
n active and rapidly developing field. As the densi
ty
and operating speed of CMOS VLSI chip increases, st
atic power dissipation becomes more significant. Th
is
is due to the leakage current when the transistor i
s off this is threshold voltage dependent. This can
be
observed in the combinational and sequential circui
ts. Static power reduction techniques are achieved
by
means of operating the transistor either in Cut-off
or in Saturation region completely and avoiding th
e
clock in unnecessary circuits. In this work, “Dual
sub-threshold voltage supply” technique is used to
operate the transistor under off state or either in
on state by applying some voltage at the gate of t
he MOS
transistor. This static power reduction technique i
s to digital circuits, so that the power dissipatio
n is
reduced and the performance of the circuit is incre
ased. The designed circuits can be simulated by usi
ng
Mentor Graphics Backend Tool
Power Dissipation of VLSI Circuits and Modern Techniques of Designing Low Pow...IJSRD
This paper focus on the various sources of power dissipation in modern VLSI circuits. This paper also discuss the importance of designing low power VLSI circuits along with various techniques of power reduction and its advantages and disadvantages. It is basically a comparative study between various power reduction techniques in modern VLSI circuits.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Design of Memory Cell for Low Power ApplicationsIJERA Editor
Aggressive CMOS scaling results in lower threshold voltage and thin oxide thickness for transistors manufactured in nano regime. As a result, reducing the sub-threshold and tunneling gate leakage currents has become crucial in the design of ICs. This paper presents a new method to reduce the total leakage power dissipation of static random access memories (SRAMs) while maintaining their performance.
Low Power Design of Standard Digital Gate Design Using Novel Sleep Transisto...IJMER
In the nanometer range design technologies static power consumption is very important
issue in present peripheral devices. In the CMOS based VLSI circuits technology is scaling towards
down in respect of size and achieving higher operating speeds. We have also considered these
parameters such that we can control the leakage power. As process model design are getting smaller
the density of device increases and threshold voltage as well as oxide thickness decrease to maintain
the device performance. In this article two novel circuit techniques for reduction leakage current in
NAND and NOR inverters using novel sleepy and sleepy property are investigated. We have proposed a
design model that has significant reduction in power dissipation during inactive (standby) mode of
operation compared to classical power gating methods for these circuit techniques. The proposed
circuit techniques are applied to NAND and NOR inverters and the results are compared with earlier
inverter leakage minimization techniques. All low leakage models of inverters are designed and
simulated in Tanner Tool environment using 65 nm CMOS Technology (1volt) technologies. Average
power, Leakage power, sleep transistor
NOVEL SLEEP TRANSISTOR TECHNIQUES FOR LOW LEAKAGE POWER PERIPHERAL CIRCUITSVLSICS Design
Static power consumption is a major concern in nanometre technologies. Along with technology scaling down and higher operating speeds of CMOS VLSI circuits, the leakage power is getting enhanced. As process geometries are becoming smaller, device density increases and threshold voltage as well as oxide thickness decrease to keep pace with performance. Two novel circuit techniques for leakage current reduction in inverters with and without state retention property are presented in this work. The power dissipation during inactive (standby) mode of operation can be significantly reduced compared to traditional power gating methods by these circuit techniques. The proposed circuit techniques are applied to inverters and the results are compared with earlier inverter leakage minimization techniques. Inverter
buffer chains are designed using new state retention low leakage technique and found to be dissipating lower power with state retention. All low leakage inverters are designed and simulated in cadence design environment using 90 nm technology files. The leakage power during sleep mode is found to be better by X 63 times for novel method. The total power dissipation has also reduced by a factor of X 3.5, compared to earlier sleepy keeper technique. The state retention feature is also good compared to earlier leakage power reduction methodologies.
ANALYSIS OF CMOS AND MTCMOS CIRCUITS USING 250 NANO METER TECHNOLOGYcscpconf
The low-power consumption with less delay time has become an important issue in the recent
trends of VLSI. In these days, the low power systems with high speed are highly preferable
everywhere. Designers need to understand how low-power techniques affect performance
attributes, and have to choose a set of techniques that are consistent with these attributes .The
main objective of this paper is to describe, how to achieve low power consumption with
approximately same delay time in a single circuit. In this paper, we make circuits with CMOS
and MTCMOS techniques and check out its power and delay characteristics. The circuits
designed using MTCMOS technique gives least power consumption.
All the pre-layout simulations have been performed at 250nm technology on tanner EDA tool.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
FORCED STACK SLEEP TRANSISTOR (FORTRAN): A NEW LEAKAGE CURRENT REDUCTION APPR...VIT-AP University
Reduction in leakage current has become a significant concern in nanotechnology-based low-power, low-voltage, and high-performance VLSI applications. This research article discusses a new low-power circuit design the approach of FORTRAN (FORced stack sleep TRANsistor), which decreases the leakage power efficiency in the CMOS-based circuit outline in VLSI domain. FORTRAN approach reduces leakage current in both active as well as standby modes of operation. Furthermore, it is not time intensive when the circuit goes from active mode to standby mode and vice-versa. To validate the proposed design approach, experiments are conducted in the Tanner EDA tool of mentor graphics bundle on projected circuit designs for the full adder, a chain of 4-inverters, and 4-bit multiplier designs utilizing 180nm, 130nm, and 90nm TSMC technology node. The outcomes obtained show the result of a 95-98% vital reduction in leakage power as well as a 15-20% reduction in dynamic power with a minor increase in delay. The result outcomes are compared for accuracy with the notable design approaches that are accessible for both active and standby modes of operation.
A novel approach for leakage power reduction techniques in 65nm technologiesVLSICS Design
The rapid progress in semiconductor technology have led the feature sizes of transistor to be shrunk there
by evolution of Deep Sub-Micron (DSM) technology; there by the extremely complex functionality is
enabled to be integrated on a single chip. In the growing market of mobile hand-held devices used all over
the world today, the battery-powered electronic system forms the backbone. To maximize the battery life,
the tremendous computational capacity of portable devices such as notebook computers, personal
communication devices (mobile phones, pocket PCs, PDAs), hearing aids and implantable pacemakers has
to be realized with very low power requirements. Leakage power consumption is one of the major technical
problem in DSM in CMOS circuit design. A comprehensive study and analysis of various leakage power
minimization techniques have been presented in this paper a novel Leakage reduction technique is
developed in Cadence virtuoso in 65nm regim with the combination of stack with sleepy keeper approach
with Low Vth & High Vth which reduces the Average Power with respect Basic Nand Gate 29.43%, 39.88%,
Force Stack 56.98, 63.01%, sleep transistor with Low Vth & High Vth 13.90, 26.61% & 33.03%, 75.24%
with respect to sleepy Keeper 93.70, 56.01% of Average Power is saved.
A NOVEL APPROACH FOR LEAKAGE POWER REDUCTION TECHNIQUES IN 65NM TECHNOLOGIESVLSICS Design
The rapid progress in semiconductor technology have led the feature sizes of transistor to be shrunk there by evolution of Deep Sub-Micron (DSM) technology; there by the extremely complex functionality is enabled to be integrated on a single chip. In the growing market of mobile hand-held devices used all over the world today, the battery-powered electronic system forms the backbone. To maximize the battery life, the tremendous computational capacity of portable devices such as notebook computers, personal communication devices (mobile phones, pocket PCs, PDAs), hearing aids and implantable pacemakers has to be realized with very low power requirements. Leakage power consumption is one of the major technical problem in DSM in CMOS circuit design. A comprehensive study and analysis of various leakage power minimization techniques have been presented in this paper a novel Leakage reduction technique is developed in Cadence virtuoso in 65nm regim with the combination of stack with sleepy keeper approach with Low Vth & High Vth which reduces the Average Power with respect Basic Nand Gate 29.43%, 39.88%, Force Stack 56.98, 63.01%, sleep transistor with Low Vth & High Vth 13.90, 26.61% & 33.03%, 75.24% with respect to sleepy Keeper 93.70, 56.01% of Average Power is saved.
LEAKAGE POWER REDUCTION AND ANALYSIS OF CMOS SEQUENTIAL CIRCUITSVLSICS Design
A significant portion of the total power consumption in high performance digital circuits in deep submicron regime is mainly due to leakage power. Leakage is the only source of power consumption in an idle circuit. Therefore it is important to reduce leakage power in portable systems. In this paper two techniques such as transistor stacking and self-adjustable voltage level circuit for reducing leakage power in sequential circuits are proposed. This work analyses the power and delay of three different types of D flip-flops using pass transistors, transmission gates and gate diffusion input gates. . All the circuits are simulated with and without the application of leakage reduction techniques. Simulation results show that the proposed pass transistor based D flip-flop using self-adjustable voltage level circuit has the least leakage power dissipation of 9.13nW with a delay of 77 nS. The circuits are simulated with MOSFET models of level 54 using HSPICE in 90 nm process technology.
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Ji3516041608
1. Mrs. Y. Syamala et al Int. Journal of Engineering Research and Application
ISSN : 2248-9622, Vol. 3, Issue 5, Sep-Oct 2013, pp.1604-1608
RESEARCH ARTICLE
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OPEN ACCESS
Design and Implementation of Digital CMOS VLSI Circuits
Using Dual Sub-Threshold Supply Voltages
A. Suvir Vikram*, Mrs. K. Srilakshmi** And Mrs. Y. Syamala***
*
M.Tech, Embedded systems, Department of Electronics and Communication Engineering, Gudlavalleru
Engineering College, Gudlavalleru, A.P. India
**, ***
Department of Electronics and Communication Engineering, Gudlavalleru Engineering College,
Gudlavalleru, A.P. India
ABSTRACT
Power dissipation in high performance systems requires more expensive packaging. In this situation, low power
VLSI design has assumed great importance as an active and rapidly developing field. As the density and
operating speed of CMOS VLSI chip increases, power dissipation becomes more significant due to the leakage
current when transistor is OFF. This can be observed in both combinational and sequential circuits. Static power
reduction techniques are achieved by means of operating the transistor either in Cut-off or in Saturation region
completely and by avoiding the clock in unnecessary circuits. In this work, “Dual sub-threshold voltage supply”
technique is used to operate the transistor under either OFF or ON state by applying some voltage at the gate of
the MOS transistor. The designed circuits are simulated by using Mentor Graphics Backend Tool. With this
technique, nearly 10-75% of the power dissipation is reduced for designed circuits. Thereby, the performance of
circuit can be increased.
Keywords- Digital circuits, Dual sub-threshold leakage current, Power dissipation, Performance.
I.
Introduction
Low power design is the upcoming design
technology due to its high performance batteryportable digital systems. Presently there are many
portable devices that run on batteries like laptop, tablet
PC, mobile phone, ipod, etc. The power dissipation in
these devices is high. This is due to the supply of high
voltage to the low power components in the device. If
the supply power is low then the circuits operating
with that power should be capable of holding the
loads. For example, if an amplifier circuit is working
with low input power then the output should be
capable of driving a loud speaker. The complexity for
the high speed devices is more. Thermal problems
arise due to more hardware in a dense packing. For
this there is a need for the cooling process. So, there
is a need for heat sinks and cooling fans for heat
exhaust. The dual sub-threshold supply voltage
technique would help to operate where complex
devices need to consume less power. Thereby, the
complex circuits will dissipate less amount of power
[1].
In this work, the circuits are designed and
simulated in mentor graphics back-end tool through
Linux operating system. This provides the better way
to design the circuits from physical design and the
circuits can be simulated easily as in the real time. The
remaining sections of the paper as follows: section 1 is
about different low power design techniques, design
principles, power dissipation are given in section 2 and
3, implementation of the circuits are given in section 4
and finally results and conclusion are discussed.
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1. Different low power design techniques
There are certain low power techniques that
provide low power dissipation by using the low power
design techniques. The different techniques used in
low power design include [1] [2]:
i) Clock gating technique
ii) Multi-threshold CMOS (MTCMOS)
iii) Stacked Transistors
iv) Dynamic Threshold MOS (DTMOS)
v) Dynamic/voltage/frequency scaling
vi) Near sub-threshold supply
vii) Dual sub-threshold supply
In this work, among these techniques the dual
sub-threshold supply voltage is used to minimize
power dissipation. Therefore, by using multi threshold
supply voltages that are provided with near
sub-threshold voltage and the voltage can also be
varied around below or near sub-threshold voltages.
The dynamic power consumed by the transistors
depends on the switching frequency of the signal that
is applied at the gate of the transistor, full supply
voltage and the load capacitance used.
Supply voltage scaling was developed for
switching power reduction. It is an efficient method
for reducing switching power. It also helps to reduce
leakage power because the sub-threshold leakage is
due to Gate Induced Drain Leakage (GIDL) and Drain
Induced Barrier Leakage (DIBL) these are also
reduced as well as the gate leakage component when
the supply voltage is scaled down. Static supply
voltage scaling is a multiple supply voltage where as
different
supply
voltages
are
provided.
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2. Mrs. Y. Syamala et al Int. Journal of Engineering Research and Application
ISSN : 2248-9622, Vol. 3, Issue 5, Sep-Oct 2013, pp.1604-1608
In order to satisfy the speed performance the critical
and non-critical paths are made to operate with same
speed without disturbing the system performance.
II.
IV.
Implementation
Any CMOS circuits can be designed by
implementing the dual sub-threshold supply voltages
along with Vdd [5-7]. The designed combinational
circuits are decoder, 4x1 multiplexer and sequential
circuits are Moore and ring counter. The logic gates
are designed with CMOS transistors, the gates are
designed as shown below. The inverter with VDD as
supply voltage is given in fig. 1.
Power dissipation
Power dissipation is reduced by reducing the
length of the channel and width of the gate of
transistors [3]. This is the easy way to reduce the
power consumption of a transistor without disturbing
its operation. The low voltage operation is that the
conduction of transistor due to diffusion of charge
carriers. Transistors connected to low threshold supply
voltage conduct as the channel will be formed for very
low voltage. So that, even for a high threshold supply
voltage the power dissipation by the transistors is less.
The near sub-threshold supply voltage is sufficient for
the transistors to conduct. Static power essentially
consists of the power used when the transistor is not in
the process of switching.
Pstatic = Istatic*Vdd
(1)
The near threshold supply voltage is also provided in
order to make the transistors to conduct if there are
equal paths that there are no critical and non-critical
paths. Thereby, the static power dissipation is reduced.
Dynamic power is the sum of transient power
consumption (Ptransient) and capacitive load power
consumption (Pcap). Ptransient represents the amount of
power consumed when the device changes logic states.
Capacitive load power consumption is the power used
to charge the load capacitance.
Pdynamic = Pcap + Ptransient = (CL + C) *Vdd2 *f*N3 (2)
Where ‘N’ is the number of logic values that are
switching, ‘f’ is the switching frequency. The short
circuit power depends upon the frequency of the
transition. Hence the total power dissipated is the sum
of all the power dissipations in the circuit.
Ptotal =Pststic+Psc+Pdynamic
(3)
The total power dissipated is the sum of static
power dissipated, short circuit power and the dynamic
power consumed by the circuit. A way to reduce
leakage power consumption is to raise the Vth of some
gates. A higher Vth reduces the sub-threshold leakage
[4]. Hence, the transistors are designed in order to
reduce the power dissipation to maximum level. The
use of two power supplies makes some devices to
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allow the leakage current hence by providing a third
power supply that is greater than the threshold
supply voltage. This technique can be applied to any
circuit either combinational or sequential circuit.
Design Principles
Transistors are designed in such a way that
the width of the gate should be more when compared
with the length of the channel this is made such that
the for applied gate voltage the channel must be
formed for logic high in NMOS and logic low in
PMOS transistors. If the insulator used at the gate of
the MOS transistor is of very less width than the
channel length, hence if the transistor is OFF even
though certain current flows due to charge induced due
to capacitance effect. To reduce the leakage current
the length and width of MOS transistor is made
suitably for low voltage applications that to near
sub-threshold voltages.
III.
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Fig. 1: Inverter with VDD as supply voltage
In this circuit the input is applied to both
transistors depending on the applied input logic the
transistors conduct and the output is obtained. The
inverter circuit uses very less number of transistors
connected through the supply voltage to the ground.
Hence very low voltage is sufficient to operate the
inverter with very less power dissipation.
The NAND gate with VDD as supply voltage is given
in fig. 2. The circuit inputs are i1 and i2, depending
on the input voltage applied transistors conduct and
the output at O is obtained. The designed NAND gate
uses supply voltage VDD, either Low or High V th.
Depending upon the voltage applied the NAND gate is
operated with low leakage current and very low power
dissipation.
Fig. 2: NAND gate with VDD as supply voltage
Fig. 3 gives the functionality of 4-input OR
gate with VDD as supply voltage. In this circuit, the
inputs are i1, i2, i3, i4 and the output is O. The input is
applied to the transistors as the input voltage is very
low the transistors conduct. Depending upon the
number of transistors used in the circuit the supply
voltage is also varied, if there are a number of
transistors connected in series the supply voltage is to
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3. Mrs. Y. Syamala et al Int. Journal of Engineering Research and Application
ISSN : 2248-9622, Vol. 3, Issue 5, Sep-Oct 2013, pp.1604-1608
www.ijera.com
be increased in order to obtain the required output for
the given input.
be provided and the OR gate that drives all the outputs
from the AND gates require VDD as power supply and
also there are more number of transistors required for
4-input OR gate.
Fig. 3: 4-input OR gate with VDD as supply voltage
Fig. 6: 4x1 Multiplexer with dual sub-threshold
supply voltage
Fig. 4: 2-input AND gate with VDD as supply voltage.
Fig. 7: Simulation waveform of 4x1 Multiplexer with
dual sub-threshold supply voltage
The 2-input AND gate with VDD as supply
voltage is given in fig. 4. In this circuit the inputs are
in1 and in2. The output is O. Depending upon the
applied logic the transistors conduct and the output is
obtained. The AND gate designed with an inverter and
the NAND gate, hence inverter requires very low
power supply, NAND gate uses some high voltage
than the inverter. Hence High Vth supply voltage is
sufficient to drive the AND gate.
The Differential cascode voltage switched
(DCVS) level converter for NOT gate is shown in
fig. 8 and its simulation waveform is given in fig. 9. In
this circuit, the input is IN, output is OUT The DCVS
circuit designed with NOT gates and few transistors so
low threshold supply voltage is provided to the inner
NOT gate and high threshold supply voltage is
provided to the overall circuit and the output driven
NOT gate.
Fig. 5: D-Flip Flop
The D-Flip flop is given in fig. 5. In this
circuit, the inputs are Data in and Clk. The outputs are
Q and Qbar. The D-Flip flop requires high threshold
supply voltage, in order to dissipate low power.
Further, the designed circuits are discussed below.
The gate level diagram of 4x1 Multiplexer
with dual sub-threshold supply voltage is given in
fig. 6. The simulation waveform of 4x1 Multiplexer
with dual sub-threshold supply voltage is given in
fig. 7. In this simulation waveform, the inputs are i1,
i2, i3, i4, s0 and s1 and output is out. In this s0, s1 are
selection lines. The NOT gate can also be provided
with low threshold supply voltage as the voltage drop
in the NOT gate is very low, the AND gat uses more
number of transistors so high Vth supply voltage can
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Fig. 8: Differential cascode voltage switched (DCVS)
level converter for NOT gate
Fig. 9: Simulation waveform of DCVS level converter
for NOT gate
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4. Mrs. Y. Syamala et al Int. Journal of Engineering Research and Application
ISSN : 2248-9622, Vol. 3, Issue 5, Sep-Oct 2013, pp.1604-1608
The 2 × 4 Decoder with dual sub-threshold supply
voltage and its simulation waveforms are given in
figures 10 and 11 respectively.
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supply voltage is given in figures 14 and 15
respectively. The ring counter is a sequential circuit in
which D flip flops are used as the memory elements.
The inputs are clk and reset are provided to the
D flip flop directly with supply voltage of low V th, 4input OR gate is supplied with high Vth.
Fig. 10: 2×4 Decoder with dual sub-threshold supply
voltage
Fig. 14: Ring counter with dual sub-threshold supply
voltage
Fig. 11: Simulation waveform of 2×4 Decoder with
dual sub-threshold supply voltage
The Moore Machine with dual sub-threshold
supply voltage and its simulation waveform is given in
figures 12 and 13 respectively.
Fig. 12: Moore Machine with dual sub-threshold
supply voltage
Fig. 13: Moore Machine with dual sub-threshold
supply voltage
In the Moore machine the use of D flip flop is
to provide some delay for the given input from the OR
gate and AND gates the high Vth and VDD can be
altered (inter changed). The logic diagram of ring
counter and its functionality with dual sub-threshold
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Fig. 15: Simulation waveform of Ring Counter with
dual sub-threshold supply voltage
Power consumption varies from one circuit to another
circuit, as it depends upon the supply voltage, load
applied, type of components, the technique and
technology used to design the circuit. The 1.25µm
technology is used to implement these designed
circuits. The power dissipation of circuits with
sub-threshold supply voltages along with VDD is given
in Table 1. The results of power dissipation of circuits
with dual sub-threshold supply voltages with out VDD
are given in Table 2.
Table 1. Power dissipation of circuits with
dual sub-threshold supply voltages along with VDD
Supply voltages
Power
Designed circuit
(volts)
dissipation
VDD
(watts)
VDD
VDD
high
low
DCVS for NOT
0.7
0.35
0.15
2.279µ
gate
Nand
----------0.15
39.9354n
Inverter
----------0.15
25.9438f
2 to 4 Decoder
0.7
0.35
0.15
1.7851µ
4x1 Multiplexer
1.0
0.7
0.35
24.3857 µ
Moore
0.7
0.25
0.15
18.6552µ
Ring counter
1.5
----0.15
690.1097n
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5. Mrs. Y. Syamala et al Int. Journal of Engineering Research and Application
ISSN : 2248-9622, Vol. 3, Issue 5, Sep-Oct 2013, pp.1604-1608
Table 2. Power dissipation of circuits with
dual sub-threshold supply voltages with out VDD
Designed
Supply voltages Power
circuit
(volts)
dissipation
(watts)
Vth
Vth
low
high
DCVS
0.15
0.24
6.385 µ
for NOT gate
Nand
0.15
0.24
244.0433n
Inverter
0.15
0.24
34.680n
2 to 4Decoder
0.15
0.24
5.417 µ
4x1 Multiplexer 0.15
0.24
40.1425 µ
Moore
0.15
0.24
20.9725 µ
Ring counter
0.15
0.24
800.6924n
V.
Power Dissipation Comparison
The power dissipation by using the dual
sub-threshold supply voltage is more this is because of
the more leakage power and the output results are not
accurate, when compared with the power dissipation
using the dual sub-threshold supply voltage along with
VDD and the output is accurate. The Table 3 describes
the percentage of power dissipation between dual
sub-threshold supply voltage along with VDD and dual
sub-threshold supply voltage.
Table 3. Percentage reduction of power dissipation for
dual sub-threshold supply voltage with and without
supply voltage
Designed
circuits
Power dissipation (watts)
Power
reduction
(%)
without
VDD
6.385 µ
With
VDD
2.279µ
244.0433n
34.680n
5.417 µ
39.9354n
25.9438f
1.7851µ
24.3857 µ
20.9725 µ
18.6552µ
800.6924n
[2]
[3]
[4]
[5]
[6]
[7]
Kaushik Roy, Amit Agarwal, Chris H. Kim,
Circuit Techniques for Leakage Reduction,
LLC 2006.
Kaushik Roy, Saibal Mukhopadhyay and
Hamid Mahmoodi-Meimand IEEE, Leakage
Current Mechanisms and Leakage Reduction
Techniques in Deep-Submicrometer CMOS
Circuits, Contributed Paper, pp.315-318.
Shinichiro Mutoh , Yasuyuki Matsuya ,
Takahko Aoki and Junzo Yamada “1-V
Power Supply High-speed Digital Circuit
Technology with Multithreshold-Voltage
CMOS”, IEEE, vol. 30, pp.847-848, August
1995.
R. Gonzalez, B. M. Gordon, and M. A.
Horowib. “Supply and threshold voltage
scaling for low power CMOS”, IEEE, Vol.
32, No. 8, August 1997.
L. Clark, R. Patel and T. Beatty, “Managing
Standby and Active Mode Leakage Power in
Deep Sub-micron Design”, IEEE Circuits
Devices Mag., vol. 21, no. 1, pp. 7–18,
Jan./Feb. 2005.
Pankaj Pant, Rabindra K. Roy, and Abhijit
Chatterjee
“Dual-Threshold
Voltage
Assignment with Transistor Sizing for Low
Power CMOS Circuits” IEEE 2001 pp.303306.
Md.Asif Jahangir Chowdhury “An Efficient
VLSI Design Approach to Reduce Static
Power using Variable Body Biasing”, World
Academy of Science, Engineering and
Technology 2012, pp. 262-263.
12.15
Ring
counter
[1]
39.25
Moore
REFERENCES
85.93
99.99
75.21
40.1425 µ
www.ijera.com
DCVS NOT
Nand
Inverter
2 to 4
Decoder
4x1
Multiplexer
73.69
13.81
690.1097n
VI.
CONCLUSION
The power dissipation of designed digital
circuits using dual sub-threshold supply voltage along
with VDD is less when compared to the dual
sub-threshold supply voltage without VDD. The power
dissipation increases while increasing the VDD supply
voltage. Hence this technique provides a better
solution for the low power devices. Therefore high
supply voltages are restricted for these circuits. The
power saving is nearly 10-70% better for dual
sub-threshold supply voltage along with VDD as supply
voltages.
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