Microelectronic technology
This report briefly discusses the need for Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs), their structure and principle of operation. Then it details the fabrication and characterization of the MOSFETs fabricated at the microelectronic lab at University of Malaya
shows the simulation and analysis of a MOSFET device using the MOSFet tool. Several powerful analytic features of this tool are demonstrated, including the following:
calculation of Id-Vg curves
potential contour plots along the device at equilibrium and at the final applied bias
electron density contour plots along the device at equilibrium and at the final applied bias
spatial doping profile along the device
1D spatial potential profile along the device
Microelectronic technology
This report briefly discusses the need for Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs), their structure and principle of operation. Then it details the fabrication and characterization of the MOSFETs fabricated at the microelectronic lab at University of Malaya
shows the simulation and analysis of a MOSFET device using the MOSFet tool. Several powerful analytic features of this tool are demonstrated, including the following:
calculation of Id-Vg curves
potential contour plots along the device at equilibrium and at the final applied bias
electron density contour plots along the device at equilibrium and at the final applied bias
spatial doping profile along the device
1D spatial potential profile along the device
Short Channel Effects are governed by complex physical phenomena and mainly Influenced because of both vertical and horizontal electric field components.
To meet the current requirements of
Electronic devices, the miniaturization of devices is important. And so is Second Order effects which otherwise degrade the performance of devices.
Reduced channel length cause departures from long channel behaviour as two-dimensional potential distribution and high electric fields give birth to Short channel effects.
Analytical Modeling of Tunneling Field Effect Transistor (TFET)Abu Obayda
Tunneling Field-Effect Transistor (TFET) has emerged as an alternative for conventional CMOS by enabling the supply voltage, VDD, scaling in ultra-low power, energy efficient computing, due to its sub-60 mV/decade sub-threshold slope (SS). Given its unique device characteristics such as the asymmetrical source/drain design induced unidirectional conduction, enhanced on-state Miller capacitance effect and steep switching at low voltages, TFET based circuit design requires strong interactions between the device-level and the circuit-level to explore the performance benefits, with certain modifications of the conventional CMOS circuits to achieve the functionality and optimal energy efficiency. Because TFET operates at low supply voltage range (VDD<0.5V) to outperform CMOS, reliability issues can have profound impact on the circuit design from the practical application perspective. In this thesis report, we have analyzed the drain current characteristics of TFET with respect channel length. From our simulation result, it is observed that the drain current is minimum with respect to increasing channel length for Si and the drain current decreases for all the materials when the channel length is increased and after normalization lowest value of drain current is got for 10nm channel length.
SHORT-CHANNEL EFFECTS
A MOSFET is considered to be short when the channel length ‘L’ is the same order of magnitude as the depletion-layer widths (xdD, xdS). The potential distribution in the channel now depends upon both, transverse field Ex, due to gate bias and also on the longitudinal field Ey, due to drain bias When the Gate channel length <<1 m, short channel effect becomes important .
This leads to many
undesirable effects in MOSFET.
The short-channel effects are attributed to two physical phenomena:
A) The limitation imposed on electron drift characteristics in the channel,
B) The modification of the threshold voltage due to the shortening channel length.
In particular five different short-channel effects can be distinguished:
1. Drain-induced barrier lowering and “Punch through”
2. Surface scattering
3. Velocity saturation
4. Impact ionization
5. Hot electrons
Design & Performance Analysis of DG-MOSFET for Reduction of Short Channel Eff...IJERA Editor
An aggressive scaling of conventional MOSFETs channel length reduces below 100nm and gate oxide thickness below 3nm to improved performance and packaging density. Due to this scaling short channel effect (SCEs) like threshold voltage, Subthreshold slope, ON current and OFF current plays a major role in determining the performance of scaled devices. The double gate (DG) MOSFETS are electro-statically superior to a single gate (SG) MOSFET and allows for additional gate length scaling. Simulation work on both devices has been carried out and presented in paper. The comparative study had been carried out for threshold voltage (VT), Subthreshold slope (Sub VT), ION and IOFF Current. It is observed that DG MOSFET provide good control on leakage current over conventional Bulk (Single Gate) MOSFET. The VT (Threshold Voltage) is 2.7 times greater than & ION of DG MOSFET is 2.2 times smaller than the conventional Bulk (Single Gate) MOSFET.
Short Channel Effects are governed by complex physical phenomena and mainly Influenced because of both vertical and horizontal electric field components.
To meet the current requirements of
Electronic devices, the miniaturization of devices is important. And so is Second Order effects which otherwise degrade the performance of devices.
Reduced channel length cause departures from long channel behaviour as two-dimensional potential distribution and high electric fields give birth to Short channel effects.
Analytical Modeling of Tunneling Field Effect Transistor (TFET)Abu Obayda
Tunneling Field-Effect Transistor (TFET) has emerged as an alternative for conventional CMOS by enabling the supply voltage, VDD, scaling in ultra-low power, energy efficient computing, due to its sub-60 mV/decade sub-threshold slope (SS). Given its unique device characteristics such as the asymmetrical source/drain design induced unidirectional conduction, enhanced on-state Miller capacitance effect and steep switching at low voltages, TFET based circuit design requires strong interactions between the device-level and the circuit-level to explore the performance benefits, with certain modifications of the conventional CMOS circuits to achieve the functionality and optimal energy efficiency. Because TFET operates at low supply voltage range (VDD<0.5V) to outperform CMOS, reliability issues can have profound impact on the circuit design from the practical application perspective. In this thesis report, we have analyzed the drain current characteristics of TFET with respect channel length. From our simulation result, it is observed that the drain current is minimum with respect to increasing channel length for Si and the drain current decreases for all the materials when the channel length is increased and after normalization lowest value of drain current is got for 10nm channel length.
SHORT-CHANNEL EFFECTS
A MOSFET is considered to be short when the channel length ‘L’ is the same order of magnitude as the depletion-layer widths (xdD, xdS). The potential distribution in the channel now depends upon both, transverse field Ex, due to gate bias and also on the longitudinal field Ey, due to drain bias When the Gate channel length <<1 m, short channel effect becomes important .
This leads to many
undesirable effects in MOSFET.
The short-channel effects are attributed to two physical phenomena:
A) The limitation imposed on electron drift characteristics in the channel,
B) The modification of the threshold voltage due to the shortening channel length.
In particular five different short-channel effects can be distinguished:
1. Drain-induced barrier lowering and “Punch through”
2. Surface scattering
3. Velocity saturation
4. Impact ionization
5. Hot electrons
Design & Performance Analysis of DG-MOSFET for Reduction of Short Channel Eff...IJERA Editor
An aggressive scaling of conventional MOSFETs channel length reduces below 100nm and gate oxide thickness below 3nm to improved performance and packaging density. Due to this scaling short channel effect (SCEs) like threshold voltage, Subthreshold slope, ON current and OFF current plays a major role in determining the performance of scaled devices. The double gate (DG) MOSFETS are electro-statically superior to a single gate (SG) MOSFET and allows for additional gate length scaling. Simulation work on both devices has been carried out and presented in paper. The comparative study had been carried out for threshold voltage (VT), Subthreshold slope (Sub VT), ION and IOFF Current. It is observed that DG MOSFET provide good control on leakage current over conventional Bulk (Single Gate) MOSFET. The VT (Threshold Voltage) is 2.7 times greater than & ION of DG MOSFET is 2.2 times smaller than the conventional Bulk (Single Gate) MOSFET.
ULTRA HIGH SPEED FACTORIAL DESIGN IN SUB-NANOMETER TECHNOLOGYcscpconf
This work proposes a high speed and low power factorial design in 22nm technology and also it counts the effect of sub nano-meter constraints on this circuit. A comparative study for this
design has been done for 90nm, 45nm and 22nm technology. The rise in circuit complexity and speed is accompanied by the scaling of MOSFET’s. The transistor saturation current Idsat is an important parameter because the transistor current determines the time needed to charge and discharge the capacitive loads on chip, and thus impacts the product speed more than any other transistor parameter. The efficient implementation of a factorial number is carried out by using
a decremented and multipliers which has been lucidly discussed in this paper. Normally in a factorial module a number is calculated as the iterative multiplication of the given number to
the decremented value of the given number. A Parallel adder based decremented has been proposed for calculating the factorial of any number that also includes 0 and 1. The
performances are calculated by using the existing 90-nm CMOS technology and scaling down the existing technology to 45-nm and 22-nm.
Structural and Electrical Analysis of Various MOSFET DesignsIJERA Editor
Invention of Transistor is the foundation of electronics industry. Metal Oxide Semiconductor Field Effect Transistor (MOSFET) has been the key to the development of nano electronics technology. This paper offers a brief review of some of the most popular MOSFET structure designs. The scaling down of planar bulk MOSFET proposed by the Moore’s Law has been saturated due to short channel effects and DIBL. Due to this alternative approaches has been considered to overcome the problems at lower node technology. SOI and FinFET technologies are promising candidates in this area.
Investigation and design of ion-implanted MOSFET based on (18 nm) channel lengthTELKOMNIKA JOURNAL
The aim of this study is to invistgate the characteristics of Si-MOSFET with 18 nm length of ion implemented channel. Technology computer aided design (TCAD) tool from Silvaco was used to simulate the MOSFET’s designed structure in this research. The results indicate that the MOSFET with 18 nm channel length has cut-off frequency of 548 GHz and transconductance of 967 μS, which are the most important factors in calculating the efficiency and improving the performance of the device. Also, it has threshold voltage of (-0.17 V) in addition obtaining a relatively small DIBL (55.11 mV/V). The subthreshold slope was in high value of 307.5 mV/dec. and this is one of the undesirable factors for the device results by short channel effect, but it does not reduce its performance and efficiency in general.
Dual Metal Gate and Conventional MOSFET at Sub nm for Analog ApplicationVLSICS Design
The use of nanometer CMOS technologies (below 90nm) however brings along significant challenges for circuit design (both analog and digital). By reducing the dimensions of transistors many physical phenomenon like gate leakage, drain induced barrier lowering and many more effects comes into picture. Reducing the feature size in the technology of device with the addition of ever more interconnect layers, the density of the digital as well as analog circuit will increase while intrinsic gate switching delay is reduced . We have simulated conventional and DMG MOSFET at 30nm scale using Silvaco TAD tool and obtained result. A two dimensional device simulation was carried out and observed that DMG MOSFET has a low leakage current as compared to conventional MOSFET and find suitable application in analog circuits.
Relevance of Grooved NMOSFETS in Ultra Deep Submicron Region in Low Power App...VLSICS Design
To manage the increasing static leakage in low power applications, solutions for leakage reduction are sought at the device design and process technology levels. In this paper, 90nm, 70nm and 50 nm groovedgate nMOS devices are simulated using Silvaco device simulator. By changing the corner angle and adjusting few structural parameters, static leakage reduction is achieved in grooved nMOSFETS in ultralow power applications. The simulation results show that leakage contributing currents like the subthreshold current, punchthrough current and tunneling leakage current are reduced. The oxide thickness can be increased without increase in the gate induced drain leakage current, and ON-OFF current ratio is improved and maintained constant even in the deep submicron region. This study can be helpful for low power applications as the static leakage is reduced drastically, as well as be applicable to high speed devices as the ON current is maintained at a constant value. The results are compared with those of corresponding conventional planar devices to bring out the achievements of this work.
Secure Image Encryption using Two Dimensional Logistic Map
* Gangadhar Tiwari1, Debashis Nandi2, Abhishek Kumar3, Madhusudhan Mishra4 1, 2Department of Information Technology, NIT Durgapur (W.B.), India 3Department of Electronics and Electrical Engineering, NITAP, (A.P.), India 4Department of Electronics and Communication Engineering, NERIST, (A.P.), India
Non-Invertible Wavelet Domain Watermarking using Hash Function
*Gangadhar Tiwari1, Debashis Nandi 2, Madhusudhan Mishra3
1,2 IT Department, NIT, Durgapur-713209, West Bengal, India,
3ECE Department, NERIST, Nirjuli-791109, Arunachal Pradesh, India,
Converting UML class diagram with anti-pattern problems to verified code based on Event-B
Eman K. Elsayed
Mathematical and computer science Dep., Faculty of Science,
Al-Azhar University, Cairo, Egypt
Approach to Seismic Signal Discrimination based on Takagi-Sugeno Fuzzy Inference System
E. H. Ait Laasri, E. Akhouayri, D. Agliz, A. Atmani Electronic, Signal processing and Physical Modelling Laboratory, Physics’ Department, Faculty of Sciences, Ibn Zohr University, B.P. 8106, Agadir, Morocco
Unit Commitment Using a Hybrid Differential Evolution with Triangular Distribution Factor for Adaptive Crossover
N. Malla Reddy* K. Ramesh Reddy** and N. V. Ramana***
Intelligent e-assessment: ontological model for personalizing assessment activities
Rafaela Blanca Silva-López1, Iris Iddaly Méndez-Gurrola1, Victor Germán Sánchez Arias2
1 Universidad Autónoma Metropolitana, Unidad Azcapotzalco.
Av. San Pablo 180, Col. Reynosa Tamaulipas, Del. Azcapotzalco, México, D.F.
2 Universidad Nacional Autónoma de México
Circuito Escolar Ciudad Universitaria, 04510 México, D.F.
Visual Perception Oriented CBIR envisaged through Fractals and Presence Score
Suhas Rautmare, Anjali Bhalchandra
A. Tata Consultancy Services, Mumbai B. Govt. College of Engineering, Aurangabad
Measuring Sub Pixel Erratic Shift in Egyptsat-1 Aliased Images: proposed method
1M.A. Fkirin, 1S.M. Badway, 2A.K. Helmy, 2S.A. Mohamed
1Department of Industrial Electronic Engineering and Control, Faculty of Electronic Engineering,
Menoufia University, Menoufia, Egypt.
2Division of Data Reception Analysis and Receiving Station Affairs, National Authority for Remote Sensing and Space Sciences, Cairo, Egypt.
The State of the Art of Video Summarization for Mobile Devices:
Review Article
Hesham Farouk *, Kamal ElDahshan**, Amr Abozeid **
* Computers and Systems Dept., Electronics Research Institute, Cairo, Egypt.
** Dept. of Mathematics, Computer Science Division,
Faculty of Science, Al-Azhar University, Cairo, Egypt.
Overwriting Grammar Model to Represent 2D Image Patterns
1Vishnu Murthy. G, 2Vakulabharanam Vijaya Kumar
1,2Anurag Group of Institutions, Hyderabad, AP,India.
Texture Classification Based on Binary Cross Diagonal Shape Descriptor Texture Matrix (BCDSDTM)
1P.Kiran Kumar Reddy, 2Vakulabharanam Vijaya Kumar, 3B.Eswar Reddy
1RGMCET, Nandyal, AP, India, 2Anurag Group of Institutions, Hyderabad, AP, India
3JNTUA College of Engineering, India.
Improved Iris Verification System
Basma M.Almezgagi, M. A. Wahby Shalaby, Hesham N. Elmahdy Faculty of Computers and Information, Cairo University, Egypt.
Employing Simple Connected Pattern Array Grammar for Generation and Recognition of Connected Patterns on an Image Neighborhood
1Vishnu Murthy. G, 2V. Vijaya Kumar, 3B.V. Ramana Reddy
1,2Anurag Group of Institutions, Hyderabad, AP,India.
3Mekapati Rajamohan Reddy Institute of Technology and Science, Udayagiri, AP,India.
Bench Marking Higuchi Fractal for CBIR
A. Suhas Rautmare, B. Anjali Bhalchandra
A. Tata Consultancy Services, Mumbai B. Govt. College of Engineering, Aurangabad
1. Surround Gate MOSFET
An Intelligent Technique To
Reduce Short Channel Effect
Presenter: Koushik Guha
Dept. of Electronics & Communication
Engineering
National Institute of Technology Silchar, India
2. Outline
Basic MOSFET Operation
Historical Perspective and Motivation
Downscaling of MOSFET
Brief of Short Channel Effect
Introduction of SOI Technology
Double Gate Technology
Multi Gate Technology and its features
DMDG-SG ………An Innovative Technology
2D Modeling of DMDG-SG MOSFET
Model Validation with Simulated Results
Conclusion
References
3. The Metal Oxide Semiconductor Field-Effect Transistor
(MOSFET)
In layman terms, MOSFET
acts like a switch
5. Motivation
• Silicon-only planar transistors are
fast approaching their scaling
limit.
• Short channel effects limiting
scaling into sub nanometer regime.
• Oxide thickness cannot be scaled
down further, problems of
tunneling.
• Need to keep Silicon technology
as the base technology while
innovating future devices; cost is
an important factor.
• Performance and power
dissipation need to be improved.
• Smaller is faster !!
8. Scaling limits of BULK MOSFET
• Limit for supply voltage (<0.6V)
•
Limit for further scaling of tox (<2nm)
• Minimum channel length Lg= 50nm
• Discrete dopant fluctuations
• Dramatic short-channels effects (SCE)
9. How can we follow Moore’s law?
By moving to Multiple Gate MOSFETs
MG might be the unique viable alternative
to build nano MOSFETs when Lg<50nm
Because:
- Better control of the channel from the gates
- Reduced short-channel effects
- Better Ion/Ioff
- Improved sub-threshold slope
(60mV/decade)
- No discrete dopant fluctuations
18. Short Channel Effect in bulk-MOS
n+ drain
n+ source
p substrate
n+ poly gate
Gate
Vdd
n+ drain
n+ source
p substrate
n+ poly gate
Gate
Vdd
Short channel effect in bulk-CMOS devices is
a major barrier to scaling
24. SOI – The technology of the future
Welcome to the world of Silicon On Insulator
Highlights
• Reduced junction capacitance.
• Absence of latch up.
• Ease in scaling (buried oxide need not
be scaled).
• Compatible with conventional Silicon
processing
• Sometimes requires fewer steps to
fabricate.
• Reduced leakage.
• Improvement in the soft error rate.
Drawbacks
• Drain Current Overshoot.
• Kink effect
• Thickness control (fully depleted
operation).
• Surface states.
25. SOI Technology
Silicon-on-Insulator (SOI) Approach
Silicon channel layer grown on a layer
of oxide.
Absence of junction capacitance makes
this an attractive option.
Low leakage currents and compatible
fabrication technology.
26. Silicon-on-Insulator (SOI) Approach
Silicon channel layer grown on a layer
of oxide.
Absence of junction capacitance makes
this an attractive option.
Low leakage currents and compatible
fabrication technology.
27. Classification of SOI MOSFETs
Conventional MOSFET Partially depleted SOI
MOSFET
Fully depleted SOI
MOSFET
• Silicon film thickness greater than bulk depletion width for a partially-depleted
MOSFET and less than the gate depletion width for a fully-depleted MOSFET.
• Partially depleted MOSFETs often plagued by KINK effects, fully depleted devices
virtually free from such effects.
• Partially depleted devices can be faster than fully depleted devices under certain
operating conditions.
29. Advantages of Double Gate Devices
Front Gate
Back Gate
DrainSource
body
n+
source
n+
drain
Gate
(metal/poly)
Gate
(metal/poly)
Front Gate
Back Gate
DrainSource
body
n+
source
n+
drain
Gate
(metal/poly)
Gate
(metal/poly)
• Short channel effect control
– Better scalability
– Lower sub threshold
current
• Higher On Current
• Near-Ideal Sub threshold
slope
• Lower Gate Leakage
• Elimination of Vt variation
due to Random dopant
fluctuation
DG devices are very
promising for circuit
design in sub-50nm
technology
30. Field Lines for Single-Gate & Double-Gate SOI
MOSFETs
S D
G
S D
G
G
E-Fieldlines
Regular SOI MOSFET Double-gate MOSFET
Double gates
electrically shield
the channel
To reduce SCE’s,
aggressively
reduce Si layer
thickness
Single-Gate SOI Double-Gate
BOX BOX
32. Why Multi-Gate SOI MOSFETs ?
• Higher current drive => better performance
• Prophesized to show higher tolerance to scaling.
• Better integration feasibility, raised source-drain structure, ease in integration.
• Larger number of parameters to tailor device performance
34. Gate All Around MOSFET- 3D View
VG
VDVS
L
DRAINSOURCE CHANNEL
VG
Gates
Gates
Oxide
W
X
Z
Y
VG
VDVS
L
DRAINSOURCE CHANNEL
VG
Gates
Gates
Oxide
W
X
Z
Y
X
Z
Y
Si TSi
SiO2
TOX
Si TSi
SiO2
TOX
Si TSi
SiO2
TOX
Si TSi
SiO2
TOX
a) b)
VG
VDVS
L
DRAINSOURCE CHANNEL
VG
Gates
Gates
Oxide
W
X
Z
Y
VG
VDVS
L
DRAINSOURCE CHANNEL
VG
Gates
Gates
Oxide
W
X
Z
Y
X
Z
Y
Si TSi
SiO2
TOX
Si TSi
SiO2
TOX
Si TSi
SiO2
TOX
Si TSi
SiO2
TOX
a) b)
WSi
VG
VDVS
L
DRAINSOURCE CHANNEL
VG
Gates
Gates
Oxide
W
X
Z
Y
VG
VDVS
L
DRAINSOURCE CHANNEL
VG
Gates
Gates
Oxide
W
X
Z
Y
X
Z
Y
Si TSi
SiO2
TOX
Si TSi
SiO2
TOX
Si TSi
SiO2
TOX
Si TSi
SiO2
TOX
a) b)
VG
VDVS
L
DRAINSOURCE CHANNEL
VG
Gates
Gates
Oxide
W
X
Z
Y
VG
VDVS
L
DRAINSOURCE CHANNEL
VG
Gates
Gates
Oxide
W
X
Z
Y
X
Z
Y
Si TSi
SiO2
TOX
Si TSi
SiO2
TOX
Si TSi
SiO2
TOX
Si TSi
SiO2
TOX
a) b)
WSi
VG
VDVS
L
DRAINSOURCE CHANNEL
VG
Gates
Gates
Oxide
W
X
Z
Y
VG
VDVS
L
DRAINSOURCE CHANNEL
VG
Gates
Gates
Oxide
W
X
Z
Y
X
Z
Y
Si TSi
SiO2
TOX
Si TSi
SiO2
TOX
Si TSi
SiO2
TOX
Si TSi
SiO2
TOX
a) b)
VG
VDVS
L
DRAINSOURCE CHANNEL
VG
Gates
Gates
Oxide
W
X
Z
Y
VG
VDVS
L
DRAINSOURCE CHANNEL
VG
Gates
Gates
Oxide
W
X
Z
Y
X
Z
Y
Si TSi
SiO2
TOX
Si TSi
SiO2
TOX
Si TSi
SiO2
TOX
Si TSi
SiO2
TOX
a) b)
WSi
35. Cylindrical Dual Material Surround Gate
MOSFET(CDMSG-MOS)
Cross section view of CDSG
3D structure of CDSG
Structure of n
channel FD-DMSG
MOSFET
36. DMDG-SG MOSFET- A Potential competitor
Dual-material gate (DMG) structure employs “gate-material engineering” instead of
“doping engineering” with different work functions to introduce a potential step in the
channel. This leads to a suppression of SCEs and an enhanced source side
electric field resulting in increased carrier transport efficiency in the channel region.
Vertical DMSG structure Cross section view through channel
37. 2D Surface Potential Modeling of Our Structure
In conventional Surrounding Gate MOSFET (C-SG)
MOSFET, the gate is made of only one material, but in
the Double material isolated Surround Gate (DMISG)
MOSFET structure, we have two gates with different
work functions and doping density under them along
with a gap in the considered structure.
Simulated structure of DMSIG
After solving 2D Poisson equation at different
surfaces and satisfying boundary conditions at
interfaces we obtained mathematical function of
Electric Field and Electrostatic Potential at different
interfaces and along the channel region.
38. Model Validation with Simulation Results
Fig. 1 shows the variation of the surface electrostatic potential for the typical device parameters with gate
voltages of M1 and M2 fixed at 0.0 V. The drain voltage is varied from 0.0 to 1.5 V. As can be observed from the
Fig. 2 that the model is able predict the surface potential in agreement with the 2D simulation results for the
different drain voltages.
It is observed that the variation in the drain voltage is not changing the minimum potential under the gate M1. It
means that the gate M1 is “screened” from the variations in the drain voltage and all the drain voltage is dropped
under M2 only. This reduces the DIBL and threshold voltage roll off effects.
Figure:1
39. Figure.2 shows the Electric Field variation along the channel. It is observed that field
remains almost constant under Metal 1 and peak field occurs at the gap region.
Figure:2
40. Figure 3 shows the electrostatic potential comparison of simulation results for different L1
/L2
ratios,
VGS1
=0.1 V, VGS2
=0.8 V and VDS
=0.5 V. It is observed that when the L1
is larger than the L2
, then
potential under M1
is less affected due to the VDS
voltage whereas when the L1
is lower than the L2
,
then the drain voltage influences the potential under M1
. In the case when L1
=L2
then this looks to be
optimum case and the potential under M1
is also not much affected by VDS
, reducing the DIBL effect.
Figure:3
41. Conclusions
• DMDG-SG devices are promising for low power and high frequency circuit design
– Better scalability
• DMDG-SG technologies provide unique opportunities for designers
– Proper use of different types of devices can maximize the advantage of the DG
technologies.
– A new physics based surface potential model for the double material double gate
surrounding gate (DMDG-SG) SOI MOSFET has been successfully derived and
validated with the TCAD Device simulation results.
– It has been found that our model is in well agreement with different drain biasing
voltages and other device parameters.
– The usefulness of this device against the SCEs and HCEs has also been demonstrated
through the simulations results.
Surround Gate technologies with proper design
parameters are attractive for circuit design in
nanometer era
42. References
1. A. Breed and K.P. Roenker, “Dual-gate (FinFET) and TriGate MOSFETs: Simulation
and design,” Proceedings of the International Semiconductor Device Research
Symposium (ISDRS-2003), pp. 150-151, December 2003.
2. J-T. Park and J-P Colinge, “Multiple-Gate SOI MOSFETs: Device Design
Guidelines,” IEEE Transactions on Electron Devices, pp. 2222-2228, vol. 49, no. 12,
Dec. 2002.
3. Aniket Breed and Kenneth P. Roenker, “A Small-signal, RF Simulation Study of
Multiple-gate MOSFET Devices,” IEEE Topical Meeting on Silicon Monolithic ICs
in RF Systems, Atlanta, GA, Sept. 2004.
4. Biswajit Ray , Santanu Mahapatra “A New Threshold Voltage Model for Omega
Gate Cylindrical Nanowire Transistor”, 21st International Conference on VLSI
Design, 1063-9667/08, DOI 10.1109/VLSI.2008.52, page 447-452.
5. Cong Li, Yiqi Zhuang, Ru Han “Cylindrical surrounding-gate MOSFETs with
electrically induced source/drain extension”, Microelectronics Journal
