This document discusses the increasing complexity of system-on-chip (SoC) designs and the challenges this poses for design tools. SoCs now contain large amounts of both analog and digital circuitry, with the analog portions becoming more complex. Traditional analog design flows are manual and do not scale well. New model-based approaches are needed. Digital designs also continue growing in capacity but current tools cannot handle blocks larger than 1 million cells, forcing designs to be artificially partitioned. Distributed implementation approaches can help improve productivity by implementing larger designs across multiple servers. Finally, signoff closure times are too long, requiring new integrated flows to reduce iterations and speed up the final netlist closure.