More returns for the day

1. FPGA Prototyping
http://uohyd.ac.in/
Prof. Samrat L. Sabat
Centre for Advanced Studies in
Electronics Science & Technology

2. v
GDP: Gross Development Product
5th Largest Economy
Y = C + I + (X - M)+ G
~ 3.8 Trillion USD
1 Tr USD~8100000 Cr. INR
According to the World Bank Forecast, India will reach 5 Trillion USD
What does India need to do reach 5 Trillion USD Economy

3. v
Country-wise Exports-Imports (2022-23) & (2021-22)

4. v
Country-wise Exports-Imports (2022-23) & (2021-22)

5. v
IMPORTS FROM CHINA IN 2022-2023

6. v
Where We Stand?

8. Moore’s Law

9. 9
System on Chip
A device which is designed and fabricated for a specific purpose by a specific owner.
• FPGA vs ASIC vs. SoC
• SoC must have a processor & runs embedded software, ASIC need not be.
• SoC is a superset of ASIC
Electronics System - > ASICS -> FPGAs -> EDA tool -> Design Service . IP - >
Embedded software

10. Chips Everywhere!
CMOS Camera
SmartPen
Source: Dr. K. Pister, UC Berkeley
Chips that Fly?

11. Electronics and the Car
•More than 30% of the cost of a car is now in Electronics
•90% of all innovations will be based on electronic systems

12. SoC architecture
The end user is influenced by the application with
which they are presented
Enabled by a SW stack of middleware, driver, OS

13. SoC architecture
The end user is influenced by the application with
which they are presented

14. (c) Giovanni De Micheli 14
Applications
Applications developer do not have direct access to
• Internal memory, Low level hardware aspects
• The Sw stack is matched by a hardware stack (many boards,many IPs…)
Intricate relationship between different company types
IP provider -> Semiconductor industries - > Integrators -> OEM (All enables
software developers – Interaction with them is A big problem for tool industry)

15. Integrated CMOS Radio
A
D
Analog RF
Timing
recovery
phone
book
Java
VM
ARQ
Keypad,
Display
Control
Filters
Adaptive
Antenna
Algorithms
Equalizers MUD
Accelerators
(bit level)
analog digital
DSP core
uC core
(ARM)
Logic
Dedicated Logic
and Memory
Integrate within the same chip very diverse system functions like:
wireless channel control, signal processing, codec algorithms,
radio modems, RF transceivers… and implement them
using a heterogeneous architecture

16. Communication versus Computation
Computation cost (2004): 60 pJ/operation (assuming continued
scaling)
Communication cost (minimum):
• 100 m distance: 20 nJ/bit @ 1.5 GHz
• 10 m distance: 2 pJ/bit @ 1.5 GHz
Computation versus Communications
• 100 m distance: 300 operations == 1bit
• 10 m distance: 0.03 operation == 1bit
Computation/Communication requirements vary with distance,
data type, and environment

17. A typical SoC development Project
Wireless headset design – 65nm technology
• Expected production run of 27 months Breakeven after 34 months (~3 years after start)
• Average volume of 1.5 million unit per month sell
• Avg. Selling price is $5.5
• Total Development cost is $31,650,000
RTL code + Verification -> 3+9 =12 months
Physical Design by 15 months (simultaneously Software development starts ; OS & porting, High
level Application goes upto 27 months)
Mask by 17 months
Post silicon verification starts at 19 months and takes many months
Predict profit 3 years before
!!!

18. How to make it easier
Start software sooner
IF SW development and validation started 5 months earlier, time to breakeven reduced by 5 months
The earlier start to sw development & validation is provided by prototyping, -> Impact on ROI is
significant
Build Prototype !!!
• Prototype provides early representation of hardware, specifically of chips and their surroundings
• Marketing needs ; interactions with customers, investors
• Architecture exploration, software development and verification

19. Architecture exploration
• Chip architects to make decisions w.r.t chip topology, power, speed,
performance of processor, bus width etc– experience plays an role!!!, many
joint discussions based on statistics
Software development:
• Port legacy code and develop new software; They need executable
representation of the chip- which runs at real time and reflects software
interfaces with hardware
Verification

20. Advantages of prototyping
Powerful method for verifying the design of hardware and validating the software in models with
mimic the target environment.
FPGA based prototyping is more important when software and hardware are integrated first time

21. Different types of Prototyping
Virtual prototyping – Synopsys Innovator
• Perform software debug on a fully function virtual model
• - Not time accurate- Time accuracy Vs speed
• They are crated before RTL
Software Development Kit : SDK
• Just enough accuracy
• End user environment can be experienced virtually.
• Developed without target hardware

23. (c) Giovanni De Micheli 23
FPGA prototyping in silicon but
pre-silicon (not a push-button process)
Fully functional hardware validation for SoCs, Boards, IOs
• They implement the same RTL as SoC
• Run real time with all peripherals
• Functionally and time accurate
After software prototyping
• Reluctance to change RTL
First silicon as a prototype platform: Enable software development on silicon chip
• Low cost development board; Run in real time with full accuracy
• Available very late in the design flow

24. Why do you do it?
High performance and accuracy;
Feasibility test
Real time data flow- interfacing real-world; Demo out of the lab
Protocol testing in real-time data speed

25. Why FPGA for signal processing

26. FPGA Technology for FPGA based
Prototyping

27. Xilinx FPGA

28. 32 KB block RAM

31. Design flow (1)
Design and implement a simple unit permitting to speed up
encryption with RC5-similar cipher with fixed key set on 8031
microcontroller. Unlike in the experiment 5, this time your unit has to
be able to perform an encryption algorithm by itself, executing 32
rounds…..
Library IEEE;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity RC5_core is
port(
clock, reset, encr_decr: in std_logic;
data_input: in std_logic_vector(31downto 0);
data_output: out std_logic_vector(31downto 0);
out_full: in std_logic;
key_input: in std_logic_vector(31downto 0);
key_read: out std_logic;
);
end AES_core;
Specification (Lab Experiments)
VHDL description (Your Source Files)
Functional simulation
Post-synthesis simulation
Synthesis

32. Design flow (2)
Implementation
Configuration
Timing simulation
On chip testing

33. Fpga Design Flow & Tool

34. Simulation Tools Many others…
Testbench

35. What is Synthesis?
Synthesis is the process that converts RTL into a technology specific gate-level netlist
optimized for a set of pre-defined constraints.
You start with: A behavioural RTL design, A standard cell library, a set of design
constraints
You finish with : A gate-level netlist, mapped to the standard cell library, optimized for
area, speed and power
Synthesis
RTL design Standard cell library Design constraints
Optimized gate level netlist
Mapped to standard library
(ASIC)
LUT,FF (PGA)

36. Different types of synthesis
X=a+b+c;
Y=M*X
module foo
(a,b,c,Y);
input [3:0] a;
…
High level synthesis/
Architectural synthesis RTL synthesis
Logic synthesis
Layout synthesis

37. RTL code Gate level netlist
Library file .lib
Design constraint (.sdc)
Synthesis

38. RTL description
Functional
simulation
Logic Synthesis
Post Synthesis
simulation
Design partition
Logic Optimization
Initial gatelevel netlist
RTL development
RTL integration
Translation
Unoptimized Boolean
representation
Technology Maping & Opt.
Timing Check
Optimized
Netlist
Post synthesis
sim.

39. Paradigm Shift in SoC Design
System on a board
System on a Chip

40. Evolutionary Problems
􀂋 Key Challenges
– Improve productivity
– HW/SW codesign
– Integration of analog & RF IPs
– Improved DFT
Emerging new technologies:
– Greater complexity
– Increased performance
– Higher density
– Lower power dissipation
􀂋 Evolutionary techniques:
- IP (Intellectual Property) based design

41. Traditional Embedded System
FPGA
CLK
CLK
CLK
custom
IF-logic
SDRAM SDRAM
SRAM SRAM
SRAM
Memory Controller
UART
Display
Controller
Timer
Power Supply
L
C
Audio
Codec
CPU
(uP / DSP) Co-
Proc.
GP I/O
Address
Decode
Unit
Ethernet
MAC
Interrupt
Controller
Images by H.Walder

42. Configurable System on Chip (CSoC)
Power Supply
SDRAM SDRAM
SRAM SRAM
SRAM
L
C
Audio
Codec EPROM
Images by H.Walder

43. Source: The Zynq Book
Traditional Architecture

44. Source: The Zynq Book
FPGA with Soft Processor Core

45. Source: The Zynq Book
Zynq Architecture

46. Source: The Zynq Book
Embedded SoC Architecture

48. Basic Elements of HW/SW Interfaces
48

49. Source: The Zynq Book
Implement Embedded SoC on Zynq

50. Memory-Mapping Interface
50
Each component has an unique address in the system address
space.

51. Memory Mapped Interfaces
51

52. Memory Mapped Interfaces
52
volatile int *MMReg = (int*) 0x8000;
int value = *MMReg;
*MMReg = 5;

53. FIFOs
53
This FIFO has two slave interfaces.

54. Coprocessor Interfaces
54
+ high throughput, fixed latency
- non-reusable.

55. Coprocessor Interfaces: An Example
55
put rD, FLSx // copy register rD to FSL interface FSLx
get rd, FSLx // copy FSL interface FSLx into register rD

57. Source: Xilinx Video Tutorials
Zynq Highlights

58. ARM Processor Roadmap
Source: Xilinx White Paper: Extensible Processing Platform

59. Basic Design Flow for Zynq SoC
Source: The Zynq Book

60. Source: The Zynq Book
The Zynq Processing System

61. Source: The Zynq Book
Application Processing Unit
(APU)
APU programming is through Xlinx SDK

62. Source: The Zynq Book
PS External Interfaces: MIO

63. Programmable Logic (PL) CLBs and IOBs
Source: The Zynq Book

64. Basic Logic Elements (BLEs)
12 2 FPGA Architectures: An Overview

65. Switch Matrix
16 2 FPGA Architectures: An Overview

66. Source: The Zynq Book
PL: Special Resources

67. Source: The Zynq Book
AXI Interconnects and Interfaces
9 AXI interfaces
between PS and
PL.