1) The document discusses the shift from 2D chip design to 3D chip stacks using through-silicon vias (TSVs) which provides benefits like reuse of older process nodes, higher performance, lower power, and reduced cost. 2) It outlines the short, medium, and long term roadmaps for 3D chip integration over the next few years targeting different markets from servers to mobile devices. 3) New EDA tool requirements are needed to support the 3D chip design flow including new layout rules, models, and thermal/mechanical analysis to account for the third dimension and TSVs.

1. Tools and Methodologies for 3D-IC
Design
AJ Incorvaia
Vice President, Silicon Package Board Group
May, 2012

2. Where we are today – Industry View
Paradigm Shift from 2D SoCs  3D stacks
Moving to vertical stacking using TSVs provides
Reuse of older process node
(IP reuse/ heterogeneous int.)
Higher performance
Low Power
Reduced Cost
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3. Short, medium and long term path to 3D-IC
EDA work starts at least 3-4 years earlier
Si Partitioning Memory Cube Logic + memory Wide IO + Logic High
with TSV with TSVs w/ 2.5D TSV with TSVs performance
Interposer computing
Interposer
• MARKET : Server •MARKET : Mobile,
Tablet, gaming • MARKET : CPU,
• Market : FPGA & Computing • MARKET : GPU,
processors MCMs etc
Gaming Console
• Xilinx in 2010 • IBM & Micron
• ST-E /LETI •ST-E /LETI
•Altera in 2012 testchip • ST testchip in WIOMING in 2011
2010 WIOMING in 2011
• 2011-2012 • 2012-2013 • 2013-2014 • 2013-2014 • ~ 2015
SHORT MEDIUM LONG
Standards, Ecosystem, Cost
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4. So what changes with 3DIC in EDA world?
Revamped EDA requirements
New Layout Rules (e.g. alignments)
New Layout Layer (e.g. Back Side RDL)
New Layout & Electrical Feature
(e.g. TSV)
New Floorplanning &
Blockage Rules (TSV)
Thermal & mechanical
constraints
New Models, Rules
Courtesy : Qualcomm
4 © 2012 Cadence Design Systems, Inc. All rights reserved.

5. 3DIC Design Flow Challenges
System Level Exploration
3D Floorplan – Optimized power
New 3DIC Design Flow
Plan and TSV/Bump locations
Implementation
Challenges
Placement, Optimization and Routing
Extraction and Analysis
Manage Power, Thermal and SI
DFT for 3DIC Stack
& Diagnostics
Silicon Package Co-Design
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5

6. 3D Stack Die Editor
Die to Die Co-Design Flow
Open access enables interaction
between analog and digital
3D Floorplan – Optimized power
Plan and TSV/Bump locations
Custom Editing
Typical 3D-IC Design Flow
TSV /Bump RDL Routing
3D IR Drop Analysis
Silicon Interposer
IC-Package Co design flow 3D Thermal Maps
Back-side Bump Management
Silicon Interposer
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7. Partnering with the Ecosystem
Designers: Analysis Driven Design &
Stacking Methodology
System House: Multi-Die
Integrated Package Prototyping
Foundry & IDM : Rules, Stacking
Layers & Modeling
Everyone : DFM/Yield/Reliability
And Redundancy
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8. Collaboration with Foundry Partners
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9. Foundation required to enable 3D-IC
Custom, Digital & Package solutions need to understand
3D constructs
Modeling and database infrastructure to support TSVs, Micro bumps, backside
metals
Seamless Digital, Custom and Package co-design
Comprehensive solutions needed to span all aspects of IC design, including
digital design, analog and custom design and packaging co-design
Ecosystem partnerships
Ecosystem is still developing, so partnerships are needed to develop
methodologies and proof points between the various stakeholders
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10. Industry Example: 2.5D Using Silicon Interposer Source: RTI 3D conference 2010 proceedings
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11. Industry Example: 3D IC Stack with WideIO
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12. Industry Example: 3D IC Stack with WideIO
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13. Summary: Cadence silicon-proven 3D-IC solution
Plan Implement  Test  Verify
• Cadence is the technology leader
providing complete and integrated 3D-
IC solution
– Plan->implement->test->verify
– 1st to market wide I/O memory controller
• Developed in close partner-
collaboration for 5+ years with leading
foundries and customers
• Multiple 3D-IC tapeouts
– Multiple testchip experience: Memory over
logic (28 nm), logic over analog, logic over
Logic, 3-stack dies
– Production design tapeouts
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14. 14 © 2012 Cadence Design Systems, Inc. All rights reserved.