1) Mobiveil develops high-speed interface IP blocks such as RapidIO, PCIe, Ethernet, and DDR controllers. 2) Designing high-speed interfaces presents challenges related to signal integrity, power integrity, validation, and bringing systems to production. 3) Key considerations for high-speed interface controllers include supporting increasingly high data rates up to 16Gb/s while maintaining signal quality over long interconnects using techniques like adaptive equalization and training.

1. High Speed Interface Panel
Keys to High Speed Interface Designs Today
Ravi Thummarukudy
Mobiveil

2. Mobiveil Introduction
 Major interface products are RapidIO, PCI Express, Ethernet and
DDRn high speed controller IP blocks
 Also licenses high speed controller blocks for NVM Express, Flash
Controllers and LDPC Error correction
• Located in Milpitas, Chennai/Bangalore (India)
 Currently Chair of RapidIO Marketing Working Group, Vice- Chair
of RapidIO BFM Working group, Contributor member for NVM
Express & HMC
Agenda
4/20/2015
2

3. Various Challenges of High Speed Design
Validation ProductionDesign, Modeling and Analysis
Define System
Architecture
Mobile XDR™ Memory Controller and DRAM Interface
Define Solution
Space
Full System Modeling
Signal and Power
Integrity Analysis
BER Analysis
Thermal and
Mechanical Analysis
Analog and Digital
Design
(Prototype) System
Bringup and Debugging
Component Validation
Package and PCB
Design
6
L
P
C
B
DDR2/DDR3
PHY
DDR2
or
DDR3
DDR2
or
DDR3
DDR2
or
DDR3
DDR2
or
DDR3
T
Optional Cost Reduction
(products w/ long lifecycle)
Production/Field
Failure Analysis
OEM Enablement –
Production System
Validation
Definition
(Prototype) System
Characterization
Pre-Silicon Post-Silicon
Signal Integrity Flow
Power Integrity Flow
Courtesy: Rambus/ Modiveil presentation at Designcon 2015

4. Typical Interface Controller
TRX TTXTCTL
DRX DTXDCTL
MRX MTXMCTL
Trans
Layer
Link
Layer
MAC Layer
PCS
Application
Interface
Serial Link
PMA
Receive Control Transmit
Logic
Layers
PHY
Layers
SERDES
Layer Primary Function
TL Quality of Service, Deadlock free
data transfer
DL Reliable Delivery of Data
between Link Partners
MAC Link Initialization, Training
PCS Encode/Decode, Elastic Buffers
PMA Clock Data Recovery,
Serializer/De-Serializer, AFE, PLL

5. Interconnect ‘Check In’
Interconnect
Requirements
RapidIO Infiniband Ethernet PCIe The Meaning of
Low Latency
switch silicon: ~100 nSec
memory to memory : < 1 uSec
Scalability
support any topology, 1000’s of
nodes, true peer-to-peer
Integrated HW
Termination
integrated into SoCs and
guaranteed, in order delivery
without software overhead
Power
Efficient
3 layers terminated in hardware,
Integrated into SoC’s
Fault Tolerant
supports hot swap and fault
tolerance
Deterministic
guaranteed, in order delivery with
deterministic flow control
Top Line
Bandwidth
supports > 8 Gbps/lane
5Courtesy: Rapidio.org

6. Challenges for Controllers
 Serial Links approaching 16G/25G Baud rates
 Signals transmitted over a link are degraded by losses and characteristic impedance
discontinuities in the interconnect media.
 The losses increase with increasing Baud rate and interconnect media length
 The signal degradation can be negated by the use of equalization in the transmitter and/or
receiver (Adaptive Equalization and Training).
• Lack of PHY <-> Logical Layer interface boundary/Definition in some of the standards
• Handshake required between PHY and Logical Layer to handle AET Implementation
 Increased Bandwidth poses challenges on Logical Layer Implementation choices
• Portability of designs across various technologies
• Configurability for different applications (High Performance vs Low Power)
• Pre Silicon verification with Verification IP(Bus Functional Models)
• Post Silicon Validation, Certification, Compliance Certification