The document proposes a framework to improve the bug fix verification process by allowing designers to instantly check the effect of fixes through on-the-fly expression calculation, without needing to recompile or resimulate the entire design. This is done by analyzing code changes, determining affected statements, and generating virtual signals to show expression results on the waveform. The goals are to minimize design re-spins caused by bugs found late and speed up the fix verification process. Initial results showed the approach works for simple logic changes. Future work aims to support more complex constructs and better compare multiple fixes.