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The Road From 2D To 3D                       IC Integration                       An EDA Perspective                     M...
Through Silicon Via (TSV)    A Solution Without a Problem for… Half of a Century                  W. Shockley…            ...
“> 2D” IC Integration Is There Already    (a) Stacked Dice (SiP), and (b) PoPCONFIDENTIAL 3                               ...
“> 2D” IC Integration Is There Already    STMicroelectronics’ Example of (a)        8 dice stack                          ...
“> 2D” IC Integration Is There Already    Apple’s A4 Is Only the Most Recent Example of (a) + (b)CONFIDENTIAL 5           ...
“3D” IC Integration Is Warming Up    But not All the Applications Are at the Same Stage    • Production           – Imagin...
“3D” IC Integration Is Warming Up    “2D” Dice    • FPGA           – Xilinx’ Virtex 7    • Processor & memory           – ...
“3D” IC Integration Is Warming Up    “3D” Functions and/or Modules    • Digital + analog & mixed-signal +…           – Pla...
“3D” IC Integration Is Warming Up    Gates and/or Transistors    • e.g. PMOS on top tier, NMOS on bottom tier           – ...
“3D” IC Integration Is Warming Up    Form Factor (6.5 x 6.5 x 5 millimeters) CMOS Camera    Lenses + Image Sensor + Image ...
“3D” IC Integration Is Warming Up    NAND Cost Reduction Flat Above 64Gb       8 dice stack                               ...
“3D” IC Integration Is Warming Up    Bandwidth > 1Tb per secondCONFIDENTIAL 12                                 Source: L. ...
“3D” IC Integration Is Warming Up    Many Cores : the Bus Is 2-3X Slower Than the CPUCONFIDENTIAL 13                      ...
“3D” IC Integration Is Warming Up    Many Cores : the Bus Is 2-3X Slower Than the CPU                  Polaris            ...
“3D” IC Integration Is Warming Up    Digital Plus Analog & Mixed-Signal         CMOS 45 nanometers,                    Act...
“3D” IC Integration Is Warming Up    Digital Plus Analog & Mixed-Signal         CMOS 45 nanometers,                       ...
“3D” IC Integration Looks Great…    Technology Node nth “2D” ≅ Technology Node (n-2)th “3D”    • Much easier D and A&M/S i...
“3D” IC Integration Looks Great…    But Its Impact Has not Been Fully Weighed Up           Cost overhead          – CoO ~ ...
Via First, Via “Middle”, Or Via Last ?    The Future May Be Via “Middle”, the Present Is Via Last    Among the Issues : Wh...
µ    1µ TSV Cross Section (A/R = 10:1)    Ultra Thin Silicon : 5 –10µ… Wafer Handling not Trivial !CONFIDENTIAL 20        ...
TSV Are Huge !    At 32/28nm, TSVs Are 5-10X a Standard-Cell’s Height,    and 15-30X the M1 Pitch…                        ...
TSV Number Is Crucial !    How Do You Find the Sweet Spot ?CONFIDENTIAL 22                                       Source: S...
TSV Placement Is Crucial !    Power/Timing (Wirelength) vs. Yield                  Irregular, Optimal      Regular, Sub-Op...
TSV Number And Placement Is Crucial !    CMP & SPE May Cause Significant Yield Losses    Not to Mention the Drop in Utiliz...
Stress Proximity Effects (SPE)    Carrier Mobility Changes Due to TSV “Pulling” Silicon                  NMOS             ...
Thousands of Transistors Impacted !    TSV-Related SPE 100X Bigger Than Strain-Related OneCONFIDENTIAL 26                 ...
Stress Proximity Effects (SPE)    Analog Keep-Out Zone (KOZ) 10X Bigger Than Digital One !CONFIDENTIAL 27                 ...
Test Becomes A Challenge    Pre-Bond Testability vs. Power Savings        Tier Testable, Higher Power      Tier not testab...
Assembly Is A Challenge Too    Binning Is Critical to Improve Yield; IDDQ Test May HelpCONFIDENTIAL 29                    ...
Assembly Is A Challenge Too    Binning Is Critical to Improve Yield; IDDQ Test May HelpCONFIDENTIAL 30                    ...
Many Flavors Of “> 2D”…    Marketing Imagination Is the Only Limit…CONFIDENTIAL 31                                        ...
Many Flavors Of “> 2D” IC Integration    Designer’s Imagination Is the Only Limit…    •    Homogeneous vs. heterogeneous  ...
What About A Phased Approach ?    ”2.5D” IC Integration, to Begin With : Homogeneous,    Side-by-Side, Passive Interposer,...
What About A Phased Approach ?    “2.5D” IC Integration is There Already : Xilinx’ Virtex 7CONFIDENTIAL 34                ...
What About A Phased Approach ?    “2.5D” IC Integration Delivers on PromisesCONFIDENTIAL 35                               ...
What About A Phased Approach ?    The “Level Road” from 2D to 3D IC Integration    • The impact of “2.5D” IC integration l...
Eventually… “~ 3D” IC Integration    Heterogeneous Side-by-Side, Active Interposer,    and Some Homogeneous Stack (F2B ?) ...
Conclusions    • “3D” IC integration will happen          – It’s all about when, not if    • But, the road from “2D” to “3...
‫ָה‬                   ‫ד‬                  May 4th, 2011                  Tel Aviv, IsraelCONFIDENTIAL 39© Synopsys 2011
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Track e the road from 2 d to 3d integration -synopsys

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Track e the road from 2 d to 3d integration -synopsys

  1. 1. The Road From 2D To 3D IC Integration An EDA Perspective Marco Casale-Rossi Synopsys, Inc.CONFIDENTIAL 1© Synopsys 2011
  2. 2. Through Silicon Via (TSV) A Solution Without a Problem for… Half of a Century W. Shockley… …and M. Smith & E. Stern U.S. Patent # 3,044,909: “Semicon- U.S. Patent #: 3,343,256 “Methods of ductive Wafer and Method of Making the Making Thru‐Connections in Semicon- ‐ Same”, 1958 ductor Wafers”, 1964CONFIDENTIAL 2© Synopsys 2011
  3. 3. “> 2D” IC Integration Is There Already (a) Stacked Dice (SiP), and (b) PoPCONFIDENTIAL 3 Source: C. Cognetti, STMicroelectronics, EMC3D 2007© Synopsys 2011
  4. 4. “> 2D” IC Integration Is There Already STMicroelectronics’ Example of (a) 8 dice stack 0.88 millimeters 40 micronsCONFIDENTIAL 4 Source: C. Cognetti, STMicroelectronics, LETI 2007© Synopsys 2011
  5. 5. “> 2D” IC Integration Is There Already Apple’s A4 Is Only the Most Recent Example of (a) + (b)CONFIDENTIAL 5 Source: TechInsights, 2010© Synopsys 2011
  6. 6. “3D” IC Integration Is Warming Up But not All the Applications Are at the Same Stage • Production – Imaging (form factor, e.g. STMicroelectronics et al.) – Memories (cost, e.g. Samsung, Hynix et al.) • Pre-Production – FPGA (connectivity, bandwidth, and yield, e.g. Xilinx) • Advanced Research – Many cores (bandwidth, e.g. Intel) – Home entertainment (A+D, e.g. ST) – Automotive (MEMS, e.g. ST, Infineon et al.) – Wireless (performance, e.g. Qualcomm et al.)CONFIDENTIAL 6© Synopsys 2011
  7. 7. “3D” IC Integration Is Warming Up “2D” Dice • FPGA – Xilinx’ Virtex 7 • Processor & memory – Small to medium # of TSVs (hundreds to thousand) – Single array of TSVs, single KOZ (on a per core basis) • SoCs with well identifiable, self contained/sufficient sub- systems – But pros/cons are unique for each SoCCONFIDENTIAL 7© Synopsys 2011
  8. 8. “3D” IC Integration Is Warming Up “3D” Functions and/or Modules • Digital + analog & mixed-signal +… – Placement of modules across 3D stack – Medium to large # of TSV (thousands) • Heterogeneous, multi-foundry, “Lego-like” – Somebody’s dream is everybody else’s nightmare : who does take ownership – and responsibility ! – of “3D” integration ? – Standards are a pre-requisiteCONFIDENTIAL 8© Synopsys 2011
  9. 9. “3D” IC Integration Is Warming Up Gates and/or Transistors • e.g. PMOS on top tier, NMOS on bottom tier – Huge # of TSVs (millions, even billions) – Better performance and lower powerCONFIDENTIAL 9 Source: P. Leduc, LETI, D43D 2010© Synopsys 2011
  10. 10. “3D” IC Integration Is Warming Up Form Factor (6.5 x 6.5 x 5 millimeters) CMOS Camera Lenses + Image Sensor + Image Processor + Memory BanksCONFIDENTIAL 10 Source: STMicroelectronics 2010© Synopsys 2011
  11. 11. “3D” IC Integration Is Warming Up NAND Cost Reduction Flat Above 64Gb 8 dice stack 0.56 millimeters 50 micronsCONFIDENTIAL 11 Source: C.-G. Hwang, Samsung, IEDM 2006© Synopsys 2011
  12. 12. “3D” IC Integration Is Warming Up Bandwidth > 1Tb per secondCONFIDENTIAL 12 Source: L. Madden, Xilinx, 2010© Synopsys 2011
  13. 13. “3D” IC Integration Is Warming Up Many Cores : the Bus Is 2-3X Slower Than the CPUCONFIDENTIAL 13 Source: S. Borkar, Intel, Asia Academic Forum 2006© Synopsys 2011
  14. 14. “3D” IC Integration Is Warming Up Many Cores : the Bus Is 2-3X Slower Than the CPU Polaris FreyaCONFIDENTIAL 14 Source: S. Borkar, Intel, Asia Academic Forum 2006 Intel, Asia Academic Forum 2006 Source: S. Borkar,© Synopsys 2011
  15. 15. “3D” IC Integration Is Warming Up Digital Plus Analog & Mixed-Signal CMOS 45 nanometers, Active interposer, 25mm2, digital functions, CMOS 130 nanometers, 1V & 1.8V 32mm2, analog functions, 1.xV, 2.5V & 3.3VCONFIDENTIAL 15 Source: L. Bonnot, STMicroelectronics, D43D 2009© Synopsys 2011
  16. 16. “3D” IC Integration Is Warming Up Digital Plus Analog & Mixed-Signal CMOS 45 nanometers, Active interposer, 25mm2, digital functions, CMOS 130 nanometers, 1V & 1.8V 32mm2, analog functions, 1.xV, 2.5V & 3.3VCONFIDENTIAL 16 Source: L. Bonnot, STMicroelectronics, D43D 2009 STMicroelectronics, D43D 2009 Source: L. Bonnot,© Synopsys 2011
  17. 17. “3D” IC Integration Looks Great… Technology Node nth “2D” ≅ Technology Node (n-2)th “3D” • Much easier D and A&M/S integration • Smaller footprint, higher bandwidth e.g. L/2 • Shorter global interconnect – 3 tier -33%, 4 tier -50% • Better timing and lower power L Silicon area = L2, footprint = L2 Silicon area = L2, footprint = L/4 Corner to corner distance = 2L Corner to corner distance = L + εCONFIDENTIAL 17© Synopsys 2011
  18. 18. “3D” IC Integration Looks Great… But Its Impact Has not Been Fully Weighed Up Cost overhead – CoO ~ $150/Wafer (5%) @ 300mm • For the sake of comparison, SOI ~ 5%, and HKMG ~ 10-20% Area & power savings cannot be given for granted – Heavily depend on TSV number and placement – Smaller footprint means less room for the bumps… Yield loss vs. “2D” – D2D, D2W, W2W,… but also F2F, F2B,… – From KGD (Known Good Die) to… MGD (Maybe Good Die) – Variation does require binning ! Design tools, flows, and methodologiesCONFIDENTIAL 18 Source: P. Sieblerud, Semitool, EMC3D 2009© Synopsys 2011
  19. 19. Via First, Via “Middle”, Or Via Last ? The Future May Be Via “Middle”, the Present Is Via Last Among the Issues : Who Does What, A/R, Cost TSV ∅ ≤ 1µ, A/R ~ 10:1 µ FEOL + BEOL FEOL TSV ∅ 1-10µ, 5:1 ≤ A/R ≤ 10:1 µ BEOL FEOL + BEOL TSV ∅ 10-100µ, 1:1 ≤ A/R ≤ 5:1 µCONFIDENTIAL 19 Source: Yole Development 2007; Y. Guillou, ST-Ericsson, D43D 2010© Synopsys 2011
  20. 20. µ 1µ TSV Cross Section (A/R = 10:1) Ultra Thin Silicon : 5 –10µ… Wafer Handling not Trivial !CONFIDENTIAL 20 Source: P. Leduc, LETI, D43D 2010© Synopsys 2011
  21. 21. TSV Are Huge ! At 32/28nm, TSVs Are 5-10X a Standard-Cell’s Height, and 15-30X the M1 Pitch… TSV Keep-Out Zone (KOZ)CONFIDENTIAL 21 Source: S.K. Lim, GATECH, EDPS 2010; P. Leduc, LETI, D43D 2010© Synopsys 2011
  22. 22. TSV Number Is Crucial ! How Do You Find the Sweet Spot ?CONFIDENTIAL 22 Source: S.K. Lim, GATECH, EDPS 2010© Synopsys 2011
  23. 23. TSV Placement Is Crucial ! Power/Timing (Wirelength) vs. Yield Irregular, Optimal Regular, Sub-OptimalCONFIDENTIAL 23 Source: S.K. Lim, GATECH, EDPS 2010© Synopsys 2011
  24. 24. TSV Number And Placement Is Crucial ! CMP & SPE May Cause Significant Yield Losses Not to Mention the Drop in Utilization 2D Place & Route 3D Place & RouteCONFIDENTIAL 24 Source: S.K. Lim, GATECH, EDPS 2010© Synopsys 2011
  25. 25. Stress Proximity Effects (SPE) Carrier Mobility Changes Due to TSV “Pulling” Silicon NMOS (∆µ/µ)e = ↑ 3.52% PMOS (∆µ/µ)h = ↑ 13.26% Copper NMOS Silicon TSV Silicon (∆µ/µ)e = ↑ 6.32% PMOS (∆µ/µ)h = ↓ 14.36%CONFIDENTIAL 25 Source: S.K. Lim, GATECH, EDPS 2010© Synopsys 2011
  26. 26. Thousands of Transistors Impacted ! TSV-Related SPE 100X Bigger Than Strain-Related OneCONFIDENTIAL 26 Source: J. Kawa, Synopsys, 2010© Synopsys 2011
  27. 27. Stress Proximity Effects (SPE) Analog Keep-Out Zone (KOZ) 10X Bigger Than Digital One !CONFIDENTIAL 27 Source: J. Kawa, Synopsys, 2010© Synopsys 2011
  28. 28. Test Becomes A Challenge Pre-Bond Testability vs. Power Savings Tier Testable, Higher Power Tier not testable, Lower PowerCONFIDENTIAL 28 Source: S.K. Lim, GATECH, EDPS 2010© Synopsys 2011
  29. 29. Assembly Is A Challenge Too Binning Is Critical to Improve Yield; IDDQ Test May HelpCONFIDENTIAL 29 Source: D. Marculescu, CMU, D43D 2010© Synopsys 2011
  30. 30. Assembly Is A Challenge Too Binning Is Critical to Improve Yield; IDDQ Test May HelpCONFIDENTIAL 30 Source: D. Marculescu, CMU, D43D 2010© Synopsys 2011
  31. 31. Many Flavors Of “> 2D”… Marketing Imagination Is the Only Limit…CONFIDENTIAL 31 Source: www.bk.com 2010© Synopsys 2011
  32. 32. Many Flavors Of “> 2D” IC Integration Designer’s Imagination Is the Only Limit… • Homogeneous vs. heterogeneous • Side-by-side vs. stack… vs. combinations • Face-to-face, face-to-back,… • Passive vs. active interposer • Single-sided vs. double-sidedCONFIDENTIAL 32© Synopsys 2011
  33. 33. What About A Phased Approach ? ”2.5D” IC Integration, to Begin With : Homogeneous, Side-by-Side, Passive Interposer, Single-sided (F2F) e.g. FPGA e.g. FPGA e.g. FPGA e.g. FPGA Passive Silicon InterposerCONFIDENTIAL 33© Synopsys 2011
  34. 34. What About A Phased Approach ? “2.5D” IC Integration is There Already : Xilinx’ Virtex 7CONFIDENTIAL 34 Source: L. Madden, Xilinx, 2010© Synopsys 2011
  35. 35. What About A Phased Approach ? “2.5D” IC Integration Delivers on PromisesCONFIDENTIAL 35 Source: L. Madden, Xilinx, 2010© Synopsys 2011
  36. 36. What About A Phased Approach ? The “Level Road” from 2D to 3D IC Integration • The impact of “2.5D” IC integration looks more “affordable” – All the necessary ingredients are at hands, or within our reach • The “pros” outnumber the “cons” – 10X higher connectivity among dice vs. package – 100X more bandwidth per Watt, ~ 10X less latency – Better yield vs. monolithic SOC, as well as vs. “3D” stack – Without the thermal burden of “3D” stack • May become the launch pad towards “3D”CONFIDENTIAL 36 Source: L. Madden, Xilinx, 2010© Synopsys 2011
  37. 37. Eventually… “~ 3D” IC Integration Heterogeneous Side-by-Side, Active Interposer, and Some Homogeneous Stack (F2B ?) Memory Memory Analog Memory Digital RF Active Silicon InterposerCONFIDENTIAL 37© Synopsys 2011
  38. 38. Conclusions • “3D” IC integration will happen – It’s all about when, not if • But, the road from “2D” to “3D” must be carefully “paved”, to be technically and economically viable for all the players – Including EDA ! True collaborative effort is required • What about a phased approach ? – “2.5D” IC integration may be more “affordable”, due to its evolutionary impact • Synopsys is working with its partners to make sure that all the EDA ingredients are timely availableCONFIDENTIAL 38© Synopsys 2011
  39. 39. ‫ָה‬ ‫ד‬ May 4th, 2011 Tel Aviv, IsraelCONFIDENTIAL 39© Synopsys 2011

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