Conventionally polysilicon is used in MOSFETs for gate material. Doping of polysilicon and thus changing the workfunction is carried out to change the threshold voltage. Additionally polysilicon is not favourable as gate material for smaller dimensional devices because of its high thermal budget process and degradation due to the depletion of the doped polysilicon, thus metal gate is preferred over polysilicon. Control of workfunction in metal gate is a challenging task. The use of metal alloys as gate materials for variable gate workfunction has been already reported in literature. In this work various threshold voltage techniques has been analyzed and a novel aligned dual metal gate technique is proposed for threshold voltage control in FinFETs.
introduction, types & structure of MOSET ,turn ON and OFF of device, working, I-V characteristics of MOSFET,Different regions of operations,applications, adv & disadvantages
The three terminals of the FET are known as Gate, Drain, and Source.
It is a voltage controlled device, where the input voltage controls by the output current.
In FET current used to flow between the drain and the source terminal. And this current can be controlled by applying the voltage between the gate and the source terminal.
So this applied voltage generate the electric field within the device and by controlling these electric field we can control the flow of current through the device.
The MOSFET is an important element in embedded system design which is used to control the loads as per the requirement. The MOSFET is a high voltage controlling device provides some key features for circuit designers in terms of their overall performance.
Design & Performance Analysis of DG-MOSFET for Reduction of Short Channel Eff...IJERA Editor
An aggressive scaling of conventional MOSFETs channel length reduces below 100nm and gate oxide thickness below 3nm to improved performance and packaging density. Due to this scaling short channel effect (SCEs) like threshold voltage, Subthreshold slope, ON current and OFF current plays a major role in determining the performance of scaled devices. The double gate (DG) MOSFETS are electro-statically superior to a single gate (SG) MOSFET and allows for additional gate length scaling. Simulation work on both devices has been carried out and presented in paper. The comparative study had been carried out for threshold voltage (VT), Subthreshold slope (Sub VT), ION and IOFF Current. It is observed that DG MOSFET provide good control on leakage current over conventional Bulk (Single Gate) MOSFET. The VT (Threshold Voltage) is 2.7 times greater than & ION of DG MOSFET is 2.2 times smaller than the conventional Bulk (Single Gate) MOSFET.
introduction, types & structure of MOSET ,turn ON and OFF of device, working, I-V characteristics of MOSFET,Different regions of operations,applications, adv & disadvantages
The three terminals of the FET are known as Gate, Drain, and Source.
It is a voltage controlled device, where the input voltage controls by the output current.
In FET current used to flow between the drain and the source terminal. And this current can be controlled by applying the voltage between the gate and the source terminal.
So this applied voltage generate the electric field within the device and by controlling these electric field we can control the flow of current through the device.
The MOSFET is an important element in embedded system design which is used to control the loads as per the requirement. The MOSFET is a high voltage controlling device provides some key features for circuit designers in terms of their overall performance.
Design & Performance Analysis of DG-MOSFET for Reduction of Short Channel Eff...IJERA Editor
An aggressive scaling of conventional MOSFETs channel length reduces below 100nm and gate oxide thickness below 3nm to improved performance and packaging density. Due to this scaling short channel effect (SCEs) like threshold voltage, Subthreshold slope, ON current and OFF current plays a major role in determining the performance of scaled devices. The double gate (DG) MOSFETS are electro-statically superior to a single gate (SG) MOSFET and allows for additional gate length scaling. Simulation work on both devices has been carried out and presented in paper. The comparative study had been carried out for threshold voltage (VT), Subthreshold slope (Sub VT), ION and IOFF Current. It is observed that DG MOSFET provide good control on leakage current over conventional Bulk (Single Gate) MOSFET. The VT (Threshold Voltage) is 2.7 times greater than & ION of DG MOSFET is 2.2 times smaller than the conventional Bulk (Single Gate) MOSFET.
Analysis of pocket double gate tunnel fet for low stand by power logic circuitsVLSICS Design
For low power circuits downscaling of MOSFET has a major issue of scaling of voltage which has ceased
after 1V. This paper highlights comparative study and analysis of pocket double gate tunnel FET
(DGTFET) with MOSFET for low standby power logic circuits. The leakage current of pocket DGTFET
and MOSFET have been studied and the analysis results shows that the pocket DGTFET gives the lower
leakage current than the MOSFET. Further a pocket DGTFET inverter circuit is design in 32 nm
technology node at VDD =0.6 V. The pocket DGTFET inverter shows the significant improvement on the
leakage power than multi-threshold CMOS (MTCMOS) inverter. The leakage power of pocket DGFET and
MTCMOS inverter are 0.116 pW and 1.83 pW respectively. It is found that, the pocket DGTFET can
replace the MOSFET for low standby power circuits.
A Study On Double Gate Field Effect Transistor For Area And Cost Efficiencypaperpublications3
Abstract: Proposal for a field effect transistor had been presented, with numerical device simulations to verify the title in every manner possible. The two transitional field effect transistors like pMOS and nMOS functions are simultaneously performed, working as one or as the other according to the voltage applied to the gate terminal. Increase in the circuit speed is observed when this technology is implemented on the device suggested with respect to the standard CMOS technology, presented a drastic reduction of number devices and associated parasitic capacitances. In addition to it IC obtained with the proposed device are fully compatible with the standard CMOS technology and the fabrication processes. Fabrication of Static Ram cells with three transistors only with minimum dimensions and a single bit line by saving silicon area and increasing the memory performance with respect to standard CMOS technologies. It is also presented that the fully compatible CMOS process can be used to successfully manufacture the new FET structure.
Operational transconductance amplifier-based comparator for high frequency a...IJECEIAES
Fin field-effect transistor (FinFET) based analog circuits are gaining importance over metal oxide semiconductor field effect transistor (MOSFET) based circuits with stability and high frequency operations. Comparator that forms the sub block of most of the analog circuits is designed using operational transconductance amplifier (OTA). The OTA is designed using new design procedures and the comparator circuit is designed integrating the sub circuits with OTA. The building blocks of the comparator design such as input level shifter, differential pair with cascode stage and class AB amplifier for output swing are designed and integrated. Folded cascode circuit is used in the feedback path to maintain the common mode input value to a constant, so that the differential pair amplifies the differential signal. The gain of the comparator is achieved to be greater than 100 dB, with phase margin of 65°, common mode rejection ratio (CMRR) of above 70 dB and output swing from rail to rail. The circuit provides unity gain bandwidth of 5 GHz and is suitable for high sampling rate data converter circuits.
Performance Comparison of CMOS and Finfet Based Circuits At 45nm Technology U...IJERA Editor
According to the Moore’s Law, the number of transistors in a unit chip area double every two years. But the existing technology of integrated circuit formation is posing limitations to this law. CMOS technology shows certain limitations as the device is reduced more and more in the nanometer regime out of which power dissipation is an important issue. FinFET is evolving to be a promising technology in this regard. This paper aims to analyze and compare the characteristics of CMOS and FinFET circuits at 45nm technology. Inverter circuit is implemented in order to study the basic characteristics such as voltage transfer characteristics, leakage current and power dissipation. Further the efficiency of FinFET to reduce power as compared to CMOS is proved using SRAM circuit. The results show that the average power is reduced by 92.93% in read operation and by 97.8% in write operation.
Performance Evaluation of GaN Based Thin Film Transistor using TCAD Simulation IJECEIAES
As reported in past decades, gallium nitride as one of the most capable compound semiconductor, GaN-based high-electron mobility transistors are the focus of intense research activities in the area of high power, high-speed, and high-temperature transistors. In this paper we present a design and simulation of the GaN based thin film transistor using sentaurus TCAD for the extracting the electrical performance. The resulting GaN TFTs exhibits good electrical performance in the simulated results, including, a threshold voltage of 12-15 V, an on/off current ratio of 6.5×10 7 ~ 8.3×10 , and a subthreshold slope of 0.44V/dec. Sentaurus TCAD simulations is the tool which offers study of comprehensive behavior of semiconductor structures with ease. The simulation results of the TFT structure based on gallium nitride active channel have great prospective in the next-generation flat-panel display applications.
Performance Evaluation of GaN Based Thin Film Transistor using TCAD Simulation Yayah Zakaria
As reported in past decades, gallium nitride as one of the most capable compound semiconductor, GaN-based high-electron mobility transistors are the focus of intense research activities in the area of high power, high-speed, and high-temperature transistors. In this paper we present a design and simulation of the GaN based thin film transistor using sentaurus TCAD for
the extracting the electrical performance. The resulting GaN TFTs exhibits good electrical performance in the simulated results, including, a threshold voltage of 12-15 V, an on/off current ratio of 6.5×10 7 ~ 8.3×10 and a subthreshold slope
of 0.44V/dec. Sentaurus TCAD simulations is the tool which
offers study of comprehensive behavior of semiconductor structures with ease. The simulation results of the TFT structure based on gallium nitride active channel have great prospective in the next-generation flat-panel display applications.
LINEARITY AND ANALOG PERFORMANCE ANALYSIS OF DOUBLE GATE TUNNEL FET: EFFECT O...VLSICS Design
The linearity and analog performance of a Silicon Double Gate Tunnel Field Effect Transistor (DG-TFET) is investigated and the impact of elevated temperature on the device performance degradation has been studied. The impact on the device performance due to the rise in temperature and a gate stack (GS) architecture has also been investigated for the case of Silicon DG-MOSFET and a comparison with DGTFET is made. The parameters overning the analog performance and linearity have been studied, and high frequency simulations are carried out to determine the cut-off frequency of the device and its temperature dependence.
This presentation is for beginners of electronics. This will give you a brief about all the important basic building blocks of electronics and hence will be helpful in creating a good foundation.
Design of up converter at 2.4GHz using Analog VLSI with 22nm Technologyijsrd.com
Up converter has been designed in 0.18μm technology at 2.4GHz Frequency. I am trying to design up converter with 22nm technology. The problems related to Up converter is often difficult to solve, and may allow different solutions, so the choice is not always simple for those engineers and professionals who are not trained in Analog VLSI. The optimal solution of Problem of Power dissipation is usually a mix of solutions for a specific situation. In such a situation, it is necessary to identify that problem and propose different solutions. Initially the thesis gives a basic idea of up converter and also about CMOS. Later on it tries to simulate the basic gates. And a detailed insight is provided with the help of a simulation using Tspice Simulator. Power Dissipation in 0.18μm Technology using current mirror gilbert mixer is 4.5 mW and in 0.25μm Technology using current mirror gilbert mixer is 3.5mW and Power Dissipation in 0.18μm Technology is 8.1mW using Gilbert mixer. Now I am trying to design mixer with low power dissipation with 22nm technology which is recent technology.
Analysis of analog and RF behaviors in junctionless double gate vertical MOSFETjournalBEEI
The prime obstacle in continuing the transistor’s scaling is to maintain ultra-shallow source/drain (S/D) junctions with high doping concentration gradient, which definitely demands an advanced and complicated S/D and channel engineering. Junctionless transistor configuration has been found to be an alternative device structure in which the junction and doping gradients could be totally eliminated, thus simplifying the fabrication process. In this paper, a process simulation has been performed to study the impact of junctionless configuration on the analog and RF behaviors of double-gate vertical MOSFET. The result proves that the performance of n-channel junctionless double-gate vertical MOSFET (n-JLDGVM) is slightly better than the junction double-gate vertical MOSFET (n-JDGVM). Junctionless device exhibits better analog behaviors as the transconductance (gm) is increased by approximately 4%. In term of RF behaviors, the junctionless device exhibits 3.4% and 7% higher cut-off frequency (fT) and gain band-width product (GBW) respectively over the junction device.
Dual Metal Gate and Conventional MOSFET at Sub nm for Analog ApplicationVLSICS Design
The use of nanometer CMOS technologies (below 90nm) however brings along significant challenges for circuit design (both analog and digital). By reducing the dimensions of transistors many physical phenomenon like gate leakage, drain induced barrier lowering and many more effects comes into picture. Reducing the feature size in the technology of device with the addition of ever more interconnect layers, the density of the digital as well as analog circuit will increase while intrinsic gate switching delay is reduced . We have simulated conventional and DMG MOSFET at 30nm scale using Silvaco TAD tool and obtained result. A two dimensional device simulation was carried out and observed that DMG MOSFET has a low leakage current as compared to conventional MOSFET and find suitable application in analog circuits.
Overview of the fundamental roles in Hydropower generation and the components involved in wider Electrical Engineering.
This paper presents the design and construction of hydroelectric dams from the hydrologist’s survey of the valley before construction, all aspects and involved disciplines, fluid dynamics, structural engineering, generation and mains frequency regulation to the very transmission of power through the network in the United Kingdom.
Author: Robbie Edward Sayers
Collaborators and co editors: Charlie Sims and Connor Healey.
(C) 2024 Robbie E. Sayers
Welcome to WIPAC Monthly the magazine brought to you by the LinkedIn Group Water Industry Process Automation & Control.
In this month's edition, along with this month's industry news to celebrate the 13 years since the group was created we have articles including
A case study of the used of Advanced Process Control at the Wastewater Treatment works at Lleida in Spain
A look back on an article on smart wastewater networks in order to see how the industry has measured up in the interim around the adoption of Digital Transformation in the Water Industry.
Saudi Arabia stands as a titan in the global energy landscape, renowned for its abundant oil and gas resources. It's the largest exporter of petroleum and holds some of the world's most significant reserves. Let's delve into the top 10 oil and gas projects shaping Saudi Arabia's energy future in 2024.
Hierarchical Digital Twin of a Naval Power SystemKerry Sado
A hierarchical digital twin of a Naval DC power system has been developed and experimentally verified. Similar to other state-of-the-art digital twins, this technology creates a digital replica of the physical system executed in real-time or faster, which can modify hardware controls. However, its advantage stems from distributing computational efforts by utilizing a hierarchical structure composed of lower-level digital twin blocks and a higher-level system digital twin. Each digital twin block is associated with a physical subsystem of the hardware and communicates with a singular system digital twin, which creates a system-level response. By extracting information from each level of the hierarchy, power system controls of the hardware were reconfigured autonomously. This hierarchical digital twin development offers several advantages over other digital twins, particularly in the field of naval power systems. The hierarchical structure allows for greater computational efficiency and scalability while the ability to autonomously reconfigure hardware controls offers increased flexibility and responsiveness. The hierarchical decomposition and models utilized were well aligned with the physical twin, as indicated by the maximum deviations between the developed digital twin hierarchy and the hardware.
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Explore the innovative world of trenchless pipe repair with our comprehensive guide, "The Benefits and Techniques of Trenchless Pipe Repair." This document delves into the modern methods of repairing underground pipes without the need for extensive excavation, highlighting the numerous advantages and the latest techniques used in the industry.
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About
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Technical Specifications
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
Key Features
Indigenized remote control interface card suitable for MAFI system CCR equipment. Compatible for IDM8000 CCR. Backplane mounted serial and TCP/Ethernet communication module for CCR remote access. IDM 8000 CCR remote control on serial and TCP protocol.
• Remote control: Parallel or serial interface
• Compatible with MAFI CCR system
• Copatiable with IDM8000 CCR
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
Application
• Remote control: Parallel or serial interface.
• Compatible with MAFI CCR system.
• Compatible with IDM8000 CCR.
• Compatible with Backplane mount serial communication.
• Compatible with commercial and Defence aviation CCR system.
• Remote control system for accessing CCR and allied system over serial or TCP.
• Indigenized local Support/presence in India.
• Easy in configuration using DIP switches.
Runway Orientation Based on the Wind Rose Diagram.pptx
THRESHOLD VOLTAGE CONTROL SCHEMES IN FINFETS
1. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.2, April 2012
DOI : 10.5121/vlsic.2012.3215 175
THRESHOLD VOLTAGE CONTROL SCHEMES
IN FINFETS
V. Narendar1
, Ramanuj Mishra2
, Sanjeev Rai3
, Nayana R4
and R. A. Mishra5
Department of Electronics & Communication Engineering, MNNIT-Allahabad
Allahabad-211004, (U.P)-India
1
narendar.vadthiya@gmail.com
2
ramanujmishra1@gmail.com
3
srai@mnnit.ac.in
4
nayana.r.r@gmail.com
5
ramishra@mnnit.ac.in
ABSTRACT
Conventionally polysilicon is used in MOSFETs for gate material. Doping of polysilicon and thus changing
the workfunction is carried out to change the threshold voltage. Additionally polysilicon is not favourable
as gate material for smaller dimensional devices because of its high thermal budget process and
degradation due to the depletion of the doped polysilicon, thus metal gate is preferred over polysilicon.
Control of workfunction in metal gate is a challenging task. The use of metal alloys as gate materials for
variable gate workfunction has been already reported in literature. In this work various threshold voltage
techniques has been analyzed and a novel aligned dual metal gate technique is proposed for threshold
voltage control in FinFETs.
KEYWORDS
Dual-Metal gate (DMG), FinFET, Gate Workfunction, Independent-Gate (IG), Short channel Effects
(SCEs), Threshold voltage (VT).
1. INTRODUCTION
CMOS technology dimensions have been continuously scaling, that it has reached its
fundamental limits such as carrier mobility degradation because of impurity, severe gate
tunneling effect with decreasing oxide thickness, high p-n junction leakage current as the junction
becoming shallower [1]. FinFET [2] is an innovative MOS device structure which gives superior
performance because they are less effected by short channel effects (SCEs) [3] can be built using
standard bulk planar CMOS processing, can be practically analyzed for analog as well as digital
applications and considered to be the best candidates for sub-65 nm scaling of MOSFETs.
2. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.2, April 2012
176
As variation of threshold voltage is very vital in digital as well as analog applications such as
MT-CMOS, DOMINO logics, SRAMs [15], in this paper we are trying to analyze and compare
various threshold voltage control schemes for FinFET. In this work 32nm FinFET is designed by
Sentaurus structure editor [4] of Sentaurus TCAD. The simulations were performed by using
Sentaurus device simulator [5] of Sentaurus TCAD.
Since the size of transistor in IC is continuously scaling, it is worthwhile to consider the
challenges that CMOS industry is facing and to discuss how to address them. Switching power
(power required to switch a transistor on or off) is equal to 0.5*Cg*VDD2 [6] where Cg is gate
capacitance and VDD is power supply voltage. CMOS scaling has traditionally involved
reduction of both the gate length LG (which proportionally reduces CG) and VDD. As VDD is
reduced for the same off-state current IOFF (and therefore the same threshold voltage VT), the
on-state current ION drops due to reduced gate overdrive (VGS – VT) .So for better on state
current, the value of Vt also decreases with VDD but at the same time low Vt increases the on
state current and hence the static power dissipation. Either way, VDD scaling is necessary in
order to reduce power density on an IC, since increased power density leads to heat which
reduces device performance (due to reduced mobility) and further increases standby power
consumption (due to increased thermal leakage). Thus, to the device designer, the present and
future goal of CMOS scaling is to keep ION as high as possible while scaling VDD. The FinFETs
suffers from short channel effects in the sub 50 nm regime due to reduction in threshold voltage
because of Vt-Rolloff. For high speed switching operation, threshold voltage should be low at the
same time low threshold voltage results in high on state current but for low threshold voltage
IOFF is high. So the lower limit of the threshold voltage is set by the amount of off-state leakage
current. In order to meet the tradeoff between speed and I off and considering the power supply
constraints the VT is set accordingly. On state and off state currents of MOSFET directly depends
on threshold voltage. For higher threshold voltage on state current will be lower and at the same
time the off state current is lower for higher threshold voltage. Ratio of Ion and Ioff is known as
figure of merit for MOSFETs. Higher value of ION/ IOFF is desirable. High on state current
results in higher current drive. Lower off state current results in low static power dissipation.
Threshold voltage of NMOS directly depends on workfunction difference between the gate and
the channel. This difference is called gate barrier. Variation in gate barrier has very dominant
effect in threshold voltage of MOSFET. In this work different characteristic along with threshold
voltage is measured.
In this work we have analyzed independent gate FinFET [6] for threshold voltage variations.
Threshold voltage of MOSFET depends on depletion region charge. The idea is to vary this
charge by applying constant DC bias on one gate and using second gate as input terminal. By
applying different gate bias DC voltage on this gate we can vary the depletion region charge of
MOSFET and a significant variation in overall threshold voltage is achieved. If we tie both gate
of IG-FinFET [13] we will have a connected gate DG-FinFET. Characteristics of DG-FinFET
under different gate barrier are also done. Simultaneously different parameters of both
configurations also extracted.
Another method of channel under/over lapping is also proposed for threshold voltage variation.
We used gate length of 32nm in this work. Threshold voltage of FinFET depends on channel
length and relative position of channel with respect to gate (gate contact). Threshold voltage
analysis along with other parameter is done. As we increase channel under lap towards drain
3. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.2, April 2012
177
/source region threshold voltage increases. Using different channel overlapping desired threshold
voltage can be achieved.
For threshold voltage optimization, variation of gate barrier in TG-FinFET is a superior method
than IG-FinFET mode of operations. So a novel aligned dual metal gate FinFET structured is
proposed. Molybdenum and tungsten are metal with different gate workfunctions. Metals are
aligned as shown in Figure 4 .Metals alloy for threshold voltage control [7], [8] is reported in
previous works. By changing the content of individual metal in alloy different workfunctions can
be obtained. Here instead of making alloy we applied separate gates of tungsten and molybdenum
along the channel. Tungsten has lower work function that molybdenum. We made TG-FinFET
using molybdenum as gate contact metal and measured its characteristics. Again we repeat the
experiment using tungsten as gate contact metal. Threshold voltage of tungsten gate (VT-TN)
FinFET is found to be lower than threshold voltage (VT-MO) of molybdenum gate FinFET. By
using both metals simultaneously as gate contact of FinFET we can achieve the threshold voltage
with in VT-TN and VT-MO. Effective gate length of FinFET is 32nm out of which X nm is
molybdenum gate length and (32-X) nm is Tungsten gate length. This whole device is acting as
two FinFET connected in series. One FinFET is Molybdenum gate and other one is tungsten gate
FinFET. Threshold voltage of molybdenum gate FinFET is higher than tungsten gate FinFET.
Overall threshold voltage lies between these threshold voltages. We can achieve different value of
threshold voltage by varying value of ‘X’. Threshold voltage for different values of X is
calculated and other standard parameters like ION, IOFF, DIBL and subthreshold threshold slope are
also extracted.
2. DEVICE STRUCTURES AND SIMULATION SETUP
Figure 1 shows the 2-D schematic top view of FinFET. Figure 5 shows the 3-D view of SOI-
FinFET device. Device dimensions are shown in Table 1. In this work we have performed
simulation on different devices designed by Sentaurus structure editor .All simulation has been
performed on 3-D FinFET structures. Before simulation TCAD tool is properly calibrated.
Calibration of tool is very vital for FinFET simulations as current flow in actual FinFETs will be
dominated by {1 1 0} plane. Sufficient mesh refinements were applied to the fin region and the
inversion layer regions to capture the inversion layer quantization.
For triple gate MOSFET simple structure is considered which is shown in Figure 1. All gates are
electrically connected in TG-FinFET and all side of gates contributing effectively in current flow.
Transfer characteristics of this device are studied for different metal gate work functions. Since
threshold voltage of devices depends on gate barrier we have gotten different threshold voltages
for different gate barriers. Simultaneously other important parameters subthreshold slope, DIBL,
on state current and off state currents also measured.
4. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.2, April 2012
178
Figure 1. Top view of DG/TG FinFET all gates are electrically connected
In second part of this work N-type independent gate FinFETs (IG-FinFETs) have been designed
and characterized. Here IG-FinFET [10] is a double gate FinFET in which a first gate is used as
input terminal and second gate is for controlling the threshold voltage of device. Using one gate
to adjust threshold voltage allows device designers to utilize intrinsic device bodies, avoiding the
random dopant fluctuation scaling limit [9].Variation in threshold voltage with back gate (second
gate) bias is examined simultaneously other vital parameters are also extracted. Device diagram
and schematic top view is shown in Figure 2. DG-FinFET with connected gate is also studied.
Figure 2 Top view of IG-FinFET
Analysis of threshold voltage under different channel lapping is studied. Top view of channel
lapping is shown in Figure 3. Here ∆Lg is channel extension towards source/drain. This extension
is symmetric so effective channel length is Lg+2∆Lg. extension of drain and source into channel
referred as channel underlap and extension of channel towards drain/source is called channel
overlap. Value of ∆Lg is positive for channel overlap and negative for channel under lap.
5. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.2, April 2012
179
Figure 3 Top view of extended channel FinFET
In final part of this work a novel dual metal gate FinFET is designed and characterized. We
propose a new aligned metal-gate CMOS technology that uses a combination of two metals to
vary threshold voltages for both n- and p-MOSFET‟s. Molybdenum is used as first gate metal
and tungsten is used as second gate metal. For different length of individual metal over gate oxide
different threshold voltage has been reported ,simultaneously different characteristics such as on
state current, off state current, SS, DIBL are also measured. Figure 4 shows top schematic view of
dual metal gate FinFET. Effective gate length is 32nm. Along the length of gate (X) nm
molybdenum is deposited and in remaining (32-X) nm length tungsten is deposited. Device has
design and studied for different value of ‘X’.
Figure 4 Top view of Dual Metal Gate FinFET
6. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.2, April 2012
180
Table 1. Device specifications
Figure 5 3-D views of SOI FinFET and Dual Metal Gate FinFET
7. International Journal of VLSI design & Communication Systems (VLSICS) Vol.3, No.2, April 2012
181
3. DEVICE SIMULATION AND RESULTS
3.1. Tri gate FinFET
The device diagram of tri-gate FinFET has been shown in Figure 5, transfer characteristics of
FinFET has been shown in Figure 6 and subthreshold characteristics of FinFET has also been
shown in Figure 8.The threshold voltage variation has been shown in Figure 7 for different values
of gate barrier. The threshold voltage of an n-channel MOSFET is classically given [11] by
Where ϕms is the workfunction difference between the gate and the silicon and called it as gate
barrier. The Barrier specification in the gate definition defines the workfunction difference
between the metal and an intrinsic reference semiconductor. Relation between gate barrier and
ϕms is given by following equations [11], [12]
Above equations clearly indicate the dependence of threshold voltage on gate barrier. For higher
threshold voltage the value of barrier should be high. A wide range of threshold voltage can be
achieved by varying gate barrier. The threshold voltage of device is found to be higher for high
barrier. Table 2 contains values of threshold voltages and subthreshold slope for different gate
barrier voltages.
Table 2.
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Figure 6 Transfer characteristics of TG-FinFET
Figure 7 variation of threshold voltage in TG-FinFET with gate barrier
Figure 8 Subthreshold characteristics of TG-FinFET for different gate barriers
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3.2. IG-FinFET
IG-FinFET structure is shown in Figure 2. Simulation of IG-FinFET has been done for various
back gate voltages. Table 3 shows the value of threshold voltages and subthreshold slopes for
different back gate voltages. Figure 9 shows transfer characteristics of IG-FinFET for different
back gate voltages and Figure 11 shows transfer characteristics of IG-FinFET.
Table 3
Figure 9 Id-Vg1 curve of IG-FinFET for different back gate voltages
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Figure 10 variation in Vt in IG-FinFET w.r.t. Back gate bias (Vg2)
Figure 11 Subthreshold characteristics of IG-FinFET
3.3. IG-FinFET with connected gate (DG-FinFET)
If both gates of IG-FinFET are electrically connected it will work as dual gate FinFET. Table 4
shows the performance of IG-FinFET in connected gate mode of operation. Both gates are
considered identical.
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Table 4
Figure 12 and 13 shows comparison between FinFET‟s IG, DG and TG mode of operations. It is
found that performance of TG-FinFET is better than IG and DG mode of operation. This is
because TG-mode provides better control of gate over the channel.
Figure 12 comparisons of transfer characteristic of IG, DG & TG FinFETs
While comparing IG, TG and DG mode, gate barriers is considered to be zero. In IG-FinFET
back voltage is zero. It is apparent from Figure 13 that subthreshold performance of TG-FinFET
and DG-FinFET is much better than IG-FinFET.
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Fig 13 comparisons of subthreshold characteristic of IG, DG & TG FinFETs
Figure 14 Id-Vg plots for different values of ∆Lg
3.4. Extended channel
Channel lapping stands for extension of channel towards drain and source regions. Channel
lapping is represented by parameter ∆Lg. Here ∆Lg shows how much channel is extended
towards drain/source. Negative value of ∆Lg shows negative channel lapping means extension of
drain and source in channel table 5 shows device performance for different value of ∆Lg.
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Figure 15- variation in threshold voltage with respect to ∆Lg
Figure 16 Subthreshold characteristics of FinFET for different value of ∆Lg
Table 5
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3.4. Dual-Metal gate FinFET
Schematic top view of dual metal gate (DMG) FinFET is shown in fig4. A transfer characteristic
of DMG FinFET is shown in Figure 14.
Figure 17 Id-Vg curve of DMG FinFET
Here X is the length of molybdenum gate and 32-X is length of tungsten gate. 32nm is total gate
length. Graph clearly indicates that we can vary threshold voltage of FinFET by changing “X”.
Figure 18 Subthreshold characteristics of DMG FinFET
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Table 6
4. CONCLUSION & DISCUSSION
IG-FinFET provides a simple way for variable threshold voltage. It is also possible in IG-FinFET
to vary the threshold voltage during the operation, by applying DC bias we got a good range of
threshold voltages. Single IG-FinFET can also used as two parallel transistor hence with IG-mode
of operation we may have a wide range of threshold voltage as well as significant area efficiency.
But there are some drawbacks while using FinFET in IG configurations. While using back gate
for threshold voltage control there is only one active gate in IG-FinFET. IG-FinFET shows very
low subthreshold performance and very low on current. Figure 12 shows the comparison of IG-
FinFET and TG FinFET transfer characteristics, and it clearly indicates that the value of on
current of IG-FinFET is lower as compare to TG mode of operation .From Figure 13 we can
conclude that IG-FinFET has less control of gate over channel than TG FinFET and DG-FinFET.
Our goal is to vary threshold voltage of FinFET without varying its other characteristics like
subthreshold slope, DIBL etc. Channel lapping technique discussed here has provided a wide
range of threshold voltage without effecting its SS and DIBL. But effective length of channel is
changed and due to high lapping capacitance it is not a good technique.
It is apparent in this work that best way of controlling threshold voltage of FinFET is by changing
its gate‟s workfunction. For long channel MOSFETs polysilicon is used as gate materials. It is
very easy to change workfunction of polysillicon by changing its doping. But for short channel a
metal gate electrode has several advantages compared to the doped polysilicon [14] gate used
almost exclusively today. Gate capacitance degradation due to the depletion of the doped
polysilicon gate typically accounts for 0.4 – 0.5 nm of the equivalent-oxide thickness of the total
gate capacitance at inversion. This is a substantial amount, considering that a gate equivalent
oxide of less than 1.5 nm. High k dielectrics are thermally unstable. Fabrication of MOSFET with
high k dielectric required low thermal budget process. Polysilicon gate required high temperature
processing so it cannot be used when high k dielectrics are used as gate insulator. Moreover the
workfunction variation of polysilicon gate technology is limited to values close to the conduction
band and the valence band of silicon. The use of a metal gate material opens up the opportunity to
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choose the work function of the gate and redesign the device to achieve the best combination of
work function and channel doping.
In this work we aligned different metals for formation of gate contact. Results are shown in
Figure 17-18. It is found that this alignment of metals not only provides a good range of threshold
voltages but gives better performance also. Values of subthreshold slope and DIBL are nearly
identical in all combinations. Different threshold voltage schemes are systematically investigated
using extensive device simulations with optimized TCAD tools. This paper shows that after
careful optimization FinFETs offer a desirable threshold voltage and use of FinFET in multiple
threshold voltage circuits will offer future low-power high-performance applications.
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Authors
V. Narendar - Received the B.Tech. degree in Electronics and Communication from SVEC-Suryapet-A.P.,
India, in 2006 and the M.Tech. degree in microelectronics and VLSI design in 2010 from the MNNNIT
Allahabad, India, where he is working as an assistant professor in SMDP-II Project and currently working
toward Ph.D. degree in Electronics and communication Engg, with “Device Modeling and VLSI Circuits”
as the area of specialization.
Ramanuj Mishra- received the B.E. Degree in Electronics and Communication from RGPV in 2009
Bhopal, India. And currently working towards M.Tech in microelectronics and VLSI design from
MNNNIT Allahabad, Allahabad, His current research interests include of Short channel devices such as
FinFETs
Nayana R- she is working towards M. Tech Degree in microelectronics and VLSI design from MNNIT
Allahabad, Allahabad, and Her area of interest is low power CMOS design.
Sanjeev Rai- He is an assistant Professor in MNNIT Allahabad. His areas of interest are Microelectronics
& VLSI Design, Modeling of Semiconductor Devices, and VLSI Circuits & Systems
Dr. R. A. Mishra : He is an assistant Prof. in MNNIT Allahabad. His areas of research are VLSI Circuits,
Modeling of Semiconductor, Devices RNS based Circuits Design