This document discusses field effect transistors (FETs) and provides details about junction FETs (JFETs). It describes the basic structure and operation of N-channel and P-channel JFETs. Key points covered include: - FETs are voltage-controlled, unipolar devices that come in two main types: JFETs and MOSFETs. - A JFET has two P-type regions diffused into an N-type (N-channel JFET) or two N-type regions into a P-type (P-channel JFET) material to form a channel. Applying a voltage to the gate controls the channel. - The characteristics of a

3. GROUP 001
Department of CS & IT. BSCS-I
 Dawood Faheem Abbasi 005
 Umar Ali 014
 Zohaib Maqbool 051

4. FET’s
FIELD EFFECT TRANSISTOR

5. CONTENT LIST
• FET’s
• Types of FET’s
• JFET
• MOSFET
• Characteristics of JFET and its parameter

6. FET’s(Field Effect Transistor)
• These are major types of transistor. Field effect transistor (FET’s) are
unipolar devices because they operate only with the one type of charge
carriers.
• FET is a voltage control device.

8. Kinds Of FET’s
• Two main kinds:
• Junction Field Effect Transistor.(JFET)
• Metal Oxide Semi-conductor Field Effect Transistor.(MOSFET).

9. JFET(Junction Field Effect Transistor)
• Two kinds:
• N-channel JFET
• P-channel JFET

10. N-channel JFET JFET
• A wire lead is connected to each end of the n channel.
• DRAIN is at upper end and SOURCE is at lower end.
• Two p-type regions are diffused in the n-type material to form a channel.
• P-type regions are connected to GATE leads.

11. P-channel JFET
• A wire lead is connected to each end of the p channel.
• DRAIN is at upper end and SOURCE is at lower end.
• Two n-type regions are diffused in the p-type material to form a channel.
• N-type regions are connected to GATE leads.

12. OPERATION
• DC biased voltage is applied to the n channel.
• VDD provides a drain to source voltage and supplies current DRAIN to
SOURCE.
• VGG sets the reverse bias voltage between GATE and SOURCE.

14. • In JFETS the gate source to p-n junction is always reversed biased.
• This produces depletion region along the p-n junction which entered into the
n-channel and thus increases its resistance by rusticating channel width.
• Channel width and channel resistance can be controlled by varying gate
voltage.
• Drain current ID is also controlled.

15. Greater VGG narrows the
channel which increases the
resistance of the channel
and decreases the ID.

16. Less the VGG increases the
channel which decreases the
resistance of the channel
and increases ID.

17. Skim etic symbols

18. JFET CHARACTERISTIC AND PARAMETER
• We consider when the case when the gate to source voltage is
zero. (VGS = 0 )
• This is produce by shorting the gate to source has shown in fig(a).

19. Fig (a)

20.  When both are grounded, as VDD increase from ‘0’ volt. ID Increase proportionally
between point A & B, as shown in fig A.(when VDD increase VDS also increase)
between A & B.
 The channel resistance is essentially constant because the depletion region is not large
enough to have a significant effect . In this area ohm law hold (V∞I). So this region is
called ohmic region.

21.  At point B in fig(A) the current level is off and ID be essentially constant ,has VDS
increase from point B to C. The reverse biased voltage from gate to drain VGD produce
depletion region large enough so the current ID constant for (VGS=0) the value of VDS
for which ID extentioly constant is called pinch of voltage…
 We grow on increasing VDS there is no change in drain current. This constant value of
drain current ID is called IDSS(saturation of drain current) .

22. We see break down occurs when ID current very rapidly with any further
increase VDS.
This region is called break down region.

23. PINCH OFF VOLTAGE:
• For VGS=0 the value of VDS for which ID essentially become
constant is called as pinch off voltage (VP ). From fig we see above pinch
off voltage VP as we go on increase VDS. There is no change in drain current
the constant value of drain current is called IDDS (drain to source current
)with gate shorted.
• We see break down occur at point C, when ID become to increase very
rapidly with any further increase in VDS ,breakdown can damage the
transistor. So, JFET must be operated between below breakdown and within
constant current area.