Tesla UBQ01B0 FSD Chip

©2021 by SystemPlus Consulting | SPR21639- Tesla UBQ01B0 FSD Chip 1
22 bd Benoni Goullin
44200 NANTES - FRANCE +33 2 40 18 09 16 info@systemplus.fr www.systemplus.fr
Tesla UBQ01B0 FSD Chip
First self-made SoC for advanced driving in Tesla Driver
Assist Autopilot 3.0
SPR21639 - Computing & Software report by Ying-Wu Liu
Physical analysis by Peggy Gallois
November 2021 – Sample
REVERSE COSTING® – STRUCTURAL, PROCESS& COST REPORT

Table of Contents
Overview / Introduction 4
o Executive Summary
o Reverse Costing Methodology
o Block Diagram
Physical Analysis 13
o Summary of the Physical Analysis
o Packaging
 Package Overviews, Dimensions
 Package Cross-section
o Die
 Die View & Dimensions
 Die Delayering & Main Blocks ID
 Die Process
 Die Cross-Section
 Die Process Characteristic
Manufacturing Process 37
o Die Front-End Process & Fabrication Unit
o Back-End Process & Fabrication Unit
o Summary of Inputs
Cost Analysis 45
o Summary of the cost analysis
o Yields Explanation & Hypotheses
o Die
 Die Front-End Cost
 Die Probe Test & Dicing
 Wafer & Die Cost
o Packaged Component
 Packaging Cost
 Back End: Final Test
 Component Cost
Estimated Selling Price 55
Feedbacks 58
Company services 60

Overview / Introduction
o Executive Summary
o Reverse Costing
Methodology
o Block Diagram
o Confidence Index
Physical Analysis
Manufacturing Process Flow
Cost Analysis
Selling Price Analysis
Feedbacks
About System Plus Consulting
Electronic Board in Tesla Model 3 Driver Assist Autopilot 3.0
Tesla
UBQ01B0
GPU Full Self Driving
Chip 3 Quad-core
Cortex-A72 2.2GHz
GPU 1GHz 2xNPU
2GHz LPDDR4 128b,
FCBGA2116 (Qty : 2)
Electronic Board in Tesla Model 3 Driver Assist Autopilot 3.0
©2021 by SystemPlusConsulting

o Executive Summary
o Reverse Costing
Methodology
o Block Diagram
o Confidence Index
Physical Analysis
Cost Analysis
Feedbacks
Functional Block Diagram
Source: Tesla Autonomy Day streamedlive on Apr 22, 2019.
o Screenshots from Tesla Autonomy Day streamed live on Apr 22, 2019.

Physical Analysis
o Synthesis
o Package
o Die
o Die Cross Section
Cost Analysis
Feedbacks
Package Views & Dimensions
Package Front View
xxx mm
xxx
mm
xxx mm
• Package: FC BGA 2116-balls
• Dimensions: xxx x xxxx xxx mm
• Pin Pitch: xxx mm
Package Back View
Package Side View

Physical Analysis
o Synthesis
o Package
o Die
o Die Cross Section
Cost Analysis
Feedbacks
Package X-Ray
Package X-Ray

Physical Analysis
o Synthesis
o Package
o Die
o Die Cross Section
Cost Analysis
Feedbacks
Die Overview & Dimensions
IC Die - Overview

Physical Analysis
o Synthesis
o Package
o Die
o Die Cross Section
Cost Analysis
Feedbacks
Die Delayering
IC Die View after removing of the metal layers - Optical View

Physical Analysis
o Synthesis
o Package
o Die
o Die Cross Section
Cost Analysis
Feedbacks
Die Overview
Die Process – SEM View
©2021 by SystemPlus Consulting
Die Process – SEM View
©2021 by SystemPlus Consulting
Die Process

Physical Analysis
o Synthesis
o Package
o Die
o Die Cross Section
Cost Analysis
Feedbacks
Die Cross-Section – Metal Layers

Physical Analysis
o Global Overview
o Wafer Fabrication Unit
o Front-End Process
o Back-End
o Packaging Process
o Final Test
Cost Analysis
Feedbacks
IC Front-End Wafer Fabrication Unit
• We assume that the circuit is manufactured by xxxx in xxxx.
• We assume that the manufacturing of the dies are made on xxxxmm wafers.
• Wafer fab unit:
o Name: xxxxx
o Wafer diameter: xxx mm
o Capacity: xxxx wafers / month
o Year of start: 2011
o Most advanced process: CMOS xxxxx µm
o Location: xxxxxx

Physical Analysis
o Global Overview
o Wafer Fabrication Unit
o Front-End Process
o Back-End
o Packaging Process
o Final Test
Cost Analysis
Feedbacks
Back End Final Test
• After the dicing and packaging steps, the component is tested during the final test.
– System Plus Consulting estimates that the final tests are outsourced in xxxx.
– Equipment test is supposed to be a “High Performance Processor” ($xxxx), with 1 component under test at one time.
– The test time is estimated to xxxxxseconds (at2 temperatures). 100% of the circuits are tested during the final test.
– The final test yield is estimated to xxxxx%.

Physical Analysis
Cost Analysis
o Cost AnalysisSummary
o Yields Explanation &
Hypotheses
o Front-End Cost
o Back End Cost
o Wafer& Die Cost
o Packaging Cost
o Component Cost
Feedbacks
Yields Explanation
• The wafers and dies are tested during the process flow. There are 2 types of test :
• The tests on the physical characteristics of the wafer like the thickness of a deposited layer.
• The tests on the electrical functionalities of the die.
• The difference is important because with the physical test, a poor result means a problem on a step and all the dies
on the wafer are defective, so the wafer is scrapped. Usually these yields are good for mature technologies.
• The tests on the dies are different. Each die is tested, one by one or simultaneously using “parallel” tests, and only the
defective dies are scraped. During the probe test which is realized on the wafer, the defective dies are marked and are
not assembled in package.
• In this reverse costing study, 6 yields are used :
Process Yield Apply on Description
Front-End Manufacturing Yield IC Die The defective wafers are scraped
Back-End 0 Probe yield IC Die
The defective dies are scraped.
The number of good dies is function of the
probe yield. Only the good dies are assembled
in the package.
Back-End 0 Testing & Dicing Yields IC Die The defective dies are scraped
Back-End 1 Assemby & Test yields Complete Component The defective components are scraped

Physical Analysis
Cost Analysis
Hypotheses
o Front-End Cost
o Back End Cost
o Wafer& Die Cost
o Packaging Cost
o Component Cost
Feedbacks
IC Die Cost
The die costis estimated between $xxx and xxx.
Silicon cost accounts for xxx% .
The probe test, bumping, backgrinding and dicing represent xxxx% of the
cost.

Physical Analysis
Cost Analysis
Hypotheses
o Front-End Cost
o Back End Cost
o Wafer& Die Cost
o Packaging Cost
o Component Cost
Feedbacks
Component Cost
The component cost is estimated between $xxxand $xxx.
The IC Die costaccounts for xxx%.
The packaging represents xxx%of the total component cost.
The capacitors represent x% of the total component cost.
Final Test and yield losses represent xxx%of the total component cost .

R E L A T E D
A N A L Y S E S

Physical Analysis
Cost Analysis
Feedback
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COMPANY
SERVICES

Physical Analysis
Cost Analysis
Feedback
Related Analyses
o Company services
o Contact
A Structure,Process andCostAnalysis
Reverse Costing® consists of disassembling a device or a system in order
to identify its technology and discern its manufacturing processes and
then using in-house models and tools to determine its cost.
Our Core Activity: Reverse Costing®

Physical Analysis
Cost Analysis
Feedback
Related Analyses
o Company services
o Contact
Fields Of Expertise

Physical Analysis
Cost Analysis
Feedback
Related Analyses
o Company services
o Contact
Business Model
Teardown
Track
205+
teardowns per
year
Monitor
1 per year
quarterly
updated
Custom
Analysis
150 custom
analyses per
year
Report
60+ per year
Costing
Tools
5 process-based
and 3 parametric
costing tools
Cost
Methods
Training
On demand

Physical Analysis
Cost Analysis
Feedback
Related Analyses
o Company services
o Contact
Worldwide Presence
100+ collaborators in 8 different countries
Headquarters
› Nantes – System Plus Consulting
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Physical Analysis
Cost Analysis
Feedback
Related Analyses
o Company services
o Contact
Contact
REPORTS, MONITORS & TRACKS
HEADQUARTER
& CUSTOM PROJECT SERVICES
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sales@systemplus.fr - +33 2 40 18 09 16
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TRACKS WEBSITE
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