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Ajay Gadhe, Ujwal Shirode / International Journal of Engineering Research and Applications
                       (IJERA)         ISSN: 2248-9622   www.ijera.com
                     Vol. 3, Issue 1, January -February 2013, pp.1073-1078
    Read stability and Write ability analysis of different SRAM cell
                              structures
                                   Ajay Gadhe*, Ujwal Shirode**
                   *(Department of Electronics, North Maharashtra University, Jalgaon-425001)
                  ** (Department of Electronics, North Maharashtra University, Jalgaon-425001)


ABSTRACT
         SRAM cell read stability and write-ability        under the required frequency constraint. Therefore, the
is major concerns in nanometer CMOS                        analysis of SRAM read/write margin is essential for
technologies, due to the progressive increase in           low-power SRAMs. In recent years, research on sub-
intra-die variability and VDD scaling. This paper          threshold SRAMs has shown the promise of SRAM
analyzes the read stability and write ability of 6T,       design for energy-efficient and ultra-low-power
8T, 9T SRAM cell structures. SRAM cell stability           applications. The most challenging issue for sub
analysis is typically based on Static Noise Margin         threshold SRAM is increasing reliability during
(SNM) investigation. This paper represents the             read/write. A good metric for read/write margin is
simulation of three SRAM cell topologies and their         critically important to all kinds of SRAM designs.
comparative analysis on the basis of read noise            Moreover, the stability of the SRAM cell is seriously
margin (RNM), write noise margin (WNM). Both               affected by the increase in variability and by the
8T SRAM cell and 9T SRAM cell provides higher              decrease in supply voltage. Furthermore, new SRAM
read noise margin as compared to 6T SRAM cell.             cell circuit designs have been developed to maximize
Although the size of 9T SRAM cell is higher than           the cell stability for future technology nodes.
that of the 8T SRAM cell but it provides higher                In this paper, we will emphasize SRAM read
write stability. In this paper we propose a                margin and write margin analysis and compare the
methodology to characterize the DC noise margin of         different SRAM cells configurations on the basis of
6T, 8T and 9T SRAM. All simulations of the SRAM            the stability analysis. Static noise margins (SNMs) [1]
cell have been carried out in 130nm CMOS                   are widely used as the criteria of stability. SNM is
technology.                                                defined as the minimum DC noise voltage [2] needed
Keywords -Noise margin, read stability, read noise         to flip the cell state, and is used to quantify the
margin (RNM), SRAM cell, Static Noise Margin               stability of a SRAM cell using a static approach.
(SNM), write ability, Write noise margin (WNM).
                                                           2. LITERATURE REVIEW OF DIFFERENT
1. INTRODUCTION                                            SRAM CELLS
         A SRAM cell consist of a latch, therefore the
cell data is kept as long as power is turned on and        2.1 6T SRAM CELL
refresh operation is not required for the SRAM cell.
SRAM is mainly used for the cache memory in
microprocessors, mainframe computers, engineering
workstations and memory in hand held devices due to
high speed and low power consumption. Each bit in an
SRAM is stored on four transistors that form two cross
coupled inverters.
   With increased device variability in nanometer
scale technologies, SRAM becomes increasingly
vulnerable to noise sources. The wider spread of local
mismatch leads to reduced SRAM reliability. For the
demand of minimizing power consumption during
active operation, supply voltage scaling is often used.
However, SRAM reliability is even more suspect at
lower voltages. VCCmin is the minimum supply                         Figure 1: Standard 6T SRAM cell.
voltage for an SRAM array to read and write safely
                                                           The schematic diagram of 6T SRAM cell is shown in
                                                           Fig.1.The conventional 6T SRAM memory cell is
                                                           composed of two cross-coupled CMOS inverters with


                                                                                                 1073 | P a g e
Ajay Gadhe, Ujwal Shirode / International Journal of Engineering Research and Applications
                       (IJERA)         ISSN: 2248-9622   www.ijera.com
                     Vol. 3, Issue 1, January -February 2013, pp.1073-1078
two pass transistors connected to complementary bit-      write operations yields a non destructive read
lines. Fig. 1 shows this well known architecture, where   operation or SNM-free read stability.
the access transistors M5 and M6 are connected to the        An additional leakage current path is introduced by
word-line (WL) to perform the access write and read       the separate read-port which increases the leakage
operations through the column bit-lines (BL and           current as compared to standard 6T bit cell. Therefore,
BLB). Bit-lines act as input/output nodes carrying the    an increased area overhead and leakage power make
data from SRAM cells to a sense amplifier during read     this design rather unattractive, since leakage power is
operation, or from write circuitry to the memory cells    a critical SRAM design metric, particularly for highly
during write operations. All transistors have minimum     energy constrained applications.
length (Lmin), while their widths are typically design
parameters.                                               2.3 9T SRAM CELL
    6T SRAM cell implementation has the advantage
                                                          The schematic of the new 9T SRAM cell is shown in
of low static power dissipation. However, the potential
                                                          Fig.3.Standard 6T bit cell along with three extra
stability problem of 6T SRAM cell as shown in figure
                                                          transistors were employed in nine-transistor (9T)
1 is such that during the read operation, a stored “0”
                                                          SRAM bit cell to bypass read-current from the data
can be overwritten by a “1”when the voltage at node Q
                                                          storage nodes.
reaches the Vth of NMOS M1 to pull node QB down
to “0” and in turn pull node Q up even further to “1”
due to the mechanism of positive feedback.
    To overcome the problem of data storage
destruction during the read operation [3], an 8T-cell
implementation was proposed, for which separate
read/write word signal lines are used as shown in fig
(2) to separate the data retention element and the data
output element.

2.2 8T SRAM CELL




                                                          Figure 3: 9T SRAM cell.

                                                             A novel 9T SRAM cell with enhanced data stability
                                                          and reduced leakage power consumption is presented
                                                          in this section. The upper sub-circuit of the new
                                                          memory cell is essentially a 6T SRAM cell.The two
                                                          write access transistors (M1 and M2) are controlled by
                                                          a write signal (WWL). The data is stored within this
               Figure 2: 8T SRAM cell                     upper memory sub-circuit. The lower sub-circuit of the
                                                          new cell is composed of the bit-line access transistors
A dual-port cell (8T-cell) is created by adding two       (M7 and M8) and the read access transistor (M9). The
data output transistors to 6T-cell, as shown in Fig. 2.   operations of M7 and M8 are controlled by the data
Separation of data retention element and data output      stored in the cell. M9 is controlled by a separate read
element means that there will be no correlation           signal (RWL).
between the read SNM cell and I cell. These separate
read and write ports are controlled by read (RWL) and     3. STATIC NOISE MARGIN (SNM)
write (WWL) word lines and used for accessing the bit
cell during read and write cycles, respectively. In 8T              SNM is the measure of stability of the SRAM
bit cell topology, read and write operations of a         cell to hold its data against noise. SNM of SRAM is
standard 6T SRAM bit cell are de-coupled by creating      defined as minimum amount of noise voltage present
an isolated read-port or read buffer (comprised of two    on the storing nodes of SRAM required to flip the
transistors, M7 and M8). De-coupling of read and          state of cell.


                                                                                               1074 | P a g e
Ajay Gadhe, Ujwal Shirode / International Journal of Engineering Research and Applications
                       (IJERA)         ISSN: 2248-9622   www.ijera.com
                     Vol. 3, Issue 1, January -February 2013, pp.1073-1078
   There are two methods to measure the SNM of                 In Fig. 4(a), the equivalent circuit for the SNM
SRAM cell. First method is a graphical approach in         definition [6] is shown. The two DC noise voltage
which SNM can be obtained by drawing and mirroring         sources are placed in series with the cross-coupled
the inverter characteristics and then finding the          inverters. The minimum value of noise voltage (Vn)
maximum possible square between them. The second           which is necessary to flip the state of the cell is
approach involves the use of noise source voltages at      recorded as SNM.
the nodes as shown in figure 4 (a).                           The graphical method to determine the SNM uses
   SNM Dependences [4] includes cell ratio (CR),           the static voltage transfer characteristics of the SRAM
supply voltage and also pull up ratio .Cell ratio [5] is   cell inverters.
the ratio between sizes of the driver transistor to the
load transistor during the read operation. Pull up ratio
[5] is the ratio between sizes of the load transistor to
the access transistor during write operation.

With reference to figure (1),

               (M1)
               (M5) (During Read Operation)

             (M4)
             (M6) (During Write Operation)

   If the cell ratio increases, size of the driver
transistor also increases, consequently increasing the
current. As current increases, the speed of the SRAM
cell also increases.
                                                           Figure 4: (b) Butterfly curve for the SRAM cell
4. READ STABILITY AND WRITE-                                  Fig.4 (b) superposes the voltage transfer
ABILITY OF THE SRAM CELL                                   characteristic (VTC) of one cell inverter to the inverse
                                                           VTC of the other cell inverter. The resulting two-lobed
4.1 The SRAM cell read stability                           graph is called a "butterfly" curve and is used to
Data retention of the SRAM cell, both in standby           determine the SNM. Its value is defined as the side
mode and during a read access, is an important             length of the largest square that can be fitted inside the
functional constraint in advanced technology nodes.        lobes of the "butterfly" curve.
The cell becomes less stable with lower supply voltage        More the value of SNM, higher is the read stability
increasing leakage currents and increasing variability,    of the SRAM cell. A cell with lower RSNM has
all resulting from technology scaling. The stability is    poorer read stability.
usually defined by the SNM [6] as the maximum value
of DC noise voltage that can be tolerated by the           4.2 Write ability of the SRAM cell
SRAM cell without changing the stored bit.




Figure 4: (a) The standard setup for the SNM
definition.




                                                                                                  1075 | P a g e
Ajay Gadhe, Ujwal Shirode / International Journal of Engineering Research and Applications
                           (IJERA)         ISSN: 2248-9622   www.ijera.com
                         Vol. 3, Issue 1, January -February 2013, pp.1073-1078
                                                                     simulation sweeping the input of the inverters (QB and
                                                                     Q‟).
                                                                        For a successful write, only one cross point should
                                                                     be found on the butterfly curves, indicating that the
                                                                     cell is mono-stable. WSNM for writing „1‟ is the
                                                                     width of the smallest square that can be embedded
                                                                     between the lower-right half of the curves. WSNM for
                                                                     writing „0‟ can be obtained from a similar simulation.
                                                                     The final WSNM for the cell is the minimum of the
                                                                     margin for writing „0‟ and writing „1‟. A cell with
                                                                     lower WSNM has poorer write ability.




   Figure 5: (a) Circuit for WSNM [7] of writing „1‟.                5. SIMULATION AND RESULTS
   Write margin is the measure of the ability to write data
   into the SRAM cell. Write margin voltage is the                   All simulations are done using 130nm CMOS logic
   maximum noise voltage present at bit lines during                 process technology in Hspice environment.
   successful write operation. When noise voltages
   exceeds the write margin voltage, then write failure
   occurs. In this section, we introduce static approach
   for measuring write margin. The most common static                                              Y1=1.10V
   approach uses SNM as a criterion.                                                               Y2=0.66V
                                                                                                   SNM = Y1-Y2
                                                                                                   SNM= 440mV
                                                              V(Q)




                                                                                                                          V(Q)
V(Q)




                                                                                           V(QB)
                                                                     Figure 6: Simulation of HOLD SNM of 6T SRAM cell




                         V(QB)
   Figure 5: (b) WSNM [7] of writing „1‟ is the width of
   the smallest embedded square at the lower-right side

      The cell is set in the write operation. Figure 5(a)
   shows the circuit for writing a „1‟ into the cell. Write
   SNM (WSNM) is measured using butterfly or VTC
   [8] curves (Figure5 b), which are obtained from a dc




                                                                                                         1076 | P a g e
Ajay Gadhe, Ujwal Shirode / International Journal of Engineering Research and Applications
                              (IJERA)         ISSN: 2248-9622   www.ijera.com
                            Vol. 3, Issue 1, January -February 2013, pp.1073-1078

                                Y1=1.12V                                                          Y1=1.10V
                                Y2=0.897V                                                         Y2=0.66V
                                SNM = Y1-Y2                                                       SNM = Y1-Y2
                                SNM= 223mV                                                        SNM= 440mV
V(Q)




                                                     V(Q)
                              V(QB)                                                     V(QB)
       Figure 7: Simulation of RNM of 6T SRAM cell                 Figure 9: Simulation of RNM of 8T SRAM cell




                                                                                                   Y1=1.10V
                                                                                                   Y2=0.66V
                                                                                                   SNM = Y1-Y2
                                                                                                   SNM= 440mV

                                      Y1=0.556V
                                      Y2=0.0825V
                                                            V(Q)




                                      SNM = Y1-Y2
                                      473.5mV




                            V(QB)
       Figure 8: Simulation of WNM of 6T SRAM cell                                        V(QB)

                                                                   Figure 10: Simulation of RNM of 9T SRAM cell




                                                                                                     1077 | P a g e
Ajay Gadhe, Ujwal Shirode / International Journal of Engineering Research and Applications
                              (IJERA)         ISSN: 2248-9622   www.ijera.com
                            Vol. 3, Issue 1, January -February 2013, pp.1073-1078
                                                           ACKNOWLEDGEMENTS
                                                                   We would like to sincerely thank to Dr. D.K. Gautam,
                                                                   head of the department of electronics engineering and
                                                                   technology, North Maharashtra University, Jalgaon
                                                                   who inspired us to do this work. Also we are thankful
                                                                   to the faculty of Department of Electronics
                                                                   engineering for their moral support.
                                           Y1=0.578V
                                           Y2=0.66V
V(Q)




                                           SNM = Y1-Y2             REFERENCES
                                           SNM= 495mV                  [1] Jiajing Wang, Satyanand Nalam, and Benton
                                                                           H. Calhoun, Analyzing Static and Dynamic
                                                                           Write Margin for Nanometer SRAMs,
                                                                           Department of Electrical and Computer
                                                                           Engineering,     University  of  Virginia,
                                                                           Charlottesville, VA 22904, USA.
                                                                       [2] Kanak Agarwal,Sani Nassif .,Statistical
                                                                           Analysis of SRAM Cell Stability, IBM
                                                                           Research, Austin, TX.
                             V(QB)                                     [3] Mo      Maggie       Zhang.,     Performance
                                                                           Comparison of SRAM Cells Implemented in
       Figure 11: Simulation of WNM of 9T SRAM cell                        6, 7 and 8-Transistor Cell Topologies,
                                                                           Electrical and Computer Engineering,
                                                                                    University of California, Davis.
           Table 1: SNM for 6T, 8Tand 9T SRAM cell
                                                                       [4] B. Alorda, G. Torrens, S. Bota and J. Segura.,
                                                                           Static-Noise Margin Analysis during Read
        SRAM           HOLD           READ          WRITE                  Operation of      6T SRAM Cells, Univ. de
        CELL           SNM            SNM            SNM                   les Illes Balears, Dept. Fisica, Cra.
                       (mV)           (mV)           (mV)                           Valldemossa, 07071 Palma de
                                                                           Mallorca, Spain.
           6T           440            223           473.5             [5] Debasis Mukherjee1, Hemanta Kr. Mondal2
           8T           440            440           473.5                 and B.V.R. Reddy3, Static Noise Margin
           9T           440            440            495                  Analysis of SRAM Cell for High Speed
                                                                           Application, IJCSI International Journal of
                                                                           Computer Science Issues, Vol. 7, Issue 5,
       6. CONCLUSION
                                                                           September 2010.
                 The stability performances of three SRAM              [6] Evelyn      Grossar,    Michele       Stucchi,
       cell topologies have been presented. As process                     KarenMaex, Read Stability and Write-Ability
       technologies continue to advance, the speed of                      Analysis of SRAM Cells for Nanometer
       SRAMs will increase, but devices will be more                       Technologies, IEEE JOURNAL OF SOLID-
       susceptible to mismatches, which worsen the static-                 STATE CIRCUITS, VOL. 41, NO. 11,
       noise margin of SRAM cells.                                         NOVEMBER 2006, pp.2577-2588.
           The 6T SRAM provide very less RNM. To obtain                [7] Jiajing Wang, Satyanand Nalam, and Benton
       higher RNM in 6T SRAM cell width of the pull down                   H.Calhoun, Analyzing Static and Dynamic
       transistor has to be increased but this increases area of           Write Margin for Nanometer SRAMs,
       the SRAM which in turn increases the leakage                        Department of Electrical and Computer
       currents.                                                           Engineering, University of Virginia.
          The 8T SRAM cell provide higher read noise                   [8] Andrei S. Pavlov, Design and Test of
       margin. Due to asymmetric cell structure 8T SRAM                    Embedded SRAMs, doctoral diss., University
       cell may prone to failure during write operation. On                of Waterloo, Ontario, Canada, 2005.
       the other hand 9T SRAM cell has higher RNM as well
       as WNM thus showing better stability performance as
       compare to 6T and 8T SRAM cell.




                                                                                                       1078 | P a g e

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Fj3110731078

  • 1. Ajay Gadhe, Ujwal Shirode / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 3, Issue 1, January -February 2013, pp.1073-1078 Read stability and Write ability analysis of different SRAM cell structures Ajay Gadhe*, Ujwal Shirode** *(Department of Electronics, North Maharashtra University, Jalgaon-425001) ** (Department of Electronics, North Maharashtra University, Jalgaon-425001) ABSTRACT SRAM cell read stability and write-ability under the required frequency constraint. Therefore, the is major concerns in nanometer CMOS analysis of SRAM read/write margin is essential for technologies, due to the progressive increase in low-power SRAMs. In recent years, research on sub- intra-die variability and VDD scaling. This paper threshold SRAMs has shown the promise of SRAM analyzes the read stability and write ability of 6T, design for energy-efficient and ultra-low-power 8T, 9T SRAM cell structures. SRAM cell stability applications. The most challenging issue for sub analysis is typically based on Static Noise Margin threshold SRAM is increasing reliability during (SNM) investigation. This paper represents the read/write. A good metric for read/write margin is simulation of three SRAM cell topologies and their critically important to all kinds of SRAM designs. comparative analysis on the basis of read noise Moreover, the stability of the SRAM cell is seriously margin (RNM), write noise margin (WNM). Both affected by the increase in variability and by the 8T SRAM cell and 9T SRAM cell provides higher decrease in supply voltage. Furthermore, new SRAM read noise margin as compared to 6T SRAM cell. cell circuit designs have been developed to maximize Although the size of 9T SRAM cell is higher than the cell stability for future technology nodes. that of the 8T SRAM cell but it provides higher In this paper, we will emphasize SRAM read write stability. In this paper we propose a margin and write margin analysis and compare the methodology to characterize the DC noise margin of different SRAM cells configurations on the basis of 6T, 8T and 9T SRAM. All simulations of the SRAM the stability analysis. Static noise margins (SNMs) [1] cell have been carried out in 130nm CMOS are widely used as the criteria of stability. SNM is technology. defined as the minimum DC noise voltage [2] needed Keywords -Noise margin, read stability, read noise to flip the cell state, and is used to quantify the margin (RNM), SRAM cell, Static Noise Margin stability of a SRAM cell using a static approach. (SNM), write ability, Write noise margin (WNM). 2. LITERATURE REVIEW OF DIFFERENT 1. INTRODUCTION SRAM CELLS A SRAM cell consist of a latch, therefore the cell data is kept as long as power is turned on and 2.1 6T SRAM CELL refresh operation is not required for the SRAM cell. SRAM is mainly used for the cache memory in microprocessors, mainframe computers, engineering workstations and memory in hand held devices due to high speed and low power consumption. Each bit in an SRAM is stored on four transistors that form two cross coupled inverters. With increased device variability in nanometer scale technologies, SRAM becomes increasingly vulnerable to noise sources. The wider spread of local mismatch leads to reduced SRAM reliability. For the demand of minimizing power consumption during active operation, supply voltage scaling is often used. However, SRAM reliability is even more suspect at lower voltages. VCCmin is the minimum supply Figure 1: Standard 6T SRAM cell. voltage for an SRAM array to read and write safely The schematic diagram of 6T SRAM cell is shown in Fig.1.The conventional 6T SRAM memory cell is composed of two cross-coupled CMOS inverters with 1073 | P a g e
  • 2. Ajay Gadhe, Ujwal Shirode / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 3, Issue 1, January -February 2013, pp.1073-1078 two pass transistors connected to complementary bit- write operations yields a non destructive read lines. Fig. 1 shows this well known architecture, where operation or SNM-free read stability. the access transistors M5 and M6 are connected to the An additional leakage current path is introduced by word-line (WL) to perform the access write and read the separate read-port which increases the leakage operations through the column bit-lines (BL and current as compared to standard 6T bit cell. Therefore, BLB). Bit-lines act as input/output nodes carrying the an increased area overhead and leakage power make data from SRAM cells to a sense amplifier during read this design rather unattractive, since leakage power is operation, or from write circuitry to the memory cells a critical SRAM design metric, particularly for highly during write operations. All transistors have minimum energy constrained applications. length (Lmin), while their widths are typically design parameters. 2.3 9T SRAM CELL 6T SRAM cell implementation has the advantage The schematic of the new 9T SRAM cell is shown in of low static power dissipation. However, the potential Fig.3.Standard 6T bit cell along with three extra stability problem of 6T SRAM cell as shown in figure transistors were employed in nine-transistor (9T) 1 is such that during the read operation, a stored “0” SRAM bit cell to bypass read-current from the data can be overwritten by a “1”when the voltage at node Q storage nodes. reaches the Vth of NMOS M1 to pull node QB down to “0” and in turn pull node Q up even further to “1” due to the mechanism of positive feedback. To overcome the problem of data storage destruction during the read operation [3], an 8T-cell implementation was proposed, for which separate read/write word signal lines are used as shown in fig (2) to separate the data retention element and the data output element. 2.2 8T SRAM CELL Figure 3: 9T SRAM cell. A novel 9T SRAM cell with enhanced data stability and reduced leakage power consumption is presented in this section. The upper sub-circuit of the new memory cell is essentially a 6T SRAM cell.The two write access transistors (M1 and M2) are controlled by a write signal (WWL). The data is stored within this Figure 2: 8T SRAM cell upper memory sub-circuit. The lower sub-circuit of the new cell is composed of the bit-line access transistors A dual-port cell (8T-cell) is created by adding two (M7 and M8) and the read access transistor (M9). The data output transistors to 6T-cell, as shown in Fig. 2. operations of M7 and M8 are controlled by the data Separation of data retention element and data output stored in the cell. M9 is controlled by a separate read element means that there will be no correlation signal (RWL). between the read SNM cell and I cell. These separate read and write ports are controlled by read (RWL) and 3. STATIC NOISE MARGIN (SNM) write (WWL) word lines and used for accessing the bit cell during read and write cycles, respectively. In 8T SNM is the measure of stability of the SRAM bit cell topology, read and write operations of a cell to hold its data against noise. SNM of SRAM is standard 6T SRAM bit cell are de-coupled by creating defined as minimum amount of noise voltage present an isolated read-port or read buffer (comprised of two on the storing nodes of SRAM required to flip the transistors, M7 and M8). De-coupling of read and state of cell. 1074 | P a g e
  • 3. Ajay Gadhe, Ujwal Shirode / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 3, Issue 1, January -February 2013, pp.1073-1078 There are two methods to measure the SNM of In Fig. 4(a), the equivalent circuit for the SNM SRAM cell. First method is a graphical approach in definition [6] is shown. The two DC noise voltage which SNM can be obtained by drawing and mirroring sources are placed in series with the cross-coupled the inverter characteristics and then finding the inverters. The minimum value of noise voltage (Vn) maximum possible square between them. The second which is necessary to flip the state of the cell is approach involves the use of noise source voltages at recorded as SNM. the nodes as shown in figure 4 (a). The graphical method to determine the SNM uses SNM Dependences [4] includes cell ratio (CR), the static voltage transfer characteristics of the SRAM supply voltage and also pull up ratio .Cell ratio [5] is cell inverters. the ratio between sizes of the driver transistor to the load transistor during the read operation. Pull up ratio [5] is the ratio between sizes of the load transistor to the access transistor during write operation. With reference to figure (1), (M1) (M5) (During Read Operation) (M4) (M6) (During Write Operation) If the cell ratio increases, size of the driver transistor also increases, consequently increasing the current. As current increases, the speed of the SRAM cell also increases. Figure 4: (b) Butterfly curve for the SRAM cell 4. READ STABILITY AND WRITE- Fig.4 (b) superposes the voltage transfer ABILITY OF THE SRAM CELL characteristic (VTC) of one cell inverter to the inverse VTC of the other cell inverter. The resulting two-lobed 4.1 The SRAM cell read stability graph is called a "butterfly" curve and is used to Data retention of the SRAM cell, both in standby determine the SNM. Its value is defined as the side mode and during a read access, is an important length of the largest square that can be fitted inside the functional constraint in advanced technology nodes. lobes of the "butterfly" curve. The cell becomes less stable with lower supply voltage More the value of SNM, higher is the read stability increasing leakage currents and increasing variability, of the SRAM cell. A cell with lower RSNM has all resulting from technology scaling. The stability is poorer read stability. usually defined by the SNM [6] as the maximum value of DC noise voltage that can be tolerated by the 4.2 Write ability of the SRAM cell SRAM cell without changing the stored bit. Figure 4: (a) The standard setup for the SNM definition. 1075 | P a g e
  • 4. Ajay Gadhe, Ujwal Shirode / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 3, Issue 1, January -February 2013, pp.1073-1078 simulation sweeping the input of the inverters (QB and Q‟). For a successful write, only one cross point should be found on the butterfly curves, indicating that the cell is mono-stable. WSNM for writing „1‟ is the width of the smallest square that can be embedded between the lower-right half of the curves. WSNM for writing „0‟ can be obtained from a similar simulation. The final WSNM for the cell is the minimum of the margin for writing „0‟ and writing „1‟. A cell with lower WSNM has poorer write ability. Figure 5: (a) Circuit for WSNM [7] of writing „1‟. 5. SIMULATION AND RESULTS Write margin is the measure of the ability to write data into the SRAM cell. Write margin voltage is the All simulations are done using 130nm CMOS logic maximum noise voltage present at bit lines during process technology in Hspice environment. successful write operation. When noise voltages exceeds the write margin voltage, then write failure occurs. In this section, we introduce static approach for measuring write margin. The most common static Y1=1.10V approach uses SNM as a criterion. Y2=0.66V SNM = Y1-Y2 SNM= 440mV V(Q) V(Q) V(Q) V(QB) Figure 6: Simulation of HOLD SNM of 6T SRAM cell V(QB) Figure 5: (b) WSNM [7] of writing „1‟ is the width of the smallest embedded square at the lower-right side The cell is set in the write operation. Figure 5(a) shows the circuit for writing a „1‟ into the cell. Write SNM (WSNM) is measured using butterfly or VTC [8] curves (Figure5 b), which are obtained from a dc 1076 | P a g e
  • 5. Ajay Gadhe, Ujwal Shirode / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 3, Issue 1, January -February 2013, pp.1073-1078 Y1=1.12V Y1=1.10V Y2=0.897V Y2=0.66V SNM = Y1-Y2 SNM = Y1-Y2 SNM= 223mV SNM= 440mV V(Q) V(Q) V(QB) V(QB) Figure 7: Simulation of RNM of 6T SRAM cell Figure 9: Simulation of RNM of 8T SRAM cell Y1=1.10V Y2=0.66V SNM = Y1-Y2 SNM= 440mV Y1=0.556V Y2=0.0825V V(Q) SNM = Y1-Y2 473.5mV V(QB) Figure 8: Simulation of WNM of 6T SRAM cell V(QB) Figure 10: Simulation of RNM of 9T SRAM cell 1077 | P a g e
  • 6. Ajay Gadhe, Ujwal Shirode / International Journal of Engineering Research and Applications (IJERA) ISSN: 2248-9622 www.ijera.com Vol. 3, Issue 1, January -February 2013, pp.1073-1078 ACKNOWLEDGEMENTS We would like to sincerely thank to Dr. D.K. Gautam, head of the department of electronics engineering and technology, North Maharashtra University, Jalgaon who inspired us to do this work. Also we are thankful to the faculty of Department of Electronics engineering for their moral support. Y1=0.578V Y2=0.66V V(Q) SNM = Y1-Y2 REFERENCES SNM= 495mV [1] Jiajing Wang, Satyanand Nalam, and Benton H. Calhoun, Analyzing Static and Dynamic Write Margin for Nanometer SRAMs, Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA 22904, USA. [2] Kanak Agarwal,Sani Nassif .,Statistical Analysis of SRAM Cell Stability, IBM Research, Austin, TX. V(QB) [3] Mo Maggie Zhang., Performance Comparison of SRAM Cells Implemented in Figure 11: Simulation of WNM of 9T SRAM cell 6, 7 and 8-Transistor Cell Topologies, Electrical and Computer Engineering, University of California, Davis. Table 1: SNM for 6T, 8Tand 9T SRAM cell [4] B. Alorda, G. Torrens, S. Bota and J. Segura., Static-Noise Margin Analysis during Read SRAM HOLD READ WRITE Operation of 6T SRAM Cells, Univ. de CELL SNM SNM SNM les Illes Balears, Dept. Fisica, Cra. (mV) (mV) (mV) Valldemossa, 07071 Palma de Mallorca, Spain. 6T 440 223 473.5 [5] Debasis Mukherjee1, Hemanta Kr. Mondal2 8T 440 440 473.5 and B.V.R. Reddy3, Static Noise Margin 9T 440 440 495 Analysis of SRAM Cell for High Speed Application, IJCSI International Journal of Computer Science Issues, Vol. 7, Issue 5, 6. CONCLUSION September 2010. The stability performances of three SRAM [6] Evelyn Grossar, Michele Stucchi, cell topologies have been presented. As process KarenMaex, Read Stability and Write-Ability technologies continue to advance, the speed of Analysis of SRAM Cells for Nanometer SRAMs will increase, but devices will be more Technologies, IEEE JOURNAL OF SOLID- susceptible to mismatches, which worsen the static- STATE CIRCUITS, VOL. 41, NO. 11, noise margin of SRAM cells. NOVEMBER 2006, pp.2577-2588. The 6T SRAM provide very less RNM. To obtain [7] Jiajing Wang, Satyanand Nalam, and Benton higher RNM in 6T SRAM cell width of the pull down H.Calhoun, Analyzing Static and Dynamic transistor has to be increased but this increases area of Write Margin for Nanometer SRAMs, the SRAM which in turn increases the leakage Department of Electrical and Computer currents. Engineering, University of Virginia. The 8T SRAM cell provide higher read noise [8] Andrei S. Pavlov, Design and Test of margin. Due to asymmetric cell structure 8T SRAM Embedded SRAMs, doctoral diss., University cell may prone to failure during write operation. On of Waterloo, Ontario, Canada, 2005. the other hand 9T SRAM cell has higher RNM as well as WNM thus showing better stability performance as compare to 6T and 8T SRAM cell. 1078 | P a g e