SlideShare a Scribd company logo
S-Band Radar LDMOS Transistors
S.J.C.H. Theeuwen, H. Mollee
NXP Semiconductors, Gerstweg 2, 6534 AE, Nijmegen, The Netherlands
steven.theeuwen@nxp.com, hans.mollee@nxp.com
Abstract — LDMOS transistors have become the device choice for
microwave applications. An overview is given of the LDMOS
technology improvements at 3.6 GHz over the last decade, and RF
performance of LDMOS microwave products for S-band radar is
presented.
Index Terms— Microwave amplifiers, MOSFET power amplifiers,
Semiconductor device fabrication.
I. INTRODUCTION
More than ten years ago LDMOS transistors were
introduced as a replacement of bipolar transistors for RF power
applications [1,2]. Nowadays LDMOS technology is the
leading RF power technology for base station applications, in
particular for GSM-EDGE and WCDMA applications at 1 and
2 GHz, and more recently for WiMax applications around 2.7
GHz and 3.8 GHz.
One of the last niche application areas in which bipolar
devices were used was the 3-4 GHz microwave area, such as S-
band radar. Main reason for this was that earlier generations of
LDMOS showed similar performance at 3 GHz compared to
bipolar, not justifying redesign of complex radar systems.
The main driver for LDMOS is a high volume application,
which enables continuous improvement of the LDMOS
technology [3,4], and this has resulted in the latest generation
LDMOS, which outperforms bipolar at S-band frequencies
with some additional advantages such as ruggedness and better
thermal behaviour. In this article an overview is given of the
LDMOS improvements at 3-4 GHz and the LDMOS
performance for microwave products is presented.
II. LDMOS ADVANTAGES
LDMOS transistors are voltage-controlled devices, so no
gate current is flowing as in bipolar devices. This voltage
control allows a much simpler and cheaper bias circuitry.
Another advantage is the source connection to the bulk-
backside of LDMOS. Bipolar devices have a collector back
side and need isolating BeO packages in combination with
bond wires. LDMOS allows for a replacement of the toxic BeO
packages by environment friendly ceramic or plastic packages.
This is a major advantage for LDMOS. In- and output
matching is provided within the package to transform the
impedance levels and reduce RF losses. The bulk source is
eutectically soldered to the package without the need for source
bond wires resulting in high gain of the LDMOS transistor.
LDMOS also has a better temperature stability than bipolar.
Bipolar devices have a positive temperature coefficient leading
to thermal runaway. Bipolar therefore needs elaborate
temperature compensation like ballast resistors to protect the
device against failures. At high current, LDMOS has a negative
temperature coefficient automatically turning off the device
when fully powered. This leads to a natural advantage with
respect to thermal properties and ruggedness.
LDMOS devices have high flexibility with respect to pulse
duration, as is important for microwave applications. The
common source configuration of LDMOS stabilizes the device
and prevents oscillations at lower pulse durations.
The RF performance of LDMOS at 3-4 GHz frequencies has
also spectacularly improved in the last decade to become
significantly better than bipolar performance. In section IV the
LDMOS RF performance is shown for 3.6 GHz, but first state
of the art LDMOS technology is described in section III.
III. LDMOS TECHNOLOGY EVOLUTION
LDMOS technology is processed in an 8-inch CMOS-fab
capable of lithography down to 0.14 um, where the LDMOS
process is derived from C075 CMOS process. Additions to the
C075 process are LOCOS isolation, the source sinker to the
substrate, back-side metallization, CoSi2 gate silicidation,
tungsten shield, mushroom-type drain structure with thick 5
layer AlCu metallization. A schematic cross-section of
LDMOS is shown in Fig. 1.
P- substrate
P-type epi
P-well
N+ SN
P-sinker
shield
N+
Source Gate
n- drain extension
Drain
p+ substrate
P-type epi
P-well
N+ SN
P-sinker
shield
N+
Source Gate
n- drain extension
Drain
Source back side metallization
P- substrate
P-type epi
P-well
N+ SN
P-sinker
shield
N+
Source Gate
n- drain extension
Drain
p+ substrate
P-type epi
P-well
N+ SN
P-sinker
shield
N+
Source Gate
n- drain extension
DrainDrain
Source back side metallization
Fig. 1: Schematic cross-section of state of art RF LDMOST fabricated
in an 8 inch CMOS fab.
The LDMOS n+ source region is connected to the backside
via a metal bridge, a p+ sinker, and a highly conducting p+
substrate. Current will flow from source to drain if the gate is
positively biased inverting the laterally diffused p-well. The
LDMOS further consists of a drain extension area to realize a
breakdown voltage of more than 65V, and multi layer drain
metal to give excellent electromigration properties. The drain is
shielded from the gate by a tungsten field plate realizing a low
feedback capacitance and good hot carrier reliability properties.
Many fingers are placed in parallel to form a power die,
resulting in a total finger length of 10-100 millimeters.
IV. LDMOS PERFORMANCE EVOLUTION AT 3.6 GHZ
We show LDMOS devices measured at 3.6 GHz with a
load-pull set-up in a water-cooled test circuit. The devices have
a power level of 10-20 W to allow low Q matching with the
load pull tuners and measure the intrinsic device performance
evolution. All devices are biased with a supply voltage of 28V
and a drain current of 5 mA per mm finger length to achieve
class AB performance.
0.5
0.6
0.7
0.8
0.9
1.0
1.1
1998 2000 2002 2004 2006 2008 2010
Year
Pdens(W/mm)
Gen2
Gen4
Gen6
Gen7
Vd = 28 V
f = 3.6 GHz
Fig. 2: Evolution of the LDMOS power density at 3.6 GHz measured
for packaged devices without internal matching in a load pull set-up.
The evolution of power density (3dB compression power) is
shown in Fig. 2. Over the last decade the power density has
about doubled, achieving more than 1.0 W/mm for the latest
generation of LDMOS. Especially for microwave applications
there is a continuous demand for higher power. The gain
evolution at 3.6 GHz is shown in Fig. 3.
6
7
8
9
10
11
12
13
14
15
16
1998 2000 2002 2004 2006 2008 2010
Year
Gain(dB)
Gen2
Gen4
Gen6
Gen7
Vd = 28 V
f = 3.6 GHz
0
200
400
600
800
1998 2002 2006 2010
Year
Lg(nm)
Fig. 3: Gain improvement at f=3.6 GHz for the subsequent LDMOS
generations as measured by load pull techniques. The inset shows the
reduction of the gate length.
The gain has increased from 7dB in the year 2000 to 14dB
for the most recent technology generation. Bipolar devices
have at this frequency a gain of about 9dB, similar to the first
few LDMOS generations, not justifying a redesign of complex
radar systems. However, the 14dB gain of the later generations
is 5dB in excess of bipolar technology, and explains designing-
in LDMOS technology.
In the inset of Fig. 3 we have plotted the reduction of gate
length for the subsequent generations. The gate length has been
drastically reduced to increase the gain of the transistor via an
increase of the transconductance. Now other contributions, like
input capacitance, feedback capacitance and source inductance
become of importance. LDMOS leverages the advantage of a
low source inductance as a consequence of the backside source
connection (opposing the bond wires for bipolar devices) and
the low feedback capacitance due to the shielding construction.
30
40
50
60
1998 2000 2002 2004 2006 2008 2010
Year
DrainEfficiency(%)
Gen2
Vd = 28 V
f = 3.6 GHz
Gen4
Gen6
Gen7
Fig. 4: Evolution of LDMOS peak drain efficiency at 3.6 GHz for a
supply voltage of 28 V.
The evolution of drain efficiency at 3.6 GHz is plotted in Fig.
4. The peak efficiency of the latest generation LDMOS is about
55%, while the maximum theoretical class AB efficiency is
78.5%. The theoretical efficiency is approached at frequencies
below 1 GHz, indicating that frequency dependent losses limit
the efficiency at 3.6 GHz [3]. The evolution of peak efficiency
has mainly been achieved by a reduction of the output
capacitance losses. This reduction has been plotted in Fig. 5,
showing a reduction by a factor 2 in the last decade.
0.20
0.30
0.40
0.50
0.60
1998 2000 2002 2004 2006 2008 2010
Year
Cds(pF/W)
Gen2
Gen4
Gen6
Gen7
Fig. 5: Reduction of off-state output capacitance at Vd = 28V for
subsequent LDMOS generations.
This LDMOS evolution of power density, gain and
efficiency, fuelled by the high volume base station market, has
resulted in an extension of the application area of LDMOS.
The WiMax [4] and microwave markets nowadays widely use
LDMOS technology.
V. LDMOS RELIABILITY
The LDMOS process qualification complies with standards
of industry and is derived from the CMOS standard procedures
[5]. Special attention is paid to the hot carrier degradation:
electrons and holes are trapped in the surface oxide due to the
high electric fields in combination with high current densities
during operation. The degradation is measured for a transistor
at bias conditions, which is typically at a current of 5mA per
mm gate width and a drain-source voltage of 28V. A
degradation of bias current, maximum current or on-resistance
could lead to a change in device performance. In Fig. 6 we
have plotted the Idq degradation for the subsequent LDMOS
generations. The degradation has been reduced over the years
and has now arrived at a low level of less than 5% degradation
after an extrapolation to 20 years.
1 0
-2
1 0
-1
1 0
0
1 0
1
1 0
2
1 0
3
1 0
4
1 0
5
1 0
6
1 0
7
1 0
8
0 .8 0
0 .8 5
0 .9 0
0 .9 5
1 .0 0
2 00 8 , V d = 3 0V
2 00 6 , V d = 2 8V
2 00 4 , V d = 2 8V
2 00 0 , V d = 2 6V
2 0 yr
Ids(t)/Ids(0)
tim e (s )
Fig. 6: Degradation of the bias current as a function of time at room
temperature. The LDMOS is biased at 26-30 V and a quiescent
current of 5 mA/mm.
Furthermore we have extensively tested the LDMOS for
electromigration. The latest generations use wide and thick
mushroom-shape multi-layer AlCu metallization. The
electromigration MTF numbers for these stacks are superior
compared to the 2-layer Au metallization stack used in the
earliest LDMOS generations.
VI. LDMOS MICROWAVE PRODUCT PERFORMANCE
The continuous technology improvement has generated best
in class microwave products. This is demonstrated in Fig. 7 for
100W broadband matched devices in the range 2.7-3.1 GHz.
The gain is plotted for a Gen6 LDMOS device, a Gen4
LDMOS device, and a bipolar device. Where the Gen4 device
only has 0.5dB higher gain than the bipolar device, the Gen6
device outperforms the bipolar device by more than 5dB.
Furthermore the Gen6 LDMOS device has 10W more power
and higher drain efficiency over the band. This is illustrated in
Fig. 8. Clearly a 5-10% surplus of drain efficiency compared to
bipolar technology has been achieved.
Another LDMOS microwave product is the S-band LDMOS
in the frequency-range 3.1-3.5 GHz. The gain and efficiency of
this 120W microwave product is plotted in Fig. 9.
7
8
9
10
11
12
13
14
15
2.6 2.7 2.8 2.9 3 3.1 3.2
freq. (GHz)
Gain(dB)
LDMOS Gen6
LDMOS Gen4
Bipolar
Fig. 7: Gain comparison of broadband matched devices operating in the 2.7-3.1
GHz frequency band.
30
40
50
60
2.6 2.7 2.8 2.9 3 3.1 3.2
freq. (GHz)
Efficiency(%)
LDMOS Gen6
Bipolar
Fig. 8: Drain efficiency comparison of broadband matched devices
operating in the 2.7-3.1 GHz frequency band.
The S-band LDMOS clearly shows a considerably better
gain and efficiency compared to state of the art bipolar
products. At 3.1 GHz the efficiency is close to 50% and at the
high end of the frequency band, due to the broadband matching
of the device, still approximately 44% has been achieved. The
broadband gain is 11-12dB.
10
11
12
13
3.0 3.1 3.2 3.3 3.4 3.5 3.6
frequency (GHz)
Gain(dB)
40
45
50
Efficiency(%)
Gain
Efficiency
Fig. 9: Gain and efficiency of the 120 W S-band LDMOS.
VII. MICROWAVE PRODUCT RELIABILITY
The thermal impedance (ZTH) of the LDMOS products is
significantly better than their bipolar counterparts. For example
the bipolar has a ZTH of 0.28 K/W when operating at a pulse
length of 10 μs and a duty cycle of 10%, while the Gen 2
LDMOS equivalent has a ZTH of 0.13 K/W under identical
conditions. Furthermore the efficiency of LDMOS devices is
higher as shown in the previous paragraph. The combination of
the low ZTH and high efficiency results in a much lower
junction temperature for LDMOS and a better reliability. This
lower junction temperature in combination with the negative
temperature coefficient of MOS devices has a positive effect
on the overdrive capability of LDMOS products. The overdrive
capability of the LDMOS is shown in Fig. 10. This device
easily tolerates 5dB overdrive without degradation.
100
110
120
130
140
150
160
5 10 15 20 25 30
Pin (W)
PL(W)
Nominal input
Power
+1dB
+2dB
+3dB
+4dB
+5dB
Fig. 10: LDMOS overdrive capability measured at 3.5 GHz, Vds = 32
V, Idq = 100 mA, τP = 300 μs, δ = 10%.
MOS has a much
na ower distribution compared to bipolar.
ower levels (below
1W
the prospect of developing into
m new applications.
10 W
100 W
1 kW
Microwave products can withstand large VSWR mismatch
conditions and make use of a specially optimized LDMOS
process for pulse shaped signals. Given the importance of this
topic, we will elaborate on the ruggedness improvements in a
separate publication. In (phased array) radar applications,
where a large number of amplifiers are combined, the insertion
phase becomes an important parameter. The common source
configuration of LDMOS reduces the coupling between the
different bond-wires in the internal matching circuit. This
configuration in combination with the CMOS process control
improves the spread in insertion phase. LD
rr
VIII. RF POWER TECHNOLOGY OVERVIEW
During the last decade LDMOS technology has rapidly
evolved in performance becoming the preferred technology for
RF power transistors. In this article we have focussed on the
replacement of bipolar devices by LDMOS technology in
microwave applications and we have explained the advantages
of LDMOS. LDMOS is nowadays the technology of choice for
design-ins in base station, broadcast, ISM, and microwave
applications. GaAs technology is hardly used for these
applications, but is preferred for mobile phone amplifiers and
high frequencies applications. For lower p
) the market is dominated by CMOS.
New technologies are continuously evolving but have not
yet matured as RF power technology, where reliability is an
important criterion. GaN now has taken over from SiC the role
of most promising (but still immature) technology of the future
for high frequency, high power applications. Such a technology
could open the realization of advanced concepts like switch
mode power amplifiers. An overview of preferred technologies
for today’s design-ins as a function of power and frequency is
given in Fig. 11. We see than LDMOS is expanding towards
the high frequency (>4-5 GHz) applications and towards high
power applications. LDMOS has occupied a solid position as
RF Power technology with
ore and
GaAs
GaN
SiC
1 W
LDMOS-50V
LDMOS-28V
10 GHz2 GHz 5 GHz0.1 GHz
RF CMOS
Si bipolar
LDMOS-3V
10 W
100 W
1 kW
GaAs
GaN
SiC
1 W
LDMOS-50V
LDMOS-28V
10 GHz2 GHz 5 GHz0.1 GHz
RF CMOS
Si bipolar
LDMOS-3V
GaAs
GaN
SiC
1 W
LDMOS-50V
LDMOS-28V
10 GHz2 GHz 5 GHz0.1 GHz
RF CMOS
Si bipolar
LDMOS-3V
MOS is
continuously expanding towards higher power and frequency.
onal advantages as better ruggedness and
thermal properties.
g, R.
Heeres, R. Jos, and the LDMOS teams for their support.
[1]
Power Amplifier
[2]
tion Application”, Eu. Micr. Conf 1998, pp. 739-744,
[3]
towards the theoretical
[4]
beyond 2.5 GHz applications”, RWS
[5]
ations”, Microelectronics
Reliability 46, pp. 1279-1284, 2006.
Fig. 11: An overview of preferred transistor technologies for design-
ins in the year 2009 as a function of power and frequency. LD
IX. CONCLUSIONS
To conclude we have shown an overview of the LDMOS
technology improvements at 3.6 GHz over the last decade.
LDMOS technology has become the device choice for
microwave applications. The presented LDMOS microwave
products for S-band radar easily outperforms bipolar products,
while having additi
ACKNOWLEDGEMENTS
The authors acknowledge M. Murphy, J. Gajadharsin
REFERENCES
A. Wood, C. Dragon, W. Burger, “High Performance Silicon
LDMOS Technology for 2 GHz RF
Applications”, IEDM 1996, pp. 87-90, 1996.
H.F.F. Jos, “Novel LDMOS Structure for 2 GHz High Power
Basesta
1998.
F. van Rijs, S.J.C.H. Theeuwen, “Efficiency improvement of
LDMOS transistors for base stations:
limit”, IEDM2006, pp. 205-208, 2006.
F. van Rijs, “Status and trends of silicon LDMOS base station
PA technologies to go
2008, pp. 69-72, 2008.
P.J. van der Wel, S.J.C.H. Theeuwen, J.A. Bielen, Y. Li, R.A.
van den Heuvel, J.G. Gommans, F. van Rijs, P. Bron, H.J.F.
Peuscher, “Wear out failure mechanisms in aluminium and gold
based LDMOS RF power applic

More Related Content

What's hot

Performance Analysis of Double Hetero-gate Tunnel Field Effect Transistor
Performance Analysis of Double Hetero-gate Tunnel Field Effect TransistorPerformance Analysis of Double Hetero-gate Tunnel Field Effect Transistor
Performance Analysis of Double Hetero-gate Tunnel Field Effect Transistor
IDES Editor
 
CMOS Topic 3 -_the_device
CMOS Topic 3 -_the_deviceCMOS Topic 3 -_the_device
CMOS Topic 3 -_the_device
Ikhwan_Fakrudin
 
Sushant
SushantSushant
ULTRA HIGH SPEED FACTORIAL DESIGN IN SUB-NANOMETER TECHNOLOGY
ULTRA HIGH SPEED FACTORIAL DESIGN IN SUB-NANOMETER TECHNOLOGYULTRA HIGH SPEED FACTORIAL DESIGN IN SUB-NANOMETER TECHNOLOGY
ULTRA HIGH SPEED FACTORIAL DESIGN IN SUB-NANOMETER TECHNOLOGY
cscpconf
 
Fanout assemblies catalogue
Fanout assemblies catalogueFanout assemblies catalogue
Fanout assemblies catalogue
Fatih BATAL
 
Chapter3
Chapter3Chapter3
Chapter3
vidhya DS
 
Structural and Electrical Analysis of Various MOSFET Designs
Structural and Electrical Analysis of Various MOSFET DesignsStructural and Electrical Analysis of Various MOSFET Designs
Structural and Electrical Analysis of Various MOSFET Designs
IJERA Editor
 
Performance Comparison of CMOS and Finfet Based Circuits At 45nm Technology U...
Performance Comparison of CMOS and Finfet Based Circuits At 45nm Technology U...Performance Comparison of CMOS and Finfet Based Circuits At 45nm Technology U...
Performance Comparison of CMOS and Finfet Based Circuits At 45nm Technology U...
IJERA Editor
 
Variable Threshold MOSFET Approach (Through Dynamic Threshold MOSFET) For Uni...
Variable Threshold MOSFET Approach (Through Dynamic Threshold MOSFET) For Uni...Variable Threshold MOSFET Approach (Through Dynamic Threshold MOSFET) For Uni...
Variable Threshold MOSFET Approach (Through Dynamic Threshold MOSFET) For Uni...
VLSICS Design
 
17.cabling system
17.cabling system17.cabling system
17.cabling system
Jacinth Varughese
 
Mosfet
MosfetMosfet
CMOS logic circuits
CMOS logic circuitsCMOS logic circuits
CMOS logic circuits
Mahesh_Naidu
 
Cmos VLSI Design By umakant bhaskar gohatre
Cmos VLSI Design By umakant bhaskar gohatreCmos VLSI Design By umakant bhaskar gohatre
Cmos VLSI Design By umakant bhaskar gohatre
Smt. Indira Gandhi College of Engineering, Navi Mumbai, Mumbai
 
Tai lieu tong quan antena
Tai lieu tong quan antenaTai lieu tong quan antena
Tai lieu tong quan antena
Van Kiem Nguyen
 
Bi cmos technology
Bi cmos technologyBi cmos technology
Bi cmos technology
dharmsinghggu
 
Chapter 10
Chapter 10Chapter 10
Chapter 10
vidhya DS
 
Dual Metal Gate and Conventional MOSFET at Sub nm for Analog Application
Dual Metal Gate and Conventional MOSFET at Sub nm for Analog ApplicationDual Metal Gate and Conventional MOSFET at Sub nm for Analog Application
Dual Metal Gate and Conventional MOSFET at Sub nm for Analog Application
VLSICS Design
 
Novel finfet domino logic circuit using dual keepers
Novel finfet domino logic circuit using dual keepersNovel finfet domino logic circuit using dual keepers
Novel finfet domino logic circuit using dual keepers
Phoenixindia Incorporation
 
Circuitree_May2001
Circuitree_May2001Circuitree_May2001
Circuitree_May2001
Brad Hammack
 
Effects of Scaling on MOS Device Performance
Effects of Scaling on MOS Device PerformanceEffects of Scaling on MOS Device Performance
Effects of Scaling on MOS Device Performance
iosrjce
 

What's hot (20)

Performance Analysis of Double Hetero-gate Tunnel Field Effect Transistor
Performance Analysis of Double Hetero-gate Tunnel Field Effect TransistorPerformance Analysis of Double Hetero-gate Tunnel Field Effect Transistor
Performance Analysis of Double Hetero-gate Tunnel Field Effect Transistor
 
CMOS Topic 3 -_the_device
CMOS Topic 3 -_the_deviceCMOS Topic 3 -_the_device
CMOS Topic 3 -_the_device
 
Sushant
SushantSushant
Sushant
 
ULTRA HIGH SPEED FACTORIAL DESIGN IN SUB-NANOMETER TECHNOLOGY
ULTRA HIGH SPEED FACTORIAL DESIGN IN SUB-NANOMETER TECHNOLOGYULTRA HIGH SPEED FACTORIAL DESIGN IN SUB-NANOMETER TECHNOLOGY
ULTRA HIGH SPEED FACTORIAL DESIGN IN SUB-NANOMETER TECHNOLOGY
 
Fanout assemblies catalogue
Fanout assemblies catalogueFanout assemblies catalogue
Fanout assemblies catalogue
 
Chapter3
Chapter3Chapter3
Chapter3
 
Structural and Electrical Analysis of Various MOSFET Designs
Structural and Electrical Analysis of Various MOSFET DesignsStructural and Electrical Analysis of Various MOSFET Designs
Structural and Electrical Analysis of Various MOSFET Designs
 
Performance Comparison of CMOS and Finfet Based Circuits At 45nm Technology U...
Performance Comparison of CMOS and Finfet Based Circuits At 45nm Technology U...Performance Comparison of CMOS and Finfet Based Circuits At 45nm Technology U...
Performance Comparison of CMOS and Finfet Based Circuits At 45nm Technology U...
 
Variable Threshold MOSFET Approach (Through Dynamic Threshold MOSFET) For Uni...
Variable Threshold MOSFET Approach (Through Dynamic Threshold MOSFET) For Uni...Variable Threshold MOSFET Approach (Through Dynamic Threshold MOSFET) For Uni...
Variable Threshold MOSFET Approach (Through Dynamic Threshold MOSFET) For Uni...
 
17.cabling system
17.cabling system17.cabling system
17.cabling system
 
Mosfet
MosfetMosfet
Mosfet
 
CMOS logic circuits
CMOS logic circuitsCMOS logic circuits
CMOS logic circuits
 
Cmos VLSI Design By umakant bhaskar gohatre
Cmos VLSI Design By umakant bhaskar gohatreCmos VLSI Design By umakant bhaskar gohatre
Cmos VLSI Design By umakant bhaskar gohatre
 
Tai lieu tong quan antena
Tai lieu tong quan antenaTai lieu tong quan antena
Tai lieu tong quan antena
 
Bi cmos technology
Bi cmos technologyBi cmos technology
Bi cmos technology
 
Chapter 10
Chapter 10Chapter 10
Chapter 10
 
Dual Metal Gate and Conventional MOSFET at Sub nm for Analog Application
Dual Metal Gate and Conventional MOSFET at Sub nm for Analog ApplicationDual Metal Gate and Conventional MOSFET at Sub nm for Analog Application
Dual Metal Gate and Conventional MOSFET at Sub nm for Analog Application
 
Novel finfet domino logic circuit using dual keepers
Novel finfet domino logic circuit using dual keepersNovel finfet domino logic circuit using dual keepers
Novel finfet domino logic circuit using dual keepers
 
Circuitree_May2001
Circuitree_May2001Circuitree_May2001
Circuitree_May2001
 
Effects of Scaling on MOS Device Performance
Effects of Scaling on MOS Device PerformanceEffects of Scaling on MOS Device Performance
Effects of Scaling on MOS Device Performance
 

Similar to S-Band Radar LDMOS Transistors EuMW2009

LDMOS technology for RF power amplifiers
LDMOS technology for RF power amplifiersLDMOS technology for RF power amplifiers
LDMOS technology for RF power amplifiers
Steven Theeuwen
 
2012 The impact of a decade of Technology downscaling
2012 The impact of a decade of Technology downscaling2012 The impact of a decade of Technology downscaling
2012 The impact of a decade of Technology downscaling
Sofics
 
EDL2003_RF power silicon-on-glass VDMOSFET
EDL2003_RF power silicon-on-glass VDMOSFETEDL2003_RF power silicon-on-glass VDMOSFET
EDL2003_RF power silicon-on-glass VDMOSFET
Steven Theeuwen
 
IEDM2006_Efficiency improvement
IEDM2006_Efficiency improvementIEDM2006_Efficiency improvement
IEDM2006_Efficiency improvement
Steven Theeuwen
 
mosfet scaling_
mosfet scaling_mosfet scaling_
mosfet scaling_
Web Design & Development
 
Iaetsd design and analysis of low-leakage high-speed
Iaetsd design and analysis of low-leakage high-speedIaetsd design and analysis of low-leakage high-speed
Iaetsd design and analysis of low-leakage high-speed
Iaetsd Iaetsd
 
Analysis of pocket double gate tunnel fet for low stand by power logic circuits
Analysis of pocket double gate tunnel fet for low stand by power logic circuitsAnalysis of pocket double gate tunnel fet for low stand by power logic circuits
Analysis of pocket double gate tunnel fet for low stand by power logic circuits
VLSICS Design
 
Design & Performance Analysis of DG-MOSFET for Reduction of Short Channel Eff...
Design & Performance Analysis of DG-MOSFET for Reduction of Short Channel Eff...Design & Performance Analysis of DG-MOSFET for Reduction of Short Channel Eff...
Design & Performance Analysis of DG-MOSFET for Reduction of Short Channel Eff...
IJERA Editor
 
P1121110526
P1121110526P1121110526
P1121110526
Ashraf Aboshosha
 
F044082128
F044082128F044082128
F044082128
IJERA Editor
 
Relevance of Grooved NMOSFETS in Ultra Deep Submicron Region in Low Power App...
Relevance of Grooved NMOSFETS in Ultra Deep Submicron Region in Low Power App...Relevance of Grooved NMOSFETS in Ultra Deep Submicron Region in Low Power App...
Relevance of Grooved NMOSFETS in Ultra Deep Submicron Region in Low Power App...
VLSICS Design
 
RELEVANCE OF GROOVED NMOSFETS IN ULTRA DEEP SUBMICRON REGION IN LOW POWER APP...
RELEVANCE OF GROOVED NMOSFETS IN ULTRA DEEP SUBMICRON REGION IN LOW POWER APP...RELEVANCE OF GROOVED NMOSFETS IN ULTRA DEEP SUBMICRON REGION IN LOW POWER APP...
RELEVANCE OF GROOVED NMOSFETS IN ULTRA DEEP SUBMICRON REGION IN LOW POWER APP...
VLSICS Design
 
Sub-Threshold Leakage Current Reduction Techniques In VLSI Circuits -A Survey
Sub-Threshold Leakage Current Reduction Techniques In VLSI Circuits -A SurveySub-Threshold Leakage Current Reduction Techniques In VLSI Circuits -A Survey
Sub-Threshold Leakage Current Reduction Techniques In VLSI Circuits -A Survey
IJERA Editor
 
FGMOS BASED LOW-VOLTAGE LOW-POWER HIGH OUTPUT IMPEDANCE REGULATED CASCODE CUR...
FGMOS BASED LOW-VOLTAGE LOW-POWER HIGH OUTPUT IMPEDANCE REGULATED CASCODE CUR...FGMOS BASED LOW-VOLTAGE LOW-POWER HIGH OUTPUT IMPEDANCE REGULATED CASCODE CUR...
FGMOS BASED LOW-VOLTAGE LOW-POWER HIGH OUTPUT IMPEDANCE REGULATED CASCODE CUR...
VLSICS Design
 
Matematicas
MatematicasMatematicas
Matematicas
legosss
 
Ch7 lecture slides Chenming Hu Device for IC
Ch7 lecture slides Chenming Hu Device for ICCh7 lecture slides Chenming Hu Device for IC
Ch7 lecture slides Chenming Hu Device for IC
Chenming Hu
 
Threshold Voltage Roll-off by Structural Parameters for Sub-10 nm Asymmetric ...
Threshold Voltage Roll-off by Structural Parameters for Sub-10 nm Asymmetric ...Threshold Voltage Roll-off by Structural Parameters for Sub-10 nm Asymmetric ...
Threshold Voltage Roll-off by Structural Parameters for Sub-10 nm Asymmetric ...
TELKOMNIKA JOURNAL
 
power electronics.pdf
power electronics.pdfpower electronics.pdf
power electronics.pdf
Gollapalli Sreenivasulu
 
Finfet Technology
Finfet TechnologyFinfet Technology
Finfet Technology
Srinivas Vasamsetti
 
A Two-stages Microstrip Power Amplifier for WiMAX Applications
A Two-stages Microstrip Power Amplifier for WiMAX ApplicationsA Two-stages Microstrip Power Amplifier for WiMAX Applications
A Two-stages Microstrip Power Amplifier for WiMAX Applications
TELKOMNIKA JOURNAL
 

Similar to S-Band Radar LDMOS Transistors EuMW2009 (20)

LDMOS technology for RF power amplifiers
LDMOS technology for RF power amplifiersLDMOS technology for RF power amplifiers
LDMOS technology for RF power amplifiers
 
2012 The impact of a decade of Technology downscaling
2012 The impact of a decade of Technology downscaling2012 The impact of a decade of Technology downscaling
2012 The impact of a decade of Technology downscaling
 
EDL2003_RF power silicon-on-glass VDMOSFET
EDL2003_RF power silicon-on-glass VDMOSFETEDL2003_RF power silicon-on-glass VDMOSFET
EDL2003_RF power silicon-on-glass VDMOSFET
 
IEDM2006_Efficiency improvement
IEDM2006_Efficiency improvementIEDM2006_Efficiency improvement
IEDM2006_Efficiency improvement
 
mosfet scaling_
mosfet scaling_mosfet scaling_
mosfet scaling_
 
Iaetsd design and analysis of low-leakage high-speed
Iaetsd design and analysis of low-leakage high-speedIaetsd design and analysis of low-leakage high-speed
Iaetsd design and analysis of low-leakage high-speed
 
Analysis of pocket double gate tunnel fet for low stand by power logic circuits
Analysis of pocket double gate tunnel fet for low stand by power logic circuitsAnalysis of pocket double gate tunnel fet for low stand by power logic circuits
Analysis of pocket double gate tunnel fet for low stand by power logic circuits
 
Design & Performance Analysis of DG-MOSFET for Reduction of Short Channel Eff...
Design & Performance Analysis of DG-MOSFET for Reduction of Short Channel Eff...Design & Performance Analysis of DG-MOSFET for Reduction of Short Channel Eff...
Design & Performance Analysis of DG-MOSFET for Reduction of Short Channel Eff...
 
P1121110526
P1121110526P1121110526
P1121110526
 
F044082128
F044082128F044082128
F044082128
 
Relevance of Grooved NMOSFETS in Ultra Deep Submicron Region in Low Power App...
Relevance of Grooved NMOSFETS in Ultra Deep Submicron Region in Low Power App...Relevance of Grooved NMOSFETS in Ultra Deep Submicron Region in Low Power App...
Relevance of Grooved NMOSFETS in Ultra Deep Submicron Region in Low Power App...
 
RELEVANCE OF GROOVED NMOSFETS IN ULTRA DEEP SUBMICRON REGION IN LOW POWER APP...
RELEVANCE OF GROOVED NMOSFETS IN ULTRA DEEP SUBMICRON REGION IN LOW POWER APP...RELEVANCE OF GROOVED NMOSFETS IN ULTRA DEEP SUBMICRON REGION IN LOW POWER APP...
RELEVANCE OF GROOVED NMOSFETS IN ULTRA DEEP SUBMICRON REGION IN LOW POWER APP...
 
Sub-Threshold Leakage Current Reduction Techniques In VLSI Circuits -A Survey
Sub-Threshold Leakage Current Reduction Techniques In VLSI Circuits -A SurveySub-Threshold Leakage Current Reduction Techniques In VLSI Circuits -A Survey
Sub-Threshold Leakage Current Reduction Techniques In VLSI Circuits -A Survey
 
FGMOS BASED LOW-VOLTAGE LOW-POWER HIGH OUTPUT IMPEDANCE REGULATED CASCODE CUR...
FGMOS BASED LOW-VOLTAGE LOW-POWER HIGH OUTPUT IMPEDANCE REGULATED CASCODE CUR...FGMOS BASED LOW-VOLTAGE LOW-POWER HIGH OUTPUT IMPEDANCE REGULATED CASCODE CUR...
FGMOS BASED LOW-VOLTAGE LOW-POWER HIGH OUTPUT IMPEDANCE REGULATED CASCODE CUR...
 
Matematicas
MatematicasMatematicas
Matematicas
 
Ch7 lecture slides Chenming Hu Device for IC
Ch7 lecture slides Chenming Hu Device for ICCh7 lecture slides Chenming Hu Device for IC
Ch7 lecture slides Chenming Hu Device for IC
 
Threshold Voltage Roll-off by Structural Parameters for Sub-10 nm Asymmetric ...
Threshold Voltage Roll-off by Structural Parameters for Sub-10 nm Asymmetric ...Threshold Voltage Roll-off by Structural Parameters for Sub-10 nm Asymmetric ...
Threshold Voltage Roll-off by Structural Parameters for Sub-10 nm Asymmetric ...
 
power electronics.pdf
power electronics.pdfpower electronics.pdf
power electronics.pdf
 
Finfet Technology
Finfet TechnologyFinfet Technology
Finfet Technology
 
A Two-stages Microstrip Power Amplifier for WiMAX Applications
A Two-stages Microstrip Power Amplifier for WiMAX ApplicationsA Two-stages Microstrip Power Amplifier for WiMAX Applications
A Two-stages Microstrip Power Amplifier for WiMAX Applications
 

More from Steven Theeuwen

High Efficiency LDMOS Technology for UMTS base stations_journal
High Efficiency LDMOS Technology for UMTS base stations_journalHigh Efficiency LDMOS Technology for UMTS base stations_journal
High Efficiency LDMOS Technology for UMTS base stations_journal
Steven Theeuwen
 
PRB_wellock_1999
PRB_wellock_1999PRB_wellock_1999
PRB_wellock_1999
Steven Theeuwen
 
Negative resistance contribution of a domain-wall structure in a constricted ...
Negative resistance contribution of a domain-wall structure in a constricted ...Negative resistance contribution of a domain-wall structure in a constricted ...
Negative resistance contribution of a domain-wall structure in a constricted ...
Steven Theeuwen
 
theeuwenapl
theeuwenapltheeuwenapl
theeuwenapl
Steven Theeuwen
 
APL
APLAPL
A 72% PAE, 10-Watt, CMOS-LDMOS Switch-Mode Power Amplifier for Sub-1GHz Appli...
A 72% PAE, 10-Watt, CMOS-LDMOS Switch-Mode Power Amplifier for Sub-1GHz Appli...A 72% PAE, 10-Watt, CMOS-LDMOS Switch-Mode Power Amplifier for Sub-1GHz Appli...
A 72% PAE, 10-Watt, CMOS-LDMOS Switch-Mode Power Amplifier for Sub-1GHz Appli...
Steven Theeuwen
 
mwj201012-RF Lighting
mwj201012-RF Lightingmwj201012-RF Lighting
mwj201012-RF Lighting
Steven Theeuwen
 
LDMOS Ruggedness Reliability Microwave Journal
LDMOS Ruggedness Reliability Microwave JournalLDMOS Ruggedness Reliability Microwave Journal
LDMOS Ruggedness Reliability Microwave Journal
Steven Theeuwen
 
High_Voltage_RF_LDMOS_Technology_for_Broadcast_Applications_pub
High_Voltage_RF_LDMOS_Technology_for_Broadcast_Applications_pubHigh_Voltage_RF_LDMOS_Technology_for_Broadcast_Applications_pub
High_Voltage_RF_LDMOS_Technology_for_Broadcast_Applications_pub
Steven Theeuwen
 

More from Steven Theeuwen (10)

High Efficiency LDMOS Technology for UMTS base stations_journal
High Efficiency LDMOS Technology for UMTS base stations_journalHigh Efficiency LDMOS Technology for UMTS base stations_journal
High Efficiency LDMOS Technology for UMTS base stations_journal
 
SJCH_Theeuwen_Thesis
SJCH_Theeuwen_ThesisSJCH_Theeuwen_Thesis
SJCH_Theeuwen_Thesis
 
PRB_wellock_1999
PRB_wellock_1999PRB_wellock_1999
PRB_wellock_1999
 
Negative resistance contribution of a domain-wall structure in a constricted ...
Negative resistance contribution of a domain-wall structure in a constricted ...Negative resistance contribution of a domain-wall structure in a constricted ...
Negative resistance contribution of a domain-wall structure in a constricted ...
 
theeuwenapl
theeuwenapltheeuwenapl
theeuwenapl
 
APL
APLAPL
APL
 
A 72% PAE, 10-Watt, CMOS-LDMOS Switch-Mode Power Amplifier for Sub-1GHz Appli...
A 72% PAE, 10-Watt, CMOS-LDMOS Switch-Mode Power Amplifier for Sub-1GHz Appli...A 72% PAE, 10-Watt, CMOS-LDMOS Switch-Mode Power Amplifier for Sub-1GHz Appli...
A 72% PAE, 10-Watt, CMOS-LDMOS Switch-Mode Power Amplifier for Sub-1GHz Appli...
 
mwj201012-RF Lighting
mwj201012-RF Lightingmwj201012-RF Lighting
mwj201012-RF Lighting
 
LDMOS Ruggedness Reliability Microwave Journal
LDMOS Ruggedness Reliability Microwave JournalLDMOS Ruggedness Reliability Microwave Journal
LDMOS Ruggedness Reliability Microwave Journal
 
High_Voltage_RF_LDMOS_Technology_for_Broadcast_Applications_pub
High_Voltage_RF_LDMOS_Technology_for_Broadcast_Applications_pubHigh_Voltage_RF_LDMOS_Technology_for_Broadcast_Applications_pub
High_Voltage_RF_LDMOS_Technology_for_Broadcast_Applications_pub
 

S-Band Radar LDMOS Transistors EuMW2009

  • 1. S-Band Radar LDMOS Transistors S.J.C.H. Theeuwen, H. Mollee NXP Semiconductors, Gerstweg 2, 6534 AE, Nijmegen, The Netherlands steven.theeuwen@nxp.com, hans.mollee@nxp.com Abstract — LDMOS transistors have become the device choice for microwave applications. An overview is given of the LDMOS technology improvements at 3.6 GHz over the last decade, and RF performance of LDMOS microwave products for S-band radar is presented. Index Terms— Microwave amplifiers, MOSFET power amplifiers, Semiconductor device fabrication. I. INTRODUCTION More than ten years ago LDMOS transistors were introduced as a replacement of bipolar transistors for RF power applications [1,2]. Nowadays LDMOS technology is the leading RF power technology for base station applications, in particular for GSM-EDGE and WCDMA applications at 1 and 2 GHz, and more recently for WiMax applications around 2.7 GHz and 3.8 GHz. One of the last niche application areas in which bipolar devices were used was the 3-4 GHz microwave area, such as S- band radar. Main reason for this was that earlier generations of LDMOS showed similar performance at 3 GHz compared to bipolar, not justifying redesign of complex radar systems. The main driver for LDMOS is a high volume application, which enables continuous improvement of the LDMOS technology [3,4], and this has resulted in the latest generation LDMOS, which outperforms bipolar at S-band frequencies with some additional advantages such as ruggedness and better thermal behaviour. In this article an overview is given of the LDMOS improvements at 3-4 GHz and the LDMOS performance for microwave products is presented. II. LDMOS ADVANTAGES LDMOS transistors are voltage-controlled devices, so no gate current is flowing as in bipolar devices. This voltage control allows a much simpler and cheaper bias circuitry. Another advantage is the source connection to the bulk- backside of LDMOS. Bipolar devices have a collector back side and need isolating BeO packages in combination with bond wires. LDMOS allows for a replacement of the toxic BeO packages by environment friendly ceramic or plastic packages. This is a major advantage for LDMOS. In- and output matching is provided within the package to transform the impedance levels and reduce RF losses. The bulk source is eutectically soldered to the package without the need for source bond wires resulting in high gain of the LDMOS transistor. LDMOS also has a better temperature stability than bipolar. Bipolar devices have a positive temperature coefficient leading to thermal runaway. Bipolar therefore needs elaborate temperature compensation like ballast resistors to protect the device against failures. At high current, LDMOS has a negative temperature coefficient automatically turning off the device when fully powered. This leads to a natural advantage with respect to thermal properties and ruggedness. LDMOS devices have high flexibility with respect to pulse duration, as is important for microwave applications. The common source configuration of LDMOS stabilizes the device and prevents oscillations at lower pulse durations. The RF performance of LDMOS at 3-4 GHz frequencies has also spectacularly improved in the last decade to become significantly better than bipolar performance. In section IV the LDMOS RF performance is shown for 3.6 GHz, but first state of the art LDMOS technology is described in section III. III. LDMOS TECHNOLOGY EVOLUTION LDMOS technology is processed in an 8-inch CMOS-fab capable of lithography down to 0.14 um, where the LDMOS process is derived from C075 CMOS process. Additions to the C075 process are LOCOS isolation, the source sinker to the substrate, back-side metallization, CoSi2 gate silicidation, tungsten shield, mushroom-type drain structure with thick 5 layer AlCu metallization. A schematic cross-section of LDMOS is shown in Fig. 1. P- substrate P-type epi P-well N+ SN P-sinker shield N+ Source Gate n- drain extension Drain p+ substrate P-type epi P-well N+ SN P-sinker shield N+ Source Gate n- drain extension Drain Source back side metallization P- substrate P-type epi P-well N+ SN P-sinker shield N+ Source Gate n- drain extension Drain p+ substrate P-type epi P-well N+ SN P-sinker shield N+ Source Gate n- drain extension DrainDrain Source back side metallization Fig. 1: Schematic cross-section of state of art RF LDMOST fabricated in an 8 inch CMOS fab. The LDMOS n+ source region is connected to the backside via a metal bridge, a p+ sinker, and a highly conducting p+ substrate. Current will flow from source to drain if the gate is positively biased inverting the laterally diffused p-well. The LDMOS further consists of a drain extension area to realize a breakdown voltage of more than 65V, and multi layer drain metal to give excellent electromigration properties. The drain is shielded from the gate by a tungsten field plate realizing a low
  • 2. feedback capacitance and good hot carrier reliability properties. Many fingers are placed in parallel to form a power die, resulting in a total finger length of 10-100 millimeters. IV. LDMOS PERFORMANCE EVOLUTION AT 3.6 GHZ We show LDMOS devices measured at 3.6 GHz with a load-pull set-up in a water-cooled test circuit. The devices have a power level of 10-20 W to allow low Q matching with the load pull tuners and measure the intrinsic device performance evolution. All devices are biased with a supply voltage of 28V and a drain current of 5 mA per mm finger length to achieve class AB performance. 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1998 2000 2002 2004 2006 2008 2010 Year Pdens(W/mm) Gen2 Gen4 Gen6 Gen7 Vd = 28 V f = 3.6 GHz Fig. 2: Evolution of the LDMOS power density at 3.6 GHz measured for packaged devices without internal matching in a load pull set-up. The evolution of power density (3dB compression power) is shown in Fig. 2. Over the last decade the power density has about doubled, achieving more than 1.0 W/mm for the latest generation of LDMOS. Especially for microwave applications there is a continuous demand for higher power. The gain evolution at 3.6 GHz is shown in Fig. 3. 6 7 8 9 10 11 12 13 14 15 16 1998 2000 2002 2004 2006 2008 2010 Year Gain(dB) Gen2 Gen4 Gen6 Gen7 Vd = 28 V f = 3.6 GHz 0 200 400 600 800 1998 2002 2006 2010 Year Lg(nm) Fig. 3: Gain improvement at f=3.6 GHz for the subsequent LDMOS generations as measured by load pull techniques. The inset shows the reduction of the gate length. The gain has increased from 7dB in the year 2000 to 14dB for the most recent technology generation. Bipolar devices have at this frequency a gain of about 9dB, similar to the first few LDMOS generations, not justifying a redesign of complex radar systems. However, the 14dB gain of the later generations is 5dB in excess of bipolar technology, and explains designing- in LDMOS technology. In the inset of Fig. 3 we have plotted the reduction of gate length for the subsequent generations. The gate length has been drastically reduced to increase the gain of the transistor via an increase of the transconductance. Now other contributions, like input capacitance, feedback capacitance and source inductance become of importance. LDMOS leverages the advantage of a low source inductance as a consequence of the backside source connection (opposing the bond wires for bipolar devices) and the low feedback capacitance due to the shielding construction. 30 40 50 60 1998 2000 2002 2004 2006 2008 2010 Year DrainEfficiency(%) Gen2 Vd = 28 V f = 3.6 GHz Gen4 Gen6 Gen7 Fig. 4: Evolution of LDMOS peak drain efficiency at 3.6 GHz for a supply voltage of 28 V. The evolution of drain efficiency at 3.6 GHz is plotted in Fig. 4. The peak efficiency of the latest generation LDMOS is about 55%, while the maximum theoretical class AB efficiency is 78.5%. The theoretical efficiency is approached at frequencies below 1 GHz, indicating that frequency dependent losses limit the efficiency at 3.6 GHz [3]. The evolution of peak efficiency has mainly been achieved by a reduction of the output capacitance losses. This reduction has been plotted in Fig. 5, showing a reduction by a factor 2 in the last decade. 0.20 0.30 0.40 0.50 0.60 1998 2000 2002 2004 2006 2008 2010 Year Cds(pF/W) Gen2 Gen4 Gen6 Gen7 Fig. 5: Reduction of off-state output capacitance at Vd = 28V for subsequent LDMOS generations. This LDMOS evolution of power density, gain and efficiency, fuelled by the high volume base station market, has resulted in an extension of the application area of LDMOS. The WiMax [4] and microwave markets nowadays widely use LDMOS technology.
  • 3. V. LDMOS RELIABILITY The LDMOS process qualification complies with standards of industry and is derived from the CMOS standard procedures [5]. Special attention is paid to the hot carrier degradation: electrons and holes are trapped in the surface oxide due to the high electric fields in combination with high current densities during operation. The degradation is measured for a transistor at bias conditions, which is typically at a current of 5mA per mm gate width and a drain-source voltage of 28V. A degradation of bias current, maximum current or on-resistance could lead to a change in device performance. In Fig. 6 we have plotted the Idq degradation for the subsequent LDMOS generations. The degradation has been reduced over the years and has now arrived at a low level of less than 5% degradation after an extrapolation to 20 years. 1 0 -2 1 0 -1 1 0 0 1 0 1 1 0 2 1 0 3 1 0 4 1 0 5 1 0 6 1 0 7 1 0 8 0 .8 0 0 .8 5 0 .9 0 0 .9 5 1 .0 0 2 00 8 , V d = 3 0V 2 00 6 , V d = 2 8V 2 00 4 , V d = 2 8V 2 00 0 , V d = 2 6V 2 0 yr Ids(t)/Ids(0) tim e (s ) Fig. 6: Degradation of the bias current as a function of time at room temperature. The LDMOS is biased at 26-30 V and a quiescent current of 5 mA/mm. Furthermore we have extensively tested the LDMOS for electromigration. The latest generations use wide and thick mushroom-shape multi-layer AlCu metallization. The electromigration MTF numbers for these stacks are superior compared to the 2-layer Au metallization stack used in the earliest LDMOS generations. VI. LDMOS MICROWAVE PRODUCT PERFORMANCE The continuous technology improvement has generated best in class microwave products. This is demonstrated in Fig. 7 for 100W broadband matched devices in the range 2.7-3.1 GHz. The gain is plotted for a Gen6 LDMOS device, a Gen4 LDMOS device, and a bipolar device. Where the Gen4 device only has 0.5dB higher gain than the bipolar device, the Gen6 device outperforms the bipolar device by more than 5dB. Furthermore the Gen6 LDMOS device has 10W more power and higher drain efficiency over the band. This is illustrated in Fig. 8. Clearly a 5-10% surplus of drain efficiency compared to bipolar technology has been achieved. Another LDMOS microwave product is the S-band LDMOS in the frequency-range 3.1-3.5 GHz. The gain and efficiency of this 120W microwave product is plotted in Fig. 9. 7 8 9 10 11 12 13 14 15 2.6 2.7 2.8 2.9 3 3.1 3.2 freq. (GHz) Gain(dB) LDMOS Gen6 LDMOS Gen4 Bipolar Fig. 7: Gain comparison of broadband matched devices operating in the 2.7-3.1 GHz frequency band. 30 40 50 60 2.6 2.7 2.8 2.9 3 3.1 3.2 freq. (GHz) Efficiency(%) LDMOS Gen6 Bipolar Fig. 8: Drain efficiency comparison of broadband matched devices operating in the 2.7-3.1 GHz frequency band. The S-band LDMOS clearly shows a considerably better gain and efficiency compared to state of the art bipolar products. At 3.1 GHz the efficiency is close to 50% and at the high end of the frequency band, due to the broadband matching of the device, still approximately 44% has been achieved. The broadband gain is 11-12dB. 10 11 12 13 3.0 3.1 3.2 3.3 3.4 3.5 3.6 frequency (GHz) Gain(dB) 40 45 50 Efficiency(%) Gain Efficiency Fig. 9: Gain and efficiency of the 120 W S-band LDMOS. VII. MICROWAVE PRODUCT RELIABILITY The thermal impedance (ZTH) of the LDMOS products is significantly better than their bipolar counterparts. For example the bipolar has a ZTH of 0.28 K/W when operating at a pulse
  • 4. length of 10 μs and a duty cycle of 10%, while the Gen 2 LDMOS equivalent has a ZTH of 0.13 K/W under identical conditions. Furthermore the efficiency of LDMOS devices is higher as shown in the previous paragraph. The combination of the low ZTH and high efficiency results in a much lower junction temperature for LDMOS and a better reliability. This lower junction temperature in combination with the negative temperature coefficient of MOS devices has a positive effect on the overdrive capability of LDMOS products. The overdrive capability of the LDMOS is shown in Fig. 10. This device easily tolerates 5dB overdrive without degradation. 100 110 120 130 140 150 160 5 10 15 20 25 30 Pin (W) PL(W) Nominal input Power +1dB +2dB +3dB +4dB +5dB Fig. 10: LDMOS overdrive capability measured at 3.5 GHz, Vds = 32 V, Idq = 100 mA, τP = 300 μs, δ = 10%. MOS has a much na ower distribution compared to bipolar. ower levels (below 1W the prospect of developing into m new applications. 10 W 100 W 1 kW Microwave products can withstand large VSWR mismatch conditions and make use of a specially optimized LDMOS process for pulse shaped signals. Given the importance of this topic, we will elaborate on the ruggedness improvements in a separate publication. In (phased array) radar applications, where a large number of amplifiers are combined, the insertion phase becomes an important parameter. The common source configuration of LDMOS reduces the coupling between the different bond-wires in the internal matching circuit. This configuration in combination with the CMOS process control improves the spread in insertion phase. LD rr VIII. RF POWER TECHNOLOGY OVERVIEW During the last decade LDMOS technology has rapidly evolved in performance becoming the preferred technology for RF power transistors. In this article we have focussed on the replacement of bipolar devices by LDMOS technology in microwave applications and we have explained the advantages of LDMOS. LDMOS is nowadays the technology of choice for design-ins in base station, broadcast, ISM, and microwave applications. GaAs technology is hardly used for these applications, but is preferred for mobile phone amplifiers and high frequencies applications. For lower p ) the market is dominated by CMOS. New technologies are continuously evolving but have not yet matured as RF power technology, where reliability is an important criterion. GaN now has taken over from SiC the role of most promising (but still immature) technology of the future for high frequency, high power applications. Such a technology could open the realization of advanced concepts like switch mode power amplifiers. An overview of preferred technologies for today’s design-ins as a function of power and frequency is given in Fig. 11. We see than LDMOS is expanding towards the high frequency (>4-5 GHz) applications and towards high power applications. LDMOS has occupied a solid position as RF Power technology with ore and GaAs GaN SiC 1 W LDMOS-50V LDMOS-28V 10 GHz2 GHz 5 GHz0.1 GHz RF CMOS Si bipolar LDMOS-3V 10 W 100 W 1 kW GaAs GaN SiC 1 W LDMOS-50V LDMOS-28V 10 GHz2 GHz 5 GHz0.1 GHz RF CMOS Si bipolar LDMOS-3V GaAs GaN SiC 1 W LDMOS-50V LDMOS-28V 10 GHz2 GHz 5 GHz0.1 GHz RF CMOS Si bipolar LDMOS-3V MOS is continuously expanding towards higher power and frequency. onal advantages as better ruggedness and thermal properties. g, R. Heeres, R. Jos, and the LDMOS teams for their support. [1] Power Amplifier [2] tion Application”, Eu. Micr. Conf 1998, pp. 739-744, [3] towards the theoretical [4] beyond 2.5 GHz applications”, RWS [5] ations”, Microelectronics Reliability 46, pp. 1279-1284, 2006. Fig. 11: An overview of preferred transistor technologies for design- ins in the year 2009 as a function of power and frequency. LD IX. CONCLUSIONS To conclude we have shown an overview of the LDMOS technology improvements at 3.6 GHz over the last decade. LDMOS technology has become the device choice for microwave applications. The presented LDMOS microwave products for S-band radar easily outperforms bipolar products, while having additi ACKNOWLEDGEMENTS The authors acknowledge M. Murphy, J. Gajadharsin REFERENCES A. Wood, C. Dragon, W. Burger, “High Performance Silicon LDMOS Technology for 2 GHz RF Applications”, IEDM 1996, pp. 87-90, 1996. H.F.F. Jos, “Novel LDMOS Structure for 2 GHz High Power Basesta 1998. F. van Rijs, S.J.C.H. Theeuwen, “Efficiency improvement of LDMOS transistors for base stations: limit”, IEDM2006, pp. 205-208, 2006. F. van Rijs, “Status and trends of silicon LDMOS base station PA technologies to go 2008, pp. 69-72, 2008. P.J. van der Wel, S.J.C.H. Theeuwen, J.A. Bielen, Y. Li, R.A. van den Heuvel, J.G. Gommans, F. van Rijs, P. Bron, H.J.F. Peuscher, “Wear out failure mechanisms in aluminium and gold based LDMOS RF power applic