Srinivas_Kotha_CV
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Srinivas Kotha is seeking a position as a Physical Design Engineer. He has experience with the full physical design flow from netlist to GDSII. He is proficient with EDA tools from Synopsys including IC Compiler, PrimeTime, and Hercules. Some of his skills include macro placement, timing analysis, power reduction techniques, Verilog coding, and scripting with Tcl. He has a Master's degree in VLSI System Design from JNTUH and is looking to apply his 5+ years of industry experience at a new company.
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Srinivas Kotha
Srinivas Kotha is seeking a position as a Physical Design Engineer. He has a master's degree in VLSI System Design and experience implementing physical design projects including block-level layout of a torpedo subsystem and timing analysis using synthesis tools. His skills include Verilog, physical design flows, timing closure, and Tcl scripting. He completed projects in image compression, FPGA memory testing, and physical design challenges like power planning and DRC/LVS fixes.
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Srinivas Kotha is seeking a position as a Physical Design Engineer. He has a master's degree in VLSI System Design and experience implementing physical design projects including block-level layout of a torpedo subsystem and timing analysis using synthesis tools. His skills include Verilog, physical design flows, timing closure, and Tcl scripting. He completed projects in image compression, FPGA memory testing, and physical design challenges like power planning and DRC/LVS fixes.
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1 unit- PPT - SS22-23.pptx
This document provides information about a Microprocessors and Microcontrollers course offered by the Department of Computer Science and Engineering. The course aims to provide students with knowledge of microprocessors and microcontrollers to solve real-world problems efficiently. The course emphasizes architecture, programming, and system design used in various everyday devices. It is a 2-credit course offered in the winter semester. Topics covered include the 8086 microprocessor, 8051 architecture, peripheral devices, and advanced processors.
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Srinivas_Kotha_CV
- 1. SRINIVAS KOTHA Email id: ksrinivasvlsi@gmail.com Mobile Number: 8123419352 Career Objective: Looking for an opportunity to work as a Physical Design Engineer in dynamic work environment. Core Competency: Well versed with Netlist - GDS II flow. Efficient in high count Macro placement during Floor-planning. Good at Timing Analysis and resolving violations for various timing paths. Basic knowledge of Power reduction techniques. Exposure to Technology by taking additional training in Physical Design with Hands on Project. Good understanding of MOS Transistor fundamentals. Good knowledge of Digital Design concepts. Good knowledge of Verilog RTL coding. Good in scripting with Tcl to handle various requirements of design. Good working knowledge of Linux Operating System. Education : Degree Discipline Institute University Year of Passing Aggregate PG Diploma Advanced Diploma in ASIC Design RV-VLSI Design Center 2015 M.Tech VLSI-System Design Aurora's Technological Research Institute JNTUH 2013 72.56 % B.Tech Electronics & Communication Sree Chaitanya College Of Engineering JNTUH 2009 68.23 % 12th MPC Loyola Junior College BIE 2005 82.40 % 10th Loyola High School BSE 2003 82.00 %
- 2. Project Details: Title: Timing Analysis with OCV Role: Timing Analysis, Identification of causes for violation and resolving violations. Organization: Duration of Project in Months: RV-VLSI Design Center 1 Month Description: 1. Generation and analysis of Timing reports for different designs in various scenarios with MCMM. 2. Analysis of CRPR. 3. Understanding the effect of clock uncertainity on timing. 4. Understanding various techniques to fix violations. Tools Used : Synopsys Prime Time Deliverable/Challenges Faced: 1. Dealing with false paths and multi-cycle paths. 2. Analysis of Latch based designs. 3. Analysis of Timing with Clock Domain Crossing (CDC). 4. Analysis of Signal Integrity/Cross Talk. Title: Scripting with Tcl Role: Writing, analysis and debug of various Tcl scripts. Organization: RV-VLSI Design Center Duration of Project in Months: ½ Month Description: Writing Tcl scripts to various design examples. Extracting information from IC Compiler data base. Analysis of tool template Tcl scripts of Floor plan, Power plan, Placement, CTS, Routing and customized them to the flow. Tools Used : Tclsh, TCL-tutor, Synopsys IC Compiler Deliverable/Challenges Faced: Writing Tcl to design examples. Title Netlist to GDS II of Torpedo Sub-system Role: Responsible for Floor-Planning, Power Planning, Placement, CTS, Routing, Physical verification, Chip finish and Analysis of timing. Organization: RV-VLSI Design Center Duration of Project in Months: 4½ Months Description: Block level Physical Design of Torpedo consisting of a Macro Count of 32 and a Standard Cell Count of 43k with a Supply Voltage of 1.8V, operating on a Clock Frequency of 400 MHz incorporated with 5 Clocks. DFT is inserted. Technology Node: 180 nm Tools Used : IC Compiler for APR, PrimeTime for STA, Hercules and Calibre for DRC/LVS.
- 3. Deliverable/Challen ges Faced: 1. Placement of macros with congestion free Floor planning 2. Power Planning to get IR drop ( VDD + VSS ) less than 5% of 1.8V 3. Fixing timing violations after each stage 4. Fixing hold violations after CTS 5. Identifying useful skew and fixing the violations 6. Fixing Antenna Violations and DRC/LVS Errors Personal Profile: Name : Srinivas Kotha Date of Birth : 1 Dec 1987 Address : #1239, 26th Main, 32 G'Cross, Near Sudarshan Vidya Mandir, Jayanagar 4 T Block, Bangalore – 560041 Father Name : Rajaiah Nationality : Indian Sex : Male Languages known : English, Hindi, Telugu