This document discusses several types of memory technologies: - DDR-DRAM can transfer data on both the rising and falling edges of a clock cycle, allowing it to transfer two data words per cycle. - SDRAM interfaces with the system bus synchronously using a clock signal, allowing it to operate faster than asynchronous DRAM. - FCRAM aims to reduce latency and increase bandwidth through architectural enhancements like three-stage row pipelining and fast access cores. - QDR-DRAM can transfer up to four words per clock cycle by using two clocks, one each for read and write data.

1. Memory Technologies
Wijayarathna D.G.C.D. 100596F
DDR-DRAM
When we consider the RAM, there are two major types of
RAMs, Static RAM (SRAM) and Dynamic RAM(DRAM).
Static RAM is developed using transistors and DRAM is
developed using capacitors. Since DRAM is developed using
capacitors, they are slower in speed, but cheap than SRAM
and consume low power. DRAM is using in main memory of a
computer and SRAM in registers and cache.
RAM is working according to a clock like a flip-flop. It
transfers its commands, addresses, and data on the rising edge
of the clock.
But DDR-DRAM transfers data not only in the rising edge of
the clock, but also in the falling edge of the clock cycle. S
DDR can transfer two data words per clock cycle.
DDR-SDRAM
SDRAM(Synchronous Dynamic Random Access Memory) is
dynamic random access memory (DRAM) that is synchronized
with the system bus.Classic DRAM has an asynchronous
interface, which means that it responds as quickly as possible
to changes in control inputs. SDRAM has a synchronous
interface, meaning that it waits for a clock signal before
responding to control inputs and is therefore synchronized
with the computer's system bus. The clock is used to drive an
internal finite state machine that pipelines incoming

2. instructions. This allows the chip to have a more complex
pattern of operation than an asynchronous DRAM, enabling
higher speeds.
FCRAM
FCRAM (Fast Cycle RAM) is a new technology that
approaches the problem of DRAM/Processor speed in a
different way. With the improvements in CPU speeds over the
last few years, designers have looked for a solution that would
get them over the ever present problem of relative slower
memory.Specifically, this memory technology was developed
to reduce random cycle latency (random access and cycle
times) while increasing peak bandwidth.FCRAM achieves this
by implementing several architectural enhancements including:
1. Three-stage row pipelining
2. Fast access core
3. Simplified DDR feature set
4. Fast bus turnaround times
FPM-DRAM
FPM DRAM (Fast Page Mode DRAM) is a common kind of
DRAM in personal computers. Page mode DRAM essentially
accesses a row of RAM without having to continually
respecify the row. A row access strobe (RAS) signal is kept
active while the column access strobe (CAS) signal changes to
read a sequence of contiguous memory cells. This reduces
access time and lowers power requirements. Clock timings for
FPM DRAM are typically 6-3-3-3 (meaning 3 clock cycles for
access setup, and 3 clock cycles for the first and each of three
successive accesses based on the initial setup).

3. QDR-DRAM
Quad Data Rate (QDR) DRAM can transfer up to four words
of data in each clock cycle.Like Double Data-Rate (DDR)
DRAM, QDR DRAM transfers data on both rising and falling
edges of the clock signal.QDR DRAM uses two clocks, one
for read data and one for write data and has separate read and
write data buses (also known as Separate I/O), whereas DDR
DRAM uses a single clock and has a single common data bus
used for both reads and writes (also known as Common I/O).
QDR-SRAM
This is a Static RAM which has the same QDR features as the
QDR DRAM.
SDRAM
This is a Dynamic RAM, which uses capacitors as described in
DDR-DRAM. This has synchronized with a system bus. It
waits for a clock signal before responding to control inputs and
is therefore synchronized with the computer's system bus.
SSRAM
This is Static RAM which has the same features as SDRAM.
ZBT-SRAM
The ZBT memories are synchronous: they require a clock
input, and their inputs are only sampled on the rising edges of
that clock.They are also pipelined, with the data bus being
delayed by two cycles after the address and control signals. In
other words, if a read cycle is initiated on clock cycle n, then
the data read from that address will be available on cycle n+2.

4. Similarly, for a write cycle, the data to be written is supplied
on cycle n+2.
RDRAM
RDRAM (Rambus Dynamic Random Access Memory) is a
memory subsystem that promises to transfer up to 1.6 billion
bytes per second. The subsystem consists of the random access
memory (RAM), the RAM controller, and the bus (path)
connecting RAM to the microprocessor and devices in the
computer that use it.Direct Rambus (DRDRAM) is the latest
version and is expected to help accelerate the growth of
visually intensive interfaces such as 3-D,interactive games,
and streaming multimedia.
RLDRAM
RLDRAM memory is a low-latency, high-bandwidth DRAM
that's designed for demanding networking tasks and L3 cache,
as well as other applications that require back-to-back
READ/WRITE operations or completely random access.