This document is a presentation on RAM that was presented by Tipu Sultan and Md Shakhawat Hossain Sujon to Tafisr Ahmed Khan. It summarizes the key differences between SRAM and DRAM. SRAM does not require refresh cycles but is more expensive and slower than DRAM. A typical SRAM cell uses 6 transistors arranged in two cross-coupled inverters, while a DRAM cell uses one transistor and one capacitor. DRAM must perform periodic refresh cycles to maintain its data due to capacitor leakage, whereas SRAM maintains its data statically without refresh.

1. Welcome
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2. A Presentation on Ram
Presented by
 Tipu Sultan
 Roll:04
 Batch: 17th
 Md Shakhawat Hossain Sujon
 Roll: 02
 Batch: 17th
Presented to
 TAFSIR AHMED KHAN
 LECTURER
 DEPARTMENT OF EETE
 DHAKA INTERNATIONAL UNIVERSITY
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3. Random Access Memory (RAM)
Static RAM
Dynamic RAM
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4. SRAM
 Hold data without external refresh
 Simplicity : don’t require external refresh circuitry
 Speed: SRAM is faster than DRAM
 Cost: several times more expensive than DRAMs
 Size: take up much more space than DRAMs
 Power: consume more power than DRAMs
 Usage: level 1 or level 2 cache
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5. Design Of SRAM
 A typical SRAM cell is made up of six
MOSFETs. Each bit in an SRAM is
stored on four transistors (M1, M2, M3,
M4) that form two cross-coupled
inverters.
 This storage cell has two stable states
which are used to denote 0 and 1.
 Two additional access transistors serve
to control the access to a storage cell
during read and write operations.
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6. SRAM – Write/Read Operation
 For WRITE
Operation-
 Data =1
 Datab =0
 Select =1
 For READ Operation-
 Data =1
 Datab =1 (forcefully)
 Select =1
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7. Reading operation
 Assume that the content of memory is 1 stored at Q. The read cycle
is started by precharging both the bit lines to a logic 1,
 The word line WL, enabling M5 AND M6 .
 The second step occurs when the value stored in Q & Q’ are
transferred to the bit line by leaving BL at its precharged value and
discharging BL’ through M1 and M5 to a logical 0
 On the BL side, the transistors M4 and M6 pull the bit line toward VDD,
a logical 1 (M4 as it is turned on because Q’ is logically set to 0).
 Bit lines reach a sense amplifier, which will sense which line has
higher voltage and thus will tell whether there was 1 stored or 0. The
higher the sensitivity of sense amplifier, the faster the speed of read
operation is.
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8. SRAM – Row Selection (2x2)
 - Simple inverted input used to select
between 2 rows
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9. SRAM – Row Selection (4x4)
A B R0 R1 R2 R3
0 0 1 0 0 0
0 1 0 1 0 0
1 0 0 0 1 0
1 1 0 0 0 1
- A decoder designed to satisfy row
selection for a 4x4 SRAM matrix
- Any one output is high at one time,
selecting a particular row of SRAM
cells
- A 3 input decoder required for more
than 4 rows (5-8)
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10. Timing Diagram
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11. SRAM example:
Samsung 1Mx4 High-speed CMOS SRAM
 Fast access time:
8, 10ns (Max)
 Low power
dissipation
 Stanby: 5mA
(max)
 Operating: 80 mA
(8 ns), 65mA
(10ns)
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12. Schematic Diagram
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13. DRAM
Dynamic Random Access Memory
 Basic storage device is not a flip flop but a MOS and a capacitor
 Charge determine the stored bit (0,1)
 Data stored as a charge not remain infinitely due to leakage current,
therefore periodic refresh cycle is required to maintain stored data.
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14. OPERATION
VDD
O/P
CT1
T3
I/P
A
 When A= 1 T1 will be ON then
capacitor charges to I/P value during
interval A=1
When T1 is OFF the invertor will
remember the sample data because of
stored charge on capacitor.
Charge on capacitor eventually leak
OFF. Because of leakage through
insulation which supports the gate on
T2.
 To larger extent it is due to leakage
through reverse biased junction formed
b/w sub. And drain of T1. 4/5/2017 14

15. 4 Transistor DRAM cell
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16.  Capacitor C1 AND C2 become accessible to data terminal
when gate T7, T8 , T5 AND T6 are made to conduct by
making X=Y=1
 When Vg > Vt(T1), T1 is ON and correspondingly capacitor
has no charge and T2 is OFF.
 If any operation is not performed for a long time the charge
of capacitor is lost due to leakage therefore refreshing is
needed.
 Refreshing is done be brief access from Vdd to cell this is
done by making T11 and T22 ON.
 Suppose initially T1 is ON and T2 is OFF, refresh is applied
through T12, T6 and C1 charges to previous value.
 note that since T2 is OFF all current goes to C1 allowing it
to replenish any charge due to leakage.
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17. SRAM DRAM
1. Data Volatility Y Y
2. Data refresh Operation N required
3. Cell structure 6T 1T-1C
4. Power consumption high/low high
5. Read Speed (latency) ~10/70 ns ~50ns
6. Write Speed ~5/40ns ~40ns
7. Cost high low
8. Power supply single single
9. Application ex. Cache Memory Main
Memory
Comparison between SRAM and DRAM
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18. Thank you
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