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Unit II Arm 7 Introduction

This document provides an introduction to the ARM-7 microprocessor architecture. It describes key features of the ARM7TDMI including its 32-bit RISC instruction set, 3-stage pipeline, 37 registers including separate registers for different processor modes, and low power consumption. The document also compares RISC and CISC architectures and summarizes the different versions of the ARM architecture.

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1 Introduction to ARM-7 The first encounter Dr. P. H. Zope Assistant Professor SSBT’s COET Bambhori Jalgaon North Maharashtra University Jalgaon India phzope@gmail.com 9860631040
2 What Is ARM? • Advanced RISC Machine • First RISC microprocessor for commercial use • Market-leader for low-power and cost- sensitive embedded applications
ARM7TDMI TDMI = (?) – Thumb instruction set – Debug-interface (JTAG/ICEBreaker) – Multiplier (hardware) – Interrupt (fast interrupts)
•32/16-bit RISC architecture ( ARM v4T ) •32-bit ARM instruction set for maximum performance and flexibility •16-bit Thumb instruction set for increased code density •Unified bus interface, 32-bit data bus carries both instructions and data •8-, 16-, and 32-bit Data Types •Three-stage pipeline •4GBytes Linear Address Space •32-bit ALU and high-performance multiplier •37 piece of 32 bit register •Very small die size and low power consumption •Fully static operation •Coprocessor interface •Extensive debug facilities: Embedded ICE-RT real-time debug unit. On-chip JTAG interface unit. •Interface for direct connection to Embedded Trace Macro cell (ETM). ARM7/ARM9 Architecture Feature Highlights
•Pipelined (ARM7: 3 stages) • Cached (depending on the implementation) • Von Neuman-type bus structure (ARM7), Harvard (ARM9) •7 modes of operation (usr, fiq, irq, svc, abt, sys, und) • Simple structure -> reasonably good speed / power consumption ratio •Very Low Power Consumption: Industry-leader in MIPS/Watt.
Differences between RISC and CISC CISC RISC Variable size instructions with many formats Fixed size instructions (32 bit)with few formats Multi clock complex instructions. Single clock reduced instructions. Memory to memory load andstore instructions Register to register load andstore Small code size, high cycles per second. Large code size, Low cycles per second. Emphasis on hardware Emphasis on software Increased hardware cost. Reduced hardware cost.
7 ARM Powered Products
8 Pipeline Organization • Increases speed – most instructions executed in single cycle • Versions: – 3-stage (ARM7TDMI and earlier) – 5-stage (ARMS, ARM9TDMI) – 6-stage (ARM10TDMI)
ARM7 Pipeline Model  ARM7  standard 3-stage pipelined architecture FETCH DECODE EXECUTE  Fetch Instruction  Select/Increment PC  Read next instruction  Related Blocks  Address Selector  Address Incrementer  Address Register  Decode Instruction  Generate Ctrl. signals  Generate immediate  Read from register file  Related Blocks  Control Logic (Decoder)  Register File  Execute Instruction  Arithmetic / Logic  Calc. branch addr.  Load / Store  Related Blocks  Shifter  Multiplier  ALU *Register write back (WB) is hidden
10 Pipeline Organization • 3-stage pipeline: Fetch – Decode - Execute • Three-cycle latency, one instruction per cycle throughput cycle Fetch Decode Execute Fetch Decode Execute Fetch Decode Execute i n s t r u c t i o n t t+1 t+2 t+3 t+4 i i+1 i+2
11 Pipeline Organization • 5-stage pipeline: Reduces work per cycle => allows higher clock frequency Separates data and instruction memory => reduction of CPI (average number of clock Cycles Per Instruction) Stages: Write-back Buffer/data Execute Decode Fetch
12 Pipeline Organization • Pipeline flushed and refilled on branch, causing execution to slow down • Special features in instruction set eliminate small jumps in code to obtain the best flow through pipeline
ARM-7 Architecture
14 ARM Architecture Version Summary Core Version Feature ARM1 v1 26 bit address ARM2, ARM2as, ARM3 v2 32 bit multiply coprocessor ARM6, ARM60, ARM610, ARM7, ARM710, ARM7D, ARM7DI v3 32 bit addresses Separate PC and PSRs Undefined instruction and Abort modes Fully static Big or little endian StrongARM, SA-110, SA-1100 ARM8, ARM810 v4 Half word and signed halfword/byte support Enhanced multiplier System mode ARM7TDMI, ARM710T, ARM720T, ARM740T ARM9TDMI, ARM920T, ARM940T v4T Thumb instruction set T: Thumb instruction set M: enhanced Multiplier D: On-chip Debug I: Embedded ICE Logic
15 ARM Architecture Version Summary (cont.)Core Version Feature ARM1020T v5T Improved ARM/Thumb Interworking CLZ instruction for improved division ARM9E-S, ARM10TDMI, ARM1020E v5TE Extended multiplication and saturated maths for DSP-like functionality ARM7EJ-S, ARM926EJ-S, ARM1026EJ-S v5TEJ Jazelle Technology for Java acceleration ARM11, ARM1136J-S, v6 Low power needed SIMD (Single Instruction Multiple Data) media processing extensions J: Jazelle S: Synthesizable F: integral vector floating point unit E: Enhanced DSP instruction
ARM7 Datapath Overview multiply data out register instruction decode & control incrementer register bank address register barrel shifter A[31:0] D[31:0] data in register ALU control P C PC A L U b u s A b u s B b u s register FETCH DECODE EXECUTE (WB) *Pipeline registers are omitted
18 ARM7TDMI Interface Signals (1/4) mreq seq lock Dout[31:0] D[31:0] r/w mas[1:0] mode[4:0] trans abort opc cpi cpa cpb memory interface MMU interface coprocessor interface mclk wait eclk isy nc bigend enin irq ¼q reset enout abe Vdd Vss clock control configuration interrupts initialization bus control power ale ape dbe dbgrq breakpt dbgack debug exec extern1 extern0 dbgen bl[3:0] TRST TCK TMS TDI JTAG controls TDO Tbit st atetbe rangeout0 rangeout1 dbgrqi commrx commtx enouti highz busdis ecapclk busen Din[31:0] A[31:0] ARM7TDMI core tapsm[3:0] ir[3:0] tdoen tck1 tck2 screg[3:0] TAP information driv ebs ecapclkbs icapclkbs highz pclkbs rstclkbs sdinbs sdoutbs shclkbs shclk2bs boundary scan extension
19TM 1939v10 The ARM Architecture Processor Modes  The ARM has seven basic operating modes: 1. User : unprivileged mode under which most tasks run 2. FIQ : entered when a high priority (fast) interrupt is raised 3. IRQ : entered when a low priority (normal) interrupt is raised 4. Supervisor : entered on reset and when a Software Interrupt 5. instruction is executed 6. Abort : used to handle memory access violations 7. Undef : used to handle undefined instructions 8. System : privileged mode using the same registers as user mode
20TM 2039v10 The ARM Architecture r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc) cpsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r8 r9 r10 r11 r12 r13 (sp) r14 (lr) spsr FIQ IRQ SVC Undef Abort User Mode r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc) cpsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r8 r9 r10 r11 r12 r13 (sp) r14 (lr) spsr Current Visible Registers Banked out Registers FIQ IRQ SVC Undef Abort r0 r1 r2 r3 r4 r5 r6 r7 r15 (pc) cpsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r8 r9 r10 r11 r12 r13 (sp) r14 (lr) spsr Current Visible Registers Banked out Registers User IRQ SVC Undef Abort r8 r9 r10 r11 r12 r13 (sp) r14 (lr) FIQ ModeIRQ Mode r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r15 (pc) cpsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r8 r9 r10 r11 r12 r13 (sp) r14 (lr) spsr Current Visible Registers Banked out Registers User FIQ SVC Undef Abort r13 (sp) r14 (lr) Undef Mode r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r15 (pc) cpsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r8 r9 r10 r11 r12 r13 (sp) r14 (lr) spsr Current Visible Registers Banked out Registers User FIQ IRQ SVC Abort r13 (sp) r14 (lr) SVC Mode r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r15 (pc) cpsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r8 r9 r10 r11 r12 r13 (sp) r14 (lr) spsr Current Visible Registers Banked out Registers User FIQ IRQ Undef Abort r13 (sp) r14 (lr) Abort Mode r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r15 (pc) cpsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r8 r9 r10 r11 r12 r13 (sp) r14 (lr) spsr Current Visible Registers Banked out Registers User FIQ IRQ SVC Undef r13 (sp) r14 (lr) The ARM Register Set
21TM 2139v10 The ARM Architecture Register Organization Summary User mode r0-r7, r15, and cpsr r8 r9 r10 r11 r12 r13 (sp) r14 (lr) spsr FIQ r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc) cpsr r0 r1 r2 r3 r4 r5 r6 r7 User r13 (sp) r14 (lr) spsr IRQ User mode r0-r12, r15, and cpsr r13 (sp) r14 (lr) spsr Undef User mode r0-r12, r15, and cpsr r13 (sp) r14 (lr) spsr SVC User mode r0-r12, r15, and cpsr r13 (sp) r14 (lr) spsr Abort User mode r0-r12, r15, and cpsr Thumbstate Low registers Thumbstate Highregisters Note: System mode uses the User mode register set
22TM 2239v10 The ARM Architecture The Registers  ARM has 37 registers all of which are 32-bits long.  1 dedicated program counter  1 dedicated current program status register  5 dedicated saved program status registers  30 general purpose registers  The current processor mode governs which of several banks is accessible. Each mode can access  a particular set of r0-r12 registers  a particular r13 (the stack pointer, sp) and r14 (the link register, lr)  the program counter, r15 (pc)  the current program status register, cpsr Privileged modes (except System) can also access  a particular spsr (saved program status register)
23TM 2339v10 The ARM Architecture Current Program Status Registers  Condition code flags  N = Negative result from ALU  Z = Zero result from ALU  C = ALU operation Carried out  V = ALU operation oVerflowed  Sticky Overflow flag - Q flag  Architecture 5TE/J only  Indicates if saturation has occurred  J bit  Architecture 5TEJ only  J = 1: Processor in Jazelle state  Interrupt Disable bits.  I = 1: Disables the IRQ.  F = 1: Disables the FIQ.  T Bit  Architecture xT only  T = 0: Processor in ARM state  T = 1: Processor in Thumb state  Mode bits  Specify the processor mode 2731 N Z C V Q 28 67 I F T mode 1623 815 5 4 024 f s x c U n d e f i n e dJ
24TM 2439v10 The ARM Architecture  When the processor is executing in ARM state:  All instructions are 32 bits wide  All instructions must be word aligned  Therefore the pc value is stored in bits [31:2] with bits [1:0] undefined (as instruction cannot be halfword or byte aligned).  When the processor is executing in Thumb state:  All instructions are 16 bits wide  All instructions must be halfword aligned  Therefore the pc value is stored in bits [31:1] with bit [0] undefined (as instruction cannot be byte aligned).  When the processor is executing in Jazelle state:  All instructions are 8 bits wide  Processor performs a word access to read 4 instructions at once Program Counter (r15)
25 Saved Program Status Register (SPSR) Each privileged mode (except system mode) has associated with it a SPSR This SPSR is used to save the state of CPSR when the privileged mode is entered in order that the user state can be fully restored when the user process is resumed Often the SPSR may be untouched from the time the privileged mode is entered to the time it is used to restore the CPSR If the privileged supervisor calls to itself the SPSR must be copied into a general register and saved
27 What is Exceptions  Exceptions are usually used to handle unexpected events which arise during the execution of a program, such as interrupts or memory faults, also cover software interrupts, undefined instruction traps, and the system reset  Three groups:  Exceptions generated as the direct effect of executing an instruction  Software interrupts, undefined instructions, and prefetch abort  Exceptions generated as a side effect of an instruction  Data aborts  Exceptions generated externally  Reset, IRQ and FIQ
28 Exception Entry  When an exception arises  ARM completes the current instruction as best it can (except that reset exception)  handle the exception which starts from a specific location (exception vector).  Processor performs the following sequence:  Change to the operating mode corresponding to the particular exception  Stores the return address in LR_<mode>  Copy old CPSR into SPSR_<mode>  Set appropriate CPSR bits  If core currently in Thumb state then ARM state is entered.  Disable IRQs by setting bit 7  If the exception is a fast interrupt, disable further faster interrupt by setting bit 6 of the CPSR
29 Exception Entry  Force PC to relevant vector address  Normally the vector address contains a branch to the relevant routine  Exception handler use r13_<mode> and r14_<mode> to hold the stack point and return address Priority Exception Mode vector address 1 Reset SVC 0x00000000 2 Data abort (data access memory fault) Abort 0x00000010 3 FIQ (fast interrupt ) FIQ 0x0000001C 4 IRQ (normal interrupt) IRQ 0x00000018 5 Prefetch abort (instruction fetch memory fault) Abort 0c0000000C 6 Undefined instruction UND 0x00000004 Software interrupt (SWI) SVC 0x00000008
30 Exception Return  Once the exception has been handled, the user task is normally resumed  The sequence is  Any modified user registers must be restored from the handler’s stack  CPSR must be restored from the appropriate SPSR  PC must be changed back to the relevant instruction address  The last two steps happen atomically as part of a single instruction
Exceptions of ARM-7  Mode changes can be made under  Software control  External interrupts  Exception process  The modes other than user mode are privileged modes  Have full access to system resources  Can change mode freely  Exception modes  FIQ  IRQ  Supervisor mode  Abort: data abort and instruction prefetch abort  Undefined
Exception Task flow Class Cause Interrupt External stimulus Fault Internal cause Trap Trap instruction
Exception (cont’d) ARM7 (ISA v4) Exceptions Type Class Description (Cause) Reset Power Up Undefined Instruction FAULT Invalid / coprocessor instruction Prefetch Abort FAULT TLB miss for instruction Data Abort FAULT TLB miss for data access IRQ INTERRUPT Normal interrupt FIQ INTERRUPT Fast Interrupt (no context switch) SW Interrupt TRAP Undefined / coprocessor instruction
Exception (cont’d) ARM7 (ISA v4) Exception Vectors Exception Address Mode on Entry Reset 0x00000000 Supervisor Undefined Instruction 0x00000004 Undefined SW Interrupt 0x00000008 Supervisor Prefetch Abort 0x0000000C Abort Data Abort 0x00000010 Abort IRQ 0x00000018 IRQ FIQ 0x0000001C FIQ Reserved 0x00000014 Reserved
Vector Table Exception Handling  When an exception occurs, the ARM:  Copies CPSR into SPSR_<mode>  Sets appropriate CPSR bits  Change to ARM state  Change to exception mode  Disable interrupts (if appropriate)  Stores the return address in LR_<mode>  Sets PC to vector address  To return, exception handler needs to:  Restore CPSR from SPSR_<mode>  Restore PC from LR_<mode> This can only be done in ARM state. Vector table can be at 0xFFFF0000 on ARM720T and on ARM9/10 family devices FIQ IRQ (Reserved) Data Abort Prefetch Abort Software Interrupt Undefined Instruction Reset 0x1C 0x18 0x14 0x10 0x0C 0x08 0x04 0x00
• Current Program Status Register (CPSR) • Saved Program Status Register (SPSR) • On exception, entering mod mode: – (PC + 4)  LR – CPSR  SPSR_mod – PC  IV address – R13, R14 replaced by R13_mod, R14_mod – In case of FIQ mode R7 – R12 also replaced Exception (cont’d) Process
Exception priorities When multiple exceptions arise at the same time, a fixed priority system determines the order in which they are handled: Highest priority: 1. Reset 2. Data abort 3. FIQ 4. IRQ 5. Prefetch abort Lowest priority: 6. Undefined Instruction, Software interrupt.
There are two ways to store data in memory 1 Little-Endian 2 Big – Endian Memory Organization
Memory Organization • Word, half-word alignment (xxxx00 or xxxxx0) • ARM can be set up to access data in either little-endian or big- endian format, through they default to little-endian.
Big-endian The most significant byte (MSB) value, which is 0Ah in our example, is stored at the memory location with the lowest address, the next byte value in significance, 0Bh, is stored at the following memory location and so on. This is akin to Left-to- Right reading in hexadecimal order.
Little-endian The least significant byte (LSB) value, 0Dh, is at the lowest address. The other bytes follow in increasing order of significance
Advanced Microprocessor Bus Architecture (AMBA)
AHB The AMBA AHB is for high performance, high clock frequency system modules. It acts as a high performance system backbone that is capable for doing burst transfer, connecting the CPU and to on chip and off chip memories. ASB AMBA ASB is an alternative system bus suitable for use where the high performance features of AHB are not required. ASB also supports the efficient connection of CPU, on chip memory and off chip memories. APB AMBA APB is for low-power peripherals. It is optimized for minimal power consumption and reduced interface complexity to support peripheral functions. APB is connected to CPU via AHB/ASB-APB bridge. Advanced Microprocessor Bus Architecture
5-Stage Pipeline ARM Organization
5-Stage Pipeline Organization (1/2) • Fetch – The instruction is fetched from memory and placed in the instruction pipeline • Decode – The instruction is decoded and register operands read from the register files. There are 3 operand read ports in the register file so most ARM instructions can source all their operands in one cycle • Execute – An operand is shifted and the ALU result generated. If the instruction is a load or store, the memory address is computed in the ALU I-cache rot/sgn ex +4 byte repl. ALU I decode register read D-cache fetch instruction decode execute buffer/ data write-back forwarding paths immediate fields next pc reg shift load/store address LDR pc SUBS pc post- index pre-index LDM/ STM register write r15 pc + 8 pc + 4 +4 mux shift mul B, BL MOV pc
5-Stage Pipeline Organization (2/2) • Buffer/Data – Data memory is accessed if required. Otherwise the ALU result is simply buffered for one cycle • Write back – The result generated by the instruction are written back to the register file, including any data loaded from memory I-cache rot/sgn ex +4 byte repl. ALU I decode register read D-cache fetch instruction decode execute buffer/ data write-back forwarding paths immediate fields next pc reg shift load/store address LDR pc SUBS pc post- index pre-index LDM/ STM register write r15 pc + 8 pc + 4 +4 mux shift mul B, BL MOV pc

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Unit II Arm 7 Introduction

  • 1.
    1 Introduction to ARM-7 Thefirst encounter Dr. P. H. Zope Assistant Professor SSBT’s COET Bambhori Jalgaon North Maharashtra University Jalgaon India phzope@gmail.com 9860631040
  • 2.
    2 What Is ARM? •Advanced RISC Machine • First RISC microprocessor for commercial use • Market-leader for low-power and cost- sensitive embedded applications
  • 3.
    ARM7TDMI TDMI = (?) –Thumb instruction set – Debug-interface (JTAG/ICEBreaker) – Multiplier (hardware) – Interrupt (fast interrupts)
  • 4.
    •32/16-bit RISC architecture( ARM v4T ) •32-bit ARM instruction set for maximum performance and flexibility •16-bit Thumb instruction set for increased code density •Unified bus interface, 32-bit data bus carries both instructions and data •8-, 16-, and 32-bit Data Types •Three-stage pipeline •4GBytes Linear Address Space •32-bit ALU and high-performance multiplier •37 piece of 32 bit register •Very small die size and low power consumption •Fully static operation •Coprocessor interface •Extensive debug facilities: Embedded ICE-RT real-time debug unit. On-chip JTAG interface unit. •Interface for direct connection to Embedded Trace Macro cell (ETM). ARM7/ARM9 Architecture Feature Highlights
  • 5.
    •Pipelined (ARM7: 3stages) • Cached (depending on the implementation) • Von Neuman-type bus structure (ARM7), Harvard (ARM9) •7 modes of operation (usr, fiq, irq, svc, abt, sys, und) • Simple structure -> reasonably good speed / power consumption ratio •Very Low Power Consumption: Industry-leader in MIPS/Watt.
  • 6.
    Differences between RISCand CISC CISC RISC Variable size instructions with many formats Fixed size instructions (32 bit)with few formats Multi clock complex instructions. Single clock reduced instructions. Memory to memory load andstore instructions Register to register load andstore Small code size, high cycles per second. Large code size, Low cycles per second. Emphasis on hardware Emphasis on software Increased hardware cost. Reduced hardware cost.
  • 7.
  • 8.
    8 Pipeline Organization • Increasesspeed – most instructions executed in single cycle • Versions: – 3-stage (ARM7TDMI and earlier) – 5-stage (ARMS, ARM9TDMI) – 6-stage (ARM10TDMI)
  • 9.
    ARM7 Pipeline Model ARM7  standard 3-stage pipelined architecture FETCH DECODE EXECUTE  Fetch Instruction  Select/Increment PC  Read next instruction  Related Blocks  Address Selector  Address Incrementer  Address Register  Decode Instruction  Generate Ctrl. signals  Generate immediate  Read from register file  Related Blocks  Control Logic (Decoder)  Register File  Execute Instruction  Arithmetic / Logic  Calc. branch addr.  Load / Store  Related Blocks  Shifter  Multiplier  ALU *Register write back (WB) is hidden
  • 10.
    10 Pipeline Organization • 3-stagepipeline: Fetch – Decode - Execute • Three-cycle latency, one instruction per cycle throughput cycle Fetch Decode Execute Fetch Decode Execute Fetch Decode Execute i n s t r u c t i o n t t+1 t+2 t+3 t+4 i i+1 i+2
  • 11.
    11 Pipeline Organization • 5-stagepipeline: Reduces work per cycle => allows higher clock frequency Separates data and instruction memory => reduction of CPI (average number of clock Cycles Per Instruction) Stages: Write-back Buffer/data Execute Decode Fetch
  • 12.
    12 Pipeline Organization • Pipelineflushed and refilled on branch, causing execution to slow down • Special features in instruction set eliminate small jumps in code to obtain the best flow through pipeline
  • 13.
  • 14.
    14 ARM Architecture VersionSummary Core Version Feature ARM1 v1 26 bit address ARM2, ARM2as, ARM3 v2 32 bit multiply coprocessor ARM6, ARM60, ARM610, ARM7, ARM710, ARM7D, ARM7DI v3 32 bit addresses Separate PC and PSRs Undefined instruction and Abort modes Fully static Big or little endian StrongARM, SA-110, SA-1100 ARM8, ARM810 v4 Half word and signed halfword/byte support Enhanced multiplier System mode ARM7TDMI, ARM710T, ARM720T, ARM740T ARM9TDMI, ARM920T, ARM940T v4T Thumb instruction set T: Thumb instruction set M: enhanced Multiplier D: On-chip Debug I: Embedded ICE Logic
  • 15.
    15 ARM Architecture Version Summary(cont.)Core Version Feature ARM1020T v5T Improved ARM/Thumb Interworking CLZ instruction for improved division ARM9E-S, ARM10TDMI, ARM1020E v5TE Extended multiplication and saturated maths for DSP-like functionality ARM7EJ-S, ARM926EJ-S, ARM1026EJ-S v5TEJ Jazelle Technology for Java acceleration ARM11, ARM1136J-S, v6 Low power needed SIMD (Single Instruction Multiple Data) media processing extensions J: Jazelle S: Synthesizable F: integral vector floating point unit E: Enhanced DSP instruction
  • 17.
    ARM7 Datapath Overview multiply dataout register instruction decode & control incrementer register bank address register barrel shifter A[31:0] D[31:0] data in register ALU control P C PC A L U b u s A b u s B b u s register FETCH DECODE EXECUTE (WB) *Pipeline registers are omitted
  • 18.
    18 ARM7TDMI Interface Signals(1/4) mreq seq lock Dout[31:0] D[31:0] r/w mas[1:0] mode[4:0] trans abort opc cpi cpa cpb memory interface MMU interface coprocessor interface mclk wait eclk isy nc bigend enin irq ¼q reset enout abe Vdd Vss clock control configuration interrupts initialization bus control power ale ape dbe dbgrq breakpt dbgack debug exec extern1 extern0 dbgen bl[3:0] TRST TCK TMS TDI JTAG controls TDO Tbit st atetbe rangeout0 rangeout1 dbgrqi commrx commtx enouti highz busdis ecapclk busen Din[31:0] A[31:0] ARM7TDMI core tapsm[3:0] ir[3:0] tdoen tck1 tck2 screg[3:0] TAP information driv ebs ecapclkbs icapclkbs highz pclkbs rstclkbs sdinbs sdoutbs shclkbs shclk2bs boundary scan extension
  • 19.
    19TM 1939v10 TheARM Architecture Processor Modes  The ARM has seven basic operating modes: 1. User : unprivileged mode under which most tasks run 2. FIQ : entered when a high priority (fast) interrupt is raised 3. IRQ : entered when a low priority (normal) interrupt is raised 4. Supervisor : entered on reset and when a Software Interrupt 5. instruction is executed 6. Abort : used to handle memory access violations 7. Undef : used to handle undefined instructions 8. System : privileged mode using the same registers as user mode
  • 20.
    20TM 2039v10 TheARM Architecture r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc) cpsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r8 r9 r10 r11 r12 r13 (sp) r14 (lr) spsr FIQ IRQ SVC Undef Abort User Mode r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc) cpsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r8 r9 r10 r11 r12 r13 (sp) r14 (lr) spsr Current Visible Registers Banked out Registers FIQ IRQ SVC Undef Abort r0 r1 r2 r3 r4 r5 r6 r7 r15 (pc) cpsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r8 r9 r10 r11 r12 r13 (sp) r14 (lr) spsr Current Visible Registers Banked out Registers User IRQ SVC Undef Abort r8 r9 r10 r11 r12 r13 (sp) r14 (lr) FIQ ModeIRQ Mode r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r15 (pc) cpsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r8 r9 r10 r11 r12 r13 (sp) r14 (lr) spsr Current Visible Registers Banked out Registers User FIQ SVC Undef Abort r13 (sp) r14 (lr) Undef Mode r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r15 (pc) cpsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r8 r9 r10 r11 r12 r13 (sp) r14 (lr) spsr Current Visible Registers Banked out Registers User FIQ IRQ SVC Abort r13 (sp) r14 (lr) SVC Mode r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r15 (pc) cpsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r8 r9 r10 r11 r12 r13 (sp) r14 (lr) spsr Current Visible Registers Banked out Registers User FIQ IRQ Undef Abort r13 (sp) r14 (lr) Abort Mode r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r15 (pc) cpsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r13 (sp) r14 (lr) spsr r8 r9 r10 r11 r12 r13 (sp) r14 (lr) spsr Current Visible Registers Banked out Registers User FIQ IRQ SVC Undef r13 (sp) r14 (lr) The ARM Register Set
  • 21.
    21TM 2139v10 TheARM Architecture Register Organization Summary User mode r0-r7, r15, and cpsr r8 r9 r10 r11 r12 r13 (sp) r14 (lr) spsr FIQ r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc) cpsr r0 r1 r2 r3 r4 r5 r6 r7 User r13 (sp) r14 (lr) spsr IRQ User mode r0-r12, r15, and cpsr r13 (sp) r14 (lr) spsr Undef User mode r0-r12, r15, and cpsr r13 (sp) r14 (lr) spsr SVC User mode r0-r12, r15, and cpsr r13 (sp) r14 (lr) spsr Abort User mode r0-r12, r15, and cpsr Thumbstate Low registers Thumbstate Highregisters Note: System mode uses the User mode register set
  • 22.
    22TM 2239v10 TheARM Architecture The Registers  ARM has 37 registers all of which are 32-bits long.  1 dedicated program counter  1 dedicated current program status register  5 dedicated saved program status registers  30 general purpose registers  The current processor mode governs which of several banks is accessible. Each mode can access  a particular set of r0-r12 registers  a particular r13 (the stack pointer, sp) and r14 (the link register, lr)  the program counter, r15 (pc)  the current program status register, cpsr Privileged modes (except System) can also access  a particular spsr (saved program status register)
  • 23.
    23TM 2339v10 TheARM Architecture Current Program Status Registers  Condition code flags  N = Negative result from ALU  Z = Zero result from ALU  C = ALU operation Carried out  V = ALU operation oVerflowed  Sticky Overflow flag - Q flag  Architecture 5TE/J only  Indicates if saturation has occurred  J bit  Architecture 5TEJ only  J = 1: Processor in Jazelle state  Interrupt Disable bits.  I = 1: Disables the IRQ.  F = 1: Disables the FIQ.  T Bit  Architecture xT only  T = 0: Processor in ARM state  T = 1: Processor in Thumb state  Mode bits  Specify the processor mode 2731 N Z C V Q 28 67 I F T mode 1623 815 5 4 024 f s x c U n d e f i n e dJ
  • 24.
    24TM 2439v10 TheARM Architecture  When the processor is executing in ARM state:  All instructions are 32 bits wide  All instructions must be word aligned  Therefore the pc value is stored in bits [31:2] with bits [1:0] undefined (as instruction cannot be halfword or byte aligned).  When the processor is executing in Thumb state:  All instructions are 16 bits wide  All instructions must be halfword aligned  Therefore the pc value is stored in bits [31:1] with bit [0] undefined (as instruction cannot be byte aligned).  When the processor is executing in Jazelle state:  All instructions are 8 bits wide  Processor performs a word access to read 4 instructions at once Program Counter (r15)
  • 25.
    25 Saved Program StatusRegister (SPSR) Each privileged mode (except system mode) has associated with it a SPSR This SPSR is used to save the state of CPSR when the privileged mode is entered in order that the user state can be fully restored when the user process is resumed Often the SPSR may be untouched from the time the privileged mode is entered to the time it is used to restore the CPSR If the privileged supervisor calls to itself the SPSR must be copied into a general register and saved
  • 27.
    27 What is Exceptions Exceptions are usually used to handle unexpected events which arise during the execution of a program, such as interrupts or memory faults, also cover software interrupts, undefined instruction traps, and the system reset  Three groups:  Exceptions generated as the direct effect of executing an instruction  Software interrupts, undefined instructions, and prefetch abort  Exceptions generated as a side effect of an instruction  Data aborts  Exceptions generated externally  Reset, IRQ and FIQ
  • 28.
    28 Exception Entry  Whenan exception arises  ARM completes the current instruction as best it can (except that reset exception)  handle the exception which starts from a specific location (exception vector).  Processor performs the following sequence:  Change to the operating mode corresponding to the particular exception  Stores the return address in LR_<mode>  Copy old CPSR into SPSR_<mode>  Set appropriate CPSR bits  If core currently in Thumb state then ARM state is entered.  Disable IRQs by setting bit 7  If the exception is a fast interrupt, disable further faster interrupt by setting bit 6 of the CPSR
  • 29.
    29 Exception Entry  ForcePC to relevant vector address  Normally the vector address contains a branch to the relevant routine  Exception handler use r13_<mode> and r14_<mode> to hold the stack point and return address Priority Exception Mode vector address 1 Reset SVC 0x00000000 2 Data abort (data access memory fault) Abort 0x00000010 3 FIQ (fast interrupt ) FIQ 0x0000001C 4 IRQ (normal interrupt) IRQ 0x00000018 5 Prefetch abort (instruction fetch memory fault) Abort 0c0000000C 6 Undefined instruction UND 0x00000004 Software interrupt (SWI) SVC 0x00000008
  • 30.
    30 Exception Return  Oncethe exception has been handled, the user task is normally resumed  The sequence is  Any modified user registers must be restored from the handler’s stack  CPSR must be restored from the appropriate SPSR  PC must be changed back to the relevant instruction address  The last two steps happen atomically as part of a single instruction
  • 31.
    Exceptions of ARM-7 Mode changes can be made under  Software control  External interrupts  Exception process  The modes other than user mode are privileged modes  Have full access to system resources  Can change mode freely  Exception modes  FIQ  IRQ  Supervisor mode  Abort: data abort and instruction prefetch abort  Undefined
  • 32.
    Exception Task flow Class Cause InterruptExternal stimulus Fault Internal cause Trap Trap instruction
  • 33.
    Exception (cont’d) ARM7 (ISAv4) Exceptions Type Class Description (Cause) Reset Power Up Undefined Instruction FAULT Invalid / coprocessor instruction Prefetch Abort FAULT TLB miss for instruction Data Abort FAULT TLB miss for data access IRQ INTERRUPT Normal interrupt FIQ INTERRUPT Fast Interrupt (no context switch) SW Interrupt TRAP Undefined / coprocessor instruction
  • 34.
    Exception (cont’d) ARM7 (ISAv4) Exception Vectors Exception Address Mode on Entry Reset 0x00000000 Supervisor Undefined Instruction 0x00000004 Undefined SW Interrupt 0x00000008 Supervisor Prefetch Abort 0x0000000C Abort Data Abort 0x00000010 Abort IRQ 0x00000018 IRQ FIQ 0x0000001C FIQ Reserved 0x00000014 Reserved
  • 35.
    Vector Table Exception Handling When an exception occurs, the ARM:  Copies CPSR into SPSR_<mode>  Sets appropriate CPSR bits  Change to ARM state  Change to exception mode  Disable interrupts (if appropriate)  Stores the return address in LR_<mode>  Sets PC to vector address  To return, exception handler needs to:  Restore CPSR from SPSR_<mode>  Restore PC from LR_<mode> This can only be done in ARM state. Vector table can be at 0xFFFF0000 on ARM720T and on ARM9/10 family devices FIQ IRQ (Reserved) Data Abort Prefetch Abort Software Interrupt Undefined Instruction Reset 0x1C 0x18 0x14 0x10 0x0C 0x08 0x04 0x00
  • 36.
    • Current ProgramStatus Register (CPSR) • Saved Program Status Register (SPSR) • On exception, entering mod mode: – (PC + 4)  LR – CPSR  SPSR_mod – PC  IV address – R13, R14 replaced by R13_mod, R14_mod – In case of FIQ mode R7 – R12 also replaced Exception (cont’d) Process
  • 37.
    Exception priorities When multipleexceptions arise at the same time, a fixed priority system determines the order in which they are handled: Highest priority: 1. Reset 2. Data abort 3. FIQ 4. IRQ 5. Prefetch abort Lowest priority: 6. Undefined Instruction, Software interrupt.
  • 38.
    There are twoways to store data in memory 1 Little-Endian 2 Big – Endian Memory Organization
  • 39.
    Memory Organization • Word,half-word alignment (xxxx00 or xxxxx0) • ARM can be set up to access data in either little-endian or big- endian format, through they default to little-endian.
  • 40.
    Big-endian The most significantbyte (MSB) value, which is 0Ah in our example, is stored at the memory location with the lowest address, the next byte value in significance, 0Bh, is stored at the following memory location and so on. This is akin to Left-to- Right reading in hexadecimal order.
  • 41.
    Little-endian The least significantbyte (LSB) value, 0Dh, is at the lowest address. The other bytes follow in increasing order of significance
  • 42.
    Advanced Microprocessor BusArchitecture (AMBA)
  • 43.
    AHB The AMBAAHB is for high performance, high clock frequency system modules. It acts as a high performance system backbone that is capable for doing burst transfer, connecting the CPU and to on chip and off chip memories. ASB AMBA ASB is an alternative system bus suitable for use where the high performance features of AHB are not required. ASB also supports the efficient connection of CPU, on chip memory and off chip memories. APB AMBA APB is for low-power peripherals. It is optimized for minimal power consumption and reduced interface complexity to support peripheral functions. APB is connected to CPU via AHB/ASB-APB bridge. Advanced Microprocessor Bus Architecture
  • 44.
  • 45.
    5-Stage Pipeline Organization(1/2) • Fetch – The instruction is fetched from memory and placed in the instruction pipeline • Decode – The instruction is decoded and register operands read from the register files. There are 3 operand read ports in the register file so most ARM instructions can source all their operands in one cycle • Execute – An operand is shifted and the ALU result generated. If the instruction is a load or store, the memory address is computed in the ALU I-cache rot/sgn ex +4 byte repl. ALU I decode register read D-cache fetch instruction decode execute buffer/ data write-back forwarding paths immediate fields next pc reg shift load/store address LDR pc SUBS pc post- index pre-index LDM/ STM register write r15 pc + 8 pc + 4 +4 mux shift mul B, BL MOV pc
  • 46.
    5-Stage Pipeline Organization(2/2) • Buffer/Data – Data memory is accessed if required. Otherwise the ALU result is simply buffered for one cycle • Write back – The result generated by the instruction are written back to the register file, including any data loaded from memory I-cache rot/sgn ex +4 byte repl. ALU I decode register read D-cache fetch instruction decode execute buffer/ data write-back forwarding paths immediate fields next pc reg shift load/store address LDR pc SUBS pc post- index pre-index LDM/ STM register write r15 pc + 8 pc + 4 +4 mux shift mul B, BL MOV pc