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Digital electronics(EC8392) unit- 1-Sesha Vidhya S/ ASP/ECE/RMKCETSeshaVidhyaS
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Number System:
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DLD Presentation By Team Reboot,Rafin Rayan,EUBRafin Rayan
Digital Logic Design Presentation By Team Rboot ,Student's of Computer Science & Engineering Department , European University Of Bangladesh . Total 4 Member's Team &Team Leader is Rafin Rayan (Dept. Of CSE,EUB)
Digital electronics(EC8392) unit- 1-Sesha Vidhya S/ ASP/ECE/RMKCETSeshaVidhyaS
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FYBSC IT Digital Electronics Unit I Chapter I Number System and Binary Arithm...Arti Parab Academics
Number System:
Analog System, digital system, numbering system, binary number
system, octal number system, hexadecimal number system, conversion
from one number system to another, floating point numbers, weighted
codes binary coded decimal, non-weighted codes Excess – 3 code, Gray
code, Alphanumeric codes – ASCII Code, EBCDIC, ISCII Code,
Hollerith Code, Morse Code, Teletypewriter (TTY), Error detection
and correction, Universal Product Code, Code conversion.
EEN 1200 L – Digital FundamentalsMerrimack CollegeLaborato.docxSALU18
EEN 1200 L – Digital Fundamentals
Merrimack College
Laboratory 2 – Introduction to 7404 Hex Inverter & Basic Gates & Timing Diagrams
NAME _____________________________
The purpose of this laboratory experiment is to:
I. Get practice in wiring integrated circuits on the trainers
II. Generate “Truth Tables” for basic gates.
III. Use these logic elements to generate a high level logic element.
IV. Generate the “Truth Table”, and identify the logic element.
V. Generate timing diagrams for the basic gates.
Part A: Introduction to 7404 Hex Inverter (IC)
Hook up the 7404 Hex Inverter integrated circuit, and look at the input and output of ONE of the inverters
(pins 1 and 2). Note: There are 6 inverters in the same package, hence the term Hex. See pin-outs of the 7404 Hex Inverter at the last page.
A
B
Z
A
B
Z
A
B
Z
A
B
C
Z
Z
A
B
Logic 1
Logic 1
A
B
Z
A-1) Using the built in signal generator (RED Trainer), place a 1 kHz and TTL input to the inverter. [Be sure to connect the IC (pin 14) to 5VDC and (pin 7) to the ground (GND)].
Look at the input and output together on the scope using 2 Volts DC per division. Draw what you see:
Output Waveform
Input Waveform
Note: Label the x-axis and y-axis
A-2) What is the period? ________________milli-seconds
A-3) Use 5.0 VDC per division on the scope, then read the following on the scope. Draw what you see below.
Voltage amplitude of input=____________
Voltage amplitude of output=____________
Frequency of input=____________
Frequency of output=____________
Period of input=____________
Period of output=____________
Note: Label the x-axis and y-axis
Part B: Basic Gates & Timing Diagrams
A
B
Z
A Truth Table consists of all possible logic inputs and the output that corresponds to each logic input.
In the following, an AND Gate with logic inputs A & B with a logic output Z is shown:
A input
B input
Z output
0
0
0
1
0
0
0
1
0
1
1
1
The timing diagram is discussed at length in Chapter 3. The basic timing diagrams for the logic gates we are using in this lab allow for a visual reading of how the logic functions. By viewing the timing diagram, the reader can see what outputs result from the different possible combinations of inputs. The truth table can easily be determined by looking at the basic timing diagram.
B-1) Follow steps of part A-1 to hook up the 7408 of Quad 2-Input AND gate, then connect input A to SW7 and input B to SW6 then generate a truth table below by measuring output Z using voltmeter. Connect a wire from the output pin to any of the 8 bits LED display located on the upper right corner of the function generator. Note: There are 4 AND gates in the same package.
A
B
C
Z
Input A
Input B
output Z
0
0
1
0
0
1
1
1
B ...
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2024.06.01 Introducing a competency framework for languag learning materials ...Sandy Millin
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Published classroom materials form the basis of syllabuses, drive teacher professional development, and have a potentially huge influence on learners, teachers and education systems. All teachers also create their own materials, whether a few sentences on a blackboard, a highly-structured fully-realised online course, or anything in between. Despite this, the knowledge and skills needed to create effective language learning materials are rarely part of teacher training, and are mostly learnt by trial and error.
Knowledge and skills frameworks, generally called competency frameworks, for ELT teachers, trainers and managers have existed for a few years now. However, until I created one for my MA dissertation, there wasn’t one drawing together what we need to know and do to be able to effectively produce language learning materials.
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Mcsl 17 ALP lab manual
1. ASSEMBLY LANGUAGE PROGRAMMING LAB
SESSION 1
1. Design and implement the Exclusive-OR gate using AND, OR and NOT gates.
Answer:
STEP 1: CIRCUIT SPECIFICATION
Exclusive or is a combinational circuit the Forms the ex-or operation on the two input
values x and y.
Input: Two bits (A, B)
Output: Output= A (+) B
STEP 2: TRUTH TABLE
A B OUTPUT
0 0 0
0 1 1
1 0 1
1 1 0
STEP 3: IDENTIFYING MINTERMS
F1 (1, 2)
STEP 4: K-MAP
0 1
1
STEP 5: EXPRESSION
Output = A (+) B
STEP 6: CIRCUIT
2. 2. Design an “Alarm circuit” using only OR gate in which, if ‘doors’ OR ‘windows’ Or ‘Fire
alarm’ is activated and then alarm sound should start.
(Hint: Alarm is sounded if the output of the above circuit is 1. The Output will be 1 only if any of
the OR conditions given above is true.)
Answer:
STEP 1: CIRCUIT SPECIFICATION
Alarm circuit is a combination circuit that forms output if ‘DOORS’ OR ‘WINDOWS’ Or
‘FIRE ALARM’ are activated by setting the corresponding bit 1.
Input: 3 input bits (‘d’,’w’,’f’)
Output: 1 bit
STEP 2: TRUTH TABLE
DOORS FIRE ALARMS WINDOWS OUTPUT
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1
STEP 3: IDENTIFYING MINTERMS
F1(1,2,3,4,5,6,7)
STEP 4: K-MAP
0 1 1 1
1 1 1 1
STEP 5: EXPRESSION
Output= f+d+w
STEP 6: CIRCUIT
3. 3. We know NAND gate is universal gate but we need proof, so Design other gates like OR, NOR,
AND and NOT using only NAND gates.
Answer:
(A) NOT gate using NAND
(B)AND gate using NAND
(C) OR gate using NAND
(D) NOR gate using NAND
4. 4. Design a digital circuit whose output is equal to 1 if the majority of inputs are 1’s . The output is
0 otherwise.
Answer:
STEP 1: CIRCUIT SPECIFICATION
Digital circuit whose output is equal to 1 if the majority of inputs are 1’s. The output is 0
otherwise.
Inputs: 4 bits (a, b, c, d)
Output: 1 bit
STEP 2: TRUTH TABLE
A B C D OUTPUT
0 0 0 0 0
0 0 0 1 0
0 0 1 0 0
0 0 1 1 0
0 1 0 0 0
0 1 0 1 0
0 1 1 0 0
0 1 1 1 1
1 0 0 0 0
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
STEP 3: IDENTIFYING MINTERMS
F1(13, 14, 15)
STEP 4: K-MAP
0 0 0 0
0 0 1 0
0 1 1 1
0 0 1 0
STEP 5: EXPRESSION
Output = abc+abd+bcd+acd
STEP 6: CIRCUIT
5. 5. Design the following digital circuit
Answer:
A. HALF ADDER
A half adder circuit takes 2 binary input and gives its sum. The input is 2 bits are a and b
the outputs are its sum and carry.
STEP 1: CIRCUIT SPECIFICATION
Inputs: 2 bits
Outputs: Sum and Carry
STEP 2: CIRCUIT AND TRUTH TABLE
B. HALF SUBTRACTOR
A half subtractor circuit takes 2 binary input and gives its difference. The input is 2 bits are
a and b the outputs are its difference and borrow
STEP 1: CIRCUIT SPECIFICATION
Input: 2 bits
Output: Difference and Borrow
STEP 2: CIRCUIT AND TRUTH TABLE
6. C. FULL SUBTRACTOR
A full subtractor is a combinational circuit that performs a subtraction between two bits
taking into account that a one may be borrowed by a lower significant bit, the circuit has 3 inputs
A, B and C. and 2 outputs Difference and Borrow.
STEP 1: CIRCUIT SPECIFICATION
Inputs: A, B and C
Outputs: Difference and Borrow
STEP 2: CIRCUIT AND TRUTH TABLE
7. 6. Design a logical circuit that will calculate the following function:
Answer:
INPUTS OUTPUT
A B C D
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 1
Explain why your circuit is correct.
This circuit is correct as its truth table is same as given truth table.
8. 7. Design a combinational circuit that takes 3-bit number and the output of that circuit should be
the square of the input Number.
Answer:
STEP 1: CIRCUIT SPECIFICATION
Square of the number is a combinational circuit that can be obtained by taking 3 bits inputs and 6
bit outputs.
STEP 2: TRUTH TABLE
A B C O1 O2 O3 O4 O5 O6
0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 0 0 1
0 1 0 0 0 0 1 0 0
0 1 1 0 0 1 0 0 1
1 0 0 0 1 0 0 0 0
1 0 1 0 1 1 0 0 1
1 1 0 1 0 0 1 0 0
1 1 1 1 1 0 0 0 1
STEP 3: IDENTIFYING MINTERMS
O1=F1 (6, 7)
O2=F2 (4, 5, 7)
O3=F3 (3, 5)
O4=F4 (2, 6)
O5=0
O6=F6 (1, 3, 5, 7)
The Boolean functions for the three inputs and 6 outputs are derived as follows:-
For F1 (6, 7)
O1=AB
For F2 (4, 5, 7)
O2=AB`+AC
For F3 (3, 7)
O3=A`BC+AB`C
For F4 (2, 6)
O4=BC`
For F6 (1, 3, 5, 7)
O6=C
STEP 4: CIRCUIT
11. SESSION 2
10. Design Sequential Circuit of clocked RS flipflop with 4 NAND gates.
Answer:
The circuit has R and S inputs and a clock input. This latch flip flop is activated by a positive level
on the clock input.
If clock = 0, Output Q, Q`= Hold (nochange)
If clock = 1, R=0, S=1,Q=1 State = Set
If clock =1, R=1, S=0, Q`=1 State= Reset
If clock =1, R=0, S=0, State = Hold (no change)
SCHEMATIC:
TRUTH TABLE:
CLOCK S R Qn+1
LOW X X Qn
HIGH 0 0 Qn
HIGH 0 1 0
HIGH 1 0 1
HIGH 1 1 INDETERMINATE
CIRCUIT:
11. Design Sequential Circuit of Clocked D flip flop with AND and NOR gates.
Answer:
12. A D-type latch is shown below.
The advantage of this is the single D input.
The flip flop takes the value at its D input whenever the clock pulse input is high it will effectively
“track’ the input levels as long as the clock input is high.
If the clock input is zero, the state will be that of the last state the flipflop was when it was high.
TRUTH TABLE:
CLOCK D Qn+1
LOW X Qn
HIGH 0 0
HIGH 1 1
CIRCUIT:
12. Design an 8-bit counter using two 4-bit counters.
13. Answer:
An 8-bit counter made from two 4-bit counters is shown below. The bottom device
represents the least significant four bits, while the top counter represents the most significant four
bits. When the bottom counter reaches 1111 (i.e., when CO = 0), it enables the top counter for one
cycle. Here the counters share clock and clear signals Hex displays are used here.
13. Design Linear Feed-back Shift Register.
Answer:
SCHEMATIC:
14. TRUTH TABLE:
CLOCK QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
5 0 1 1 1
6 0 0 1 1
7 0 0 0 1
CIRCUIT:
14. Design a logical circuit that will calculate the less-than (<) function for two 2-bit inputs. That
is, if the inputs are A and B, each of whose values can be in the range 0-3 (i.e., 00-11 in binary),
then the output should be 1 whenever A < B, and 0 otherwise. This circuit requires four inputs,
referred to as a1, a2, b1, and b2. a1 and a2 represent a 2-bit number, as do b1 and b2. The output
will be true if the decimal number represented by the pair a1a2 is less than the decimal number
represented by b1b2. Design this circuit with an optimal number of gates.
Answer:
15. STEP 1: CIRCUIT SPECIFICATION
This circuit compares two inputs of size 2- bits i.e. its range is (0-3) the output will be 1 if A<B
else0
Input: 2 input bits
1 bit for A0
1 bit for A1
1 bit for B0
1 bit for B1
Output: 1 bit (either 0 or 1)
STEP 2: TRUTH TABLE
STEP 3: IDENTIFYING MINTERMS
O1=F1 (1, 2, 3, 6, 7, 11)
STEP 4: CIRCUIT
15. A multiplexer circuit accepts N inputs and outputs the value of one of those inputs. The
selection of which input goes out on the output is determined by a set of M control inputs. A
16. multiplexer with M control inputs can steer up to 2M inputs to a single output. Design 2-to-1
multiplexer.
Answer:
Multiplexing means transmitting a large number of information units over a smaller number
of channels or lines. A 2-to-1 multiplexer sends one of 2M input lines to a single output line.
SCHEMATIC:
TRUTH TABLE:
S D1 D0 Q
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
CIRCUIT:
16. A decoder has M inputs and up to 2M outputs. If the logic values on the M inputs are
interpreted as a binary number of value P, then the Pth output will be at logic 1 while all the others
are at logic 0. Design 2-to-4 decoder.
Answer: