Arithmetic PPT of COA that can be helpful for understanding the sums of COA

2. Arithmatic
 We discuss some of the techniques used in modern
computers to perform arithmetic operations at high
speed

3. Addition/subtraction of unsigned numbers
si =
ci +1 =
13
7
+ Y
1
0
0
0
1
0
1
1
0
0
1
1
0
1
1
0
0
1
1
0
1
0
0
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Example:
1
0
= = 0
0
1 1
1
1 1 0 0
1
1 1 1
0
Legend for stage i
xi yi Carry-in ci Sumsi Carry-outci+1
X
Z
+ 6 0
+
xi
yi
si
Carry-out
ci+1
Carry-in
ci
xi
yi
ci
xi
yi
ci
xi
yi
ci
xi
yi
ci xi yi ci
 
=
+ + +
yi
ci
xi
ci
xi
yi
+ +
At the ith stage:
Input:
ci is the carry-in
Output:
si is the sum
ci+1 carry-out to (i+1)st
state

4. Addition logic for a single stage
Full adder
(FA)
ci
ci 1
+
s
i
Sum Carry
yi
xi
c
i
yi
xi
c
i
yi
x
i
xi
ci
yi
si
c
i 1
+
Full Adder (FA): Symbol for the complete circuit
for a single stage of addition.

5. n-bit adder
•Cascade n full adder (FA) blocks to form a n-bit adder.
•Carries propagate or ripple through this cascade, n-bit ripple carry adder.
FA c0
y1
x1
s1
FA
c1
y0
x0
s0
FA
cn 1
-
yn 1
-
xn 1
-
cn
sn 1
-
Most significant bit
(MSB) position
Least significant bit
(LSB) position
Carry-in c0 into the LSB position provides a convenient way to
perform subtraction.

6. K n-bit adder
K n-bit numbers can be added by cascading k n-bit adders.
n-bit c
0
yn
xn
s
n
cn
y0
xn 1
-
s
0
ckn
s
k 1
-
( )n
x0
yn 1
-
y2n 1
-
x2n 1
-
ykn 1
-
s
n 1
-
s
2n 1
-
s
kn 1
-
xkn 1
-
adder
n-bit
adder
n-bit
adder
Each n-bit adder forms a block, so this is cascading of blocks.
Carries ripple or propagate through blocks, Blocked Ripple Carry Adder

7. n-bit subtractor
FA 1
y1
x1
s1
FA
c1
y0
x0
s0
FA
cn 1
-
yn 1
-
xn 1
-
cn
sn 1
-
Most significant bit
(MSB) position
Least significant bit
(LSB) position
•Recall X – Y is equivalent to adding 2’s complement of Y to X.
•2’s complement is equivalent to 1’s complement + 1.
•X – Y = X + Y + 1
•2’s complement of positive and negative numbers is computed similarly.

8. n-bit adder/subtractor (contd..)
Add/Sub
control
n-bit adder
x
n 1
-
x
1
x
0
c
n
s
n 1
- s
1
s
0
c
0
y
n 1
-
y
1
y
0
•Add/sub control = 0, addition.
•Add/sub control = 1, subtraction.

9. Detecting overflows
 Overflows can only occur when the sign of the two operands is
the same.
 Overflow occurs if the sign of the result is different from the
sign of the operands.
 Recall that the MSB represents the sign.
 xn-1, yn-1, sn-1 represent the sign of operand x, operand y and result s
respectively.
 Circuit to detect overflow can be implemented by the
following logic expressions:
1
1
1
1
1
1 




 
 n
n
n
n
n
n s
y
x
s
y
x
Overflow
1


 n
n c
c
Overflow

10. Computing the add time
Consider 0th stage:
x0
y0
c0
c1
s0
FA
•c1 is available after 2 gate delays.
•s1 is available after 1 gate delay.
c
i
yi
xi
c
i
yi
x
i
xi
ci
yi
si
c
i 1
+
Sum Carry
Delay can be calculated
by adding up the number
of logic gate delays along
the longest signal
propagation path through
the circuit

11. Computing the add time (contd..)
x0
y0
s2
FA
x0 y0
x0
y0
s1
FA
c2
s0
FA
c1
c3
c0
x0
y0
s3
FA
c4
Cascade of 4 Full Adders, or a 4-bit adder
•s0 available after 1 gate delays, c1 available after 2 gate delays.
•s1 available after 3 gate delays, c2 available after 4 gate delays.
•s2 available after 5 gate delays, c3 available after 6 gate delays.
•s3 available after 7 gate delays, c4 available after 8 gate delays.
For an n-bit adder, sn-1 is available after 2n-1 gate delays
cn is available after 2n gate delays.

12. Fast addition
Recall the equations:
i
i
i
i
i
i
i
i
i
i
i
c
y
c
x
y
x
c
c
y
x
s






1
Second equation can be written as:
i
i
i
i
i
i c
y
x
y
x
c )
(
1 



We can write:
i
i
i
i
i
i
i
i
i
i
y
x
P
and
y
x
G
where
c
P
G
c





1
•Gi is called generate function and Pi is called propagate function
•Gi and Pi are computed only from xi and yi and not ci, thus they can
be computed in one gate delay after X and Y are applied to the
inputs of an n-bit adder.
Pi can be implemented using xor gate
Two approaches are
used
1. Used fastest possible
electronic technology
2. Carry-lookahead
network

13. Carry lookahead
ci 1  Gi  Pici
ci  Gi1  Pi1ci1
 ci1  Gi  Pi(Gi1  Pi 1ci 1)
continuing
 ci1  Gi  Pi(Gi1  Pi 1(Gi 2  Pi 2ci 2 ))
until
ci1  Gi  PiGi 1  Pi Pi1Gi 2  ..  PiPi1..P1G0  Pi Pi 1...P0c0
•All carries can be obtained 3 gate delays after X, Y and c0 are applied.
-One gate delay for Pi and Gi
-Two gate delays in the AND-OR circuit for ci+1
•All sums can be obtained 1 gate delay after the carries are computed.
•Independent of n, n-bit addition requires only 4 gate delays.
•This is called Carry Lookahead adder.

14. Carry-lookahead adder
Carry-lookahead logic
B cell B cell B cell B cell
s
3
P3
G3
c
3
P2
G2
c
2
s
2
G
1
c
1
P
1
s
1
G
0
c
0
P
0
s
0
.
c4
x
1
y
1
x
3
y
3
x
2
y
2
x
0
y
0
G i
c
i
.
.
.
P i
s i
x i
y i
B cell
4-bit
carry-lookahead
adder
B-cell for a single stage

15. Draw the block diagram of 4bit carry-lookahead adder .Justify that
it required only four gate delay independent of n

17. Multiplication of unsigned numbers
Product of 2 n-bit numbers is at most a 2n-bit number.
Unsigned multiplication can be viewed as addition of shifted
versions of the multiplicand.

18. Multiplication of unsigned
numbers (contd..)
 We added the partial products at end.
 Alternative would be to add the partial products at each stage.
 Rules to implement multiplication are:
 If the ith bit of the multiplier is 1, shift the multiplicand and add the
shifted multiplicand to the current value of the partial product.
 Hand over the partial product to the next stage
 Value of the partial product at the start stage is 0.

19. Multiplication of unsigned numbers
ith multiplier bit
carry in
carry out
jth multiplicand bit
ith multiplier bit
Bit of incoming partial product (PPi)
Bit of outgoing partial product (PP(i+1))
FA
Typical multiplication cell

20. Combinatorial array multiplier
Multiplicand
m3 m2 m1 m0
0 0 0 0
q3
q2
q1
q0
0
p2
p1
p0
0
0
0
p3
p4
p5
p6
p7
PP1
PP2
PP3
(PP0)
,
Product is: p7,p6,..p0
Multiplicand is shifted by displacing it through an array of adders.
Combinatorial array multiplier

21. Combinatorial array multiplier
(contd..)
 Combinatorial array multipliers are:
 Extremely inefficient.
 Have a high gate count for multiplying numbers of practical size such as 32-
bit or 64-bit numbers.
 Perform only one function, namely, unsigned integer product.
 Improve gate efficiency by using a mixture of
combinatorial array techniques and sequential
techniques requiring less combinational logic.

22. Sequential multiplication
 Recall the rule for generating partial products:
 If the ith bit of the multiplier is 1, add the appropriately shifted multiplicand
to the current partial product.
 Multiplicand has been shifted left when added to the partial product.
 However, adding a left-shifted multiplicand to an
unshifted partial product is equivalent to adding an
unshifted multiplicand to a right-shifted partial
product.

23. Sequential Circuit Multiplier
q
n 1
-
m
n 1
-
n-bit
Adder
Multiplicand M
Control
sequencer
Multiplier Q
0
C
Shift right
Register A (initially 0)
Add/Noadd
control
a
n 1
-
a
0
q
0
m
0
0
MUX

24. Sequential multiplication (contd..)
1 1 1 1
1 0 1 1
1 1 1 1
1 1 1 0
1 1 1 0
1 1 0 1
1 1 0 1
Initial configuration
Add
M
1 1 0 1
C
First cycle
Second cycle
Third cycle
Fourth cycle
No add
Shift
Shift
Add
Shift
Shift
Add
1 1 1 1
0
0
0
1
0
0
0
1
0
0 0 0 0
0 1 1 0
1 1 0 1
0 0 1 1
1 0 0 1
0 1 0 0
0 0 0 1
1 0 0 0
1 0 0 1
1 0 1 1
Q
A
Product

25. 8085 program

27. Manual Division
Longhand division examples.
1101
1
13
14
26
21
274 100010010
10101
1101
1
1110
1101
10000
13 1101

28. Longhand Division Steps
 Position the divisor appropriately with respect to the
dividend and performs a subtraction.
 If the remainder is zero or positive, a quotient bit of 1
is determined, the remainder is extended by another
bit of the dividend, the divisor is repositioned, and
another subtraction is performed.
 If the remainder is negative, a quotient bit of 0 is
determined, the dividend is restored by adding back
the divisor, and the divisor is repositioned for another
subtraction.

29. Circuit Arrangement
Figure 6.21. Circuit arrangement for binary division.
qn-1
Divisor M
Control
Sequencer
Dividend Q
Shift left
N+1 bit
adder
q0
Add/Subtract
Quotient
Setting
A
m0
0 mn-1
a0
an
an-1

30. Restoring Division
 Shift A and Q left one binary position
 Subtract M from A, and place the answer back in A
 If the sign of A is 1, set q0 to 0 and add M back to A
(restore A); otherwise, set q0 to 1
 Repeat these steps n times

31. Examples
1
0
1
1
1
Figure 6.22. A restoring-division example.
1 1 1 1 1
0
1
1
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1 0
1
1
1
1 1
0
1
0
0
0
1
Subtract
Shift
Restore
1 0
0
0
0
1 0
0
0
0
1 1
Initially
Subtract
Shift
1
0
1
1
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
Subtract
Shift
Restore
1
0
1
1
1
0
1
0
0
0
1
0
0
0
0
1 1
Quotient
Remainder
Shift
1
0
1
1
1
1 0
0
0
0
Subtract
Second cycle
First cycle
Third cycle
Fourth cycle
0
0
0
0
0
0
1
0
1
1
0
0
0
0
1 1
1 0
0
0
0
1
1
1
1
1
Restore
q0
Set
q0
Set
q0
Set
q0
Set

32. Nonrestoring Division
 Avoid the need for restoring A after an
unsuccessful subtraction.
 Any idea?
 Step 1: (Repeat n times)
If the sign of A is 0, shift A and Q left one bit position and
subtract M from A; otherwise, shift A and Q left and add M
to A.
Now, if the sign of A is 0, set q0 to 1; otherwise, set q0 to 0.
 Step2: If the sign of A is 1, add M to A
In restoring we are doing A+M then shift so 2A+2M then subtract M so 2A+M

33. Examples
A nonrestoring-division example.
Add
Restore
remainder
Remainder
0 0 0 0
1
1 1 1 1 1
0 0 0 1 1
1
Quotient
0 0 1 0
1 1 1 1 1
0 0 0 0
1 1 1 1 1
Shift 0 0 0
1
1
0
0
0
0
1
1
1
1
Add
0 0 0 1 1
0 0 0 0 1 0 0 0
1 1 1 0 1
Shift
Subtract
Initially 0 0 0 0 0 1 0 0 0
1 1 1 0 0
0
0
0
1 1 1 0 0
0 0 0 1 1
0 0 0
Shift
Add
0 0 1
0 0 0 0
1
1 1 1 0 1
Shift
Subtract
0 0 0 1
1
0
0
0
0
Fourth cycle
Third cycle
Second cycle
First cycle
q
0
Set
q
0
Set
q
0
Set
q
0
Set

35. Signed Multiplication
 Considering 2’s-complement signed operands, what will happen to (-
13)(+11) if following the same method of unsigned multiplication?
Sign extension of negative multiplicand.
1
0
1
1 1
1 1 1 0 0 1 1
1
1
0
1
1
0
1
0
1
0
0
0
1
1
1
0
1
1
0
0
0
0
0
0
1
1
0
0
1
1
1
0
0
0
0
0
0
0
0
1
1
0
0
1
1
1
1
1
13
-
( )
143
-
( )
11
+
( )
Sign extension is
shown in blue

36. Signed Multiplication
 Not work well for all kind of signed operand
 A technique that works equally well for both negative
and positive multipliers – Booth algorithm.

37. Booth Algorithm
 First represent multiplier using different encoding
 Put -1 when go form 0 to 1, put 1 when going from
1 to 0 and put 0 when going from 1 to 1 or 0 to 0
 Assume 0 to right of lsb of multiplier
 E.g. multiplier is 30 so 0011110
 Represented as 0+1000-10

38. Booth Algorithm
Booth multiplication with a negative multiplier.
0
1
0
1 1 1 1 0 1 1
0 0 0 0 0 0 0 0 0
0
0
0
1
1
0
0 0 0 0 1 1 0
1
1
0
0
1
1
1
0 0 0 0 0 0
0
1
0
0
0 1
1
1
1
1
1
1
0 1 1 0 1
1 1 0 1 0 6
-
( )
13
+
( )
X
78
-
( )
+1
1
- 1
-

39.  Multiply -5X-2
 (-5) 1011 1011
 (-2) 1110 00-1 0
 0000
 01010
 Answer 1010

40. he two numbers given below are multiplied
using the Booth’s algorithm.
Multiplicand : 0101 1010 1110 1110
Multiplier: 0111 0111 1011 1101
How many additions/Subtractions are
required for the multiplication of the above
two numbers?
(A) 6
(B) 8
(C) 10
(D) 12
+1 0 0 -1 +1 0 0 0 -1 +1 0 0 0 -1 +1 -1

41. Using Booth’s Algorithm for multiplication,
the multiplier -57 will be recoded as
(A) 0 -1 0 0 1 0 0 -1
(B) 1 1 0 0 0 1 1 1
(C) 0 -1 0 0 1 0 0 0
(D) 0 1 0 0 -1 0 0 1

42. Booth’s algorithm for integer multiplication
gives worst performance when the
multiplier pattern is
(A) 101010 ………1010
(B) 100000 ………0001
(C) 111111 ………1111
(D) 011111 ………1110

44. IEEE notation
IEEE Floating Point notation is the standard representation in use. There are two
representations:
- Single precision.
- Double precision.
Both have an implied base of 2.
Single precision:
- 32 bits (23-bit mantissa, 8-bit exponent in excess-127 representation)
Double precision:
- 64 bits (52-bit mantissa, 11-bit exponent in excess-1023 representation)
Fractional mantissa, with an implied binary point at immediate left.
Sign Exponent Mantissa
1 8 or 11 23 or 52

45. Peculiarities of IEEE notation
•Floating point numbers have to be represented in a normalized form to
maximize the use of available mantissa digits.
•In a base-2 representation, this implies that the MSB of the mantissa is
always equal to 1.
•If every number is normalized, then the MSB of the mantissa is always 1.
We can do away without storing the MSB.
•IEEE notation assumes that all numbers are normalized so that the MSB
of the mantissa is a 1 and does not store this bit.
•So the real MSB of a number in the IEEE notation is either a 0 or a 1.
•The values of the numbers represented in the IEEE single precision
notation are of the form:
(+,-) 1.M x 2(E - 127)
•The hidden 1 forms the integer part of the mantissa.
•Note that excess-127 and excess-1023 (not excess-128 or excess-1024) are used
to represent the exponent.

46. Represent 20.59375 into short real format
10100 + .10011=10100.10011
1.010010011 X E 4
S=0 E=127+4=131=10000011
0 10000011 01001001100000000000000
e.g. e.g. 0 10000010 01101100000000000000000
Exp=130-127=3
No is 1.011011 X 23 =1011.011=11.375