Kartik Parmar has over 4 years of experience in ASIC verification using SystemVerilog, UVM and related tools. He has worked on verifying FPGA designs for applications such as video processing, I/O modules and data processing. His skills include developing UVM testbenches, writing functional coverage and regression test scripts in Perl and Python. He is proficient in object oriented programming and protocols like AXI and AMBA.

1. KARTIK PARMAR
Mobile: +91-7259144097
Email: kartik.prmr@gmail.com
PROFESSIONAL EXPERIENCE:
4.9 years of experience in:
 ASIC Verification experience that includes development of the Verification Environment,
SV/UVM Testbench development, Testplan definition and development, Testcase
implementation, Functional Coverage and checker coverage implementation,
Regression analysis and Code Coverage.
 Good exposure in developing complete SV/UVM environment and reusable UVCs from
scratch.
 Module level as well as SOC Level verification and Debugging using UVM, OVM, System
Verilog (SV) and VHDL.
 Expertise in scripting – Perl, Object Oriented Perl, Python, Shell.
 Proficient in Object Oriented Programming concept.
 Knowledge of AMBA AXI-Stream and AXI4 protocols.
EXPERIENCE:
Worked at eInfochips LTD, Ahmedabad as ASIC Verification Engineer, from Aug 2011 to April
2015.
Working at Wafer Space as Design Engineer II from April 2015 to till date.
PROFESSIONAL SKILLS
Operating Systems Linux, Windows
HDL Verilog HDL,VHDL
HVL System Verilog
Methodology UVM, OVM
Scripting languages Perl, Shell, Python
EDA Tools Questasim, ISE
Other Tools ModelSim
EXPERIENCE DETAILS
Project #5:
Project : Verification of 5 different FPGA of Trusted TMR IO Family
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2. Technology : Trusted TM Input/Output Module
Team Size: 2
Script : Perl, Shell
Language : System Verilog/UVM
Tools : Questasim, P4 (Version Control)
Description :
The Trusted TMR Digital24V/48V, Analog, Speed and AC Output FPGAs are a member of the
Trusted range of Input/Output (I/O) modules.
Role and responsibility :
 Developing scripts from scratch in shell & perl for automation of the compilation and
simulation activities.
 Developing complete UVM Environment from scratch for 5 FPGA of Trusted IO family.
 Writing testcases and regression analysis.
 Writing Perl script for Missing Code Coverage Analysis.
 Code coverage analysis (Statement, Branch, Condition, Expression & Toggle) and
coverage closure.
Project #4:
Project :
DO-254 compliant DEL – A, High Speed Data Processing FPGA SOC
Verification
Technology : ARINC429 RX, ARINC429 TX, DDR2, AXI4, AXI4-Stream, SRIO, ADC,
Discrete
Team Size : 6-8
Language : System Verilog/OVM
Tools : Questasim, SVN, CVS, DOORS, PREP
Description :
The SOC verification of the FPGA device that concentrates data, and makes it available via the
high speed serial interfaces and the A429 transmitters.
The main functions of the SOC are the following:
 Two independent serial RapidIO interfaces that can individually configured for read-only
operations.
 Analog to Digital converter SPI interface supporting up to sixty-four channels with a
configurable serial data stream length.
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3.  Sixteen ARINC 429 transmitters.
 Sixty-four ARINC 429 receivers.
 Discrete interface with thirty-two general purpose IO, expandable via I2C interface to a
total of 1056 discrete.
 Frequency interface for converting tachometer and fuel flow data.
 DDR2 memory interface that is used to store time-tagged, receive ARINC 429 data
 DDR2 EDAC and test controller.
 Data forwarding interface that is used to autonomously transmit data from the ADC,
discrete and frequency functions out of the ARINC 429 transmitters.
Role and responsibility :
 Understanding the device level requirements and identifying the scenarios.
 Writing testplan as per the requirements of DO-254 for different blocks within the
Device.
 Implementing testcases and debugging simulation failure during the development of the
testcases.
 Writing test result summary perl script used for post processing to generate the
regression summary of the testcases in excel file.
 Writing functional coverage validation perl script to validate the cover bin hit.
Project #3:
Project : AXI Stream and AXI-4 VIP
Technology : AXI
Team Size : 3
Language : System Verilog/OVM
Tools Questasim, SVN, CVS
Description :
 The AMBA AXI protocol supports high-performance, high-frequency system designs. The
AXI4-Stream and AXI-Full protocols are used as a standard interface to connect
components that wish to exchange data. The interface can be used to connect a single
master that generates data, to a single slave, that receives data. The protocol can also be
used when connecting larger numbers of master and slave components.
Role and responsibility :
 Understanding the specification and capturing requirements in compliance with DO-254
process.
 Writing testplan to verify the requirements compliance with DO-254 process.
 Developing AXI BFM and SV/OVM Env.
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4.  Implementation of testcases and debugging.
Project #2:
Project :
DO-254 compliant DEL – A, Video Processing And Distortion Correction
FPGA Verification
Technology : Video Processing, Digital Signal Processing, DDR2, Flash, I2C, USB, TCON
LVDS
Team Size : 3
Language : Verilog, VHDL
Tools QuestaSim, SVN, CVS, DOORS, PREP
Description :
The SOC verification of the FPGA device that provides distortion correction to a video stream to correct
for the optical distortion in the optical path through the HPU and Combiner.
The main function of the SOC are following:
 A Video Transfer Interface to receive input video stream for applying distortion correction
algorithm.
 A Flash Memory Interface to transfer one of the eight DLUTs that are stored in flash memory.
 A USB interface used to program the DLUTs into the flash memory during the manufacturing
process.
 A BIT Data Interface used to report the error flags and CRC errors.
 A DLUT SDRAM Interface used to provide 32-bit instruction to the distortion processor for
processing the images provided by video stream.
 A Distortion Processor to process the video stream provided on Video Transfer Interface.
 A Frame Buffer SDRAM interface to store the distortion corrected images.
 A TCON LVDS interface to transmit the distortion corrected images to the AMLCD Timing
Controller.
 A Brightness Monitor EEPROM interface that reads from and writes to an ST Microelectronics
M24C64 serial I2C EEPROM.
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5. Role and responsibility :
 Writing Verification plan document in compliance with DO-254.
 Development of Verification Environment using Test Harness concept. Writing test
cases, monitors, Bus Functional Models.
 Performing simulation activities and debuggingfailure while developing the test cases.
 Writing test result summary perl script used for post processing to generate the
regression summary of the testcases in excel file.
Project #1:
Project :
DO-254 compliant Design Assurance Level – A, Nand Controller FPGA:
Hardware Testing
Technology : Nand Controller
Role : Team Member
Team Size : 3
Language : TCL
Tools ETSI
Methodology None
Description :
 The ONFI NAND Controller is an FPGA device which interfaces between the PPC-460
processor and NAND Flash memory devices used to store file systems on the AFD-3700
display.
Role and responsibility :
 Writing test plan in DOORs as per DO-254 Process.
 Writing prototype testcases for hardware testing.
EDUCATIONAL QUALIFICATION
 I have completed B.Tech. In Electronics & Communication from School Of Engineering,
Singhania University in 2011.
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