Srishail Upadhye is an ASIC design engineer with over 3 years of experience specializing in design for test, static timing analysis, and RTL design. He is currently pursuing an MS in electrical engineering at Arizona State University and has worked at LSI Logic designing test logic and verifying chips for Cisco and RAID accelerators. His skills include RTL design, formal verification, static timing analysis, design for test techniques, and experience with Synopsys, Cadence, and Mentor Graphics tools.

1. Srishail Upadhye
Unit # 335, 625 W, 1st street 1-480-559-4867
Tempe, AZ 85281 supadhye@asu.edu
Linkedin : www.linkedin.com/in/srishail/
SUMMARY
ASIC Design Engineer with 3.5 years of ASIC design experience at LSI Logic, specializing in Design for Test (DFT),
Static Timing Analysis (STA) and RTL Design
SKILLS
 STA, MBIST, ATPG Stuck-At & Transition, BSCAN, PLL Debug, JTAG, FV, Coverage analysis and improvement
 RTL Design & Verification
 RTL coding, Coverage analysis and improvement, RTL assertions
 Verilog, System Verilog, VHDL, Basic OVM & UVM Methodology
 FPGA and FPGA prototyping
 Tools : Synopsys-ICC, Primetime, VCS, FPGA-Xilinx, Cadence-Virtuoso, Spectre, Encounter, Mentor-Fastscan, Tessent
 Languages: C, Verilog, System Verilog, VHDL, Perl, Tcl/Tk
EDUCATION
MS Candidate - Electrical Engineering, Mixed Signal Circuit Design Expected May 2016
Arizona State University, GPA 3.8
Bachelor of Engineering, Electronics and Telecommunication August 2009
Pune University, GPA 3.87
ACADEMIC PROJECTS
 Register File – Layout and Design, optimization focus - area and EDP
 Layout and Design of 8 bit pipelined adder and optimization for minimum EDP
 Standard Cell Design for 32nm process
 Development of exception handler for 32bit MIPS processor
RELATED EXPERIENCE
ASIC Design Engineer 2, LSI Logic Oct 2011 - July 2014
Design for Test & Static Timing analysis, Custom Silicon Design group
 Block Level DFT logic insertion, Block level Static Timing Analysis (STA) and Silicon Verification/Debugging on Cisco
‘Strider’ – 28nm CAM intensive Router design with gate count of ~40 million
 Individual owner - Memory BIST synthesis and BSCAN/JTAG synthesis and responsible for In-System BIST
support at Cisco’s end (customer interface)
 ATE pattern generation and pattern simulation with/without timing annotation,
 Debug ATE pattern failures : MBIST, BSCAN, JTAG, SERDES (coreware/IP)
 Lead DFT for a 28nm SERDES test chip – flop count of ~1million
 ATPG for Stuck-At, Transition, IDDQ, DRC analysis
 Coverage analysis and improvement
 PLL test solution development in coordination with PLL design team,
 Address PLL bring up and PLL frequency locking issues on silicon
 SERDES test programming through JTAG interface
 Static Timing Analysis (STA) for 2 blocks with a gate count of ~500K - False path and Multicycle path
recognition, timing Constraint analysis and improvement, CDC checks
 Individual owner - Formal Verification of 28nm Low Power SERDES test chip
 Debug Post-Silicon SCAN chain integrity issues and MBIST issues for two 28nm SERDES test chips
 Pre-Test/Post-Test netlist quality check automation using Perl and Tcl
Intern - RTL Design, LSI Logic Jan 2011 - Oct 2011
RAID Accelerator engine and Storage Design group
 RTL Design and Implementation of AMBA-AHB module on a 28 nm RAID Accelerator chip
 Successful Design and Verification of top level - AHB Master slave(s) system with AHB Arbiter module using Verilog
HDL
 Building testbenches, development of verification environment
 Functional verification
 Automated design and verification tasks using Tcl, Perl, Shell scripts
Guest Lecturer, Centre for Development of Advanced Computing- CDAC ACTS May 2014 - June 2014
 Taught RTL Synthesis and DFT concepts to graduate diploma students
COURSEWORK
 Courses : Digital Circuit Design, Hardware Design & Verification Languages and VLSI Design