Wei Wei is seeking full-time positions in ASIC/digital design, verification, RTL design, and hardware design. He has experience in ASIC design flow including RTL design, functional simulation, verification, and static timing analysis. He has a Master's degree in Electrical Engineering from Illinois Institute of Technology and a Bachelor's degree from Beijing Information Science & Technology University. His technical skills include Verilog, C/C++, Python, Modelsim, Cadence Virtuoso, and Matlab. His past experience includes working as an application engineer testing GPS/INS devices and power supply products.