2. Introduction - 1978-84
Apprentice Electrician and Electronics Hobbyist, ONC, HNC, B.Eng.
Degree sponsored by WD & HO Wills (Imperial Tobacco Ltd.)
HAUNI PROTOS Cigarette making machine 7-20000 Cig/Min
1984 Designed and constructed a
Motorola 6502 based, 4 channel
transient recorder as a HNC project,
for which I received a distinction.
1980: Disco console. I designed the pre-amps… hummed, purchased kits… hummed.
(Lesson learnt... Ground loops & Star points)
3. Power Electronics – ASIC 1984-91
Initially, a project engineer for AC and DC variable speed
Motor Drives/Inverters, moved to UPS C&I.
Started a Power Electronics M.Sc. at University of Bristol.
1st FPGA project using Xilinx XC2064.
Moved into design for UPS subsystems, and project lead for AP10-50 series domestic UPS.
I developed Emerson’s first mixed signal ASIC (SGS Thomson 6μ mixed signal cell array).
Liebert 610 Online UPS
225-1000kVA
3 Phase Inverters
4. ASIC and FPGA 1991-present
Ericsson: GSM and Bluetooth Baseband
designer. Design in VHDL, and Verilog.
Designed a Bluetooth-Ethernet reference
design to promote a potential ASIC project.
GEC Plessey, Semicustom & Media Group.
Gave a presentation VHDL User Group.
Teletext and Satellite FEC design,
13 tape outs, schematic and VHDL
Ericsson sold the division to Infineon who closed the Swindon office in 2003.
Using redundancy, I purchased Altium Designer and Modelsim PE Dual Language, registered
Ipeva Limited December 2003, dissolved the company in 2014.
5. C-RTL
Read Solomon for DVB Satellite decoder, one of a three chip
chipset.
V42bis de/compression in hardware for a phone baseband.
Evaluated Cadence DFII and SPW (Signal Processing Workbench)
with HDS option to attempt co-simulating VHDL model concurrently
with the ANSI C model.
Evaluated a number of C-RTL tool flows for Ericsson, which also
formed the basis of my M.Sc. Dissertation.
Modelled a graphical system based on a PIC processor coded in
VHDL, C, and JAVA.
Compared performance of system level modelling, simulation and
synthesis of each language, and ease of co-simulating models in
Modelsim simulator using C-FLI, and TCP sockets.
6. Bluetooth
Block designer responsible for Voice codec µ law, α law, CVSD,
MPCM, DMA and ARM top level integration.
IP verified in simulation and on FPGA platforms for Software
development.
Developed a fully automated flow converting VHDL RTL IP to
Verilog for supply to Ericsson’s customers.
Used Advanced System Concepts (ASC) V2V and Synopsys
formality
Source VHDL required recoding to strict coding guideline, and low
level RTL arithmetic to convert correctly to Verilog.
Regression suite run on Cadence Incisive, Mentor Modelsim and
Synopsys VCS.
7. Board, FPGA and ASIC
System Level design, RTL, ASIC, FPGA
and PCB design and verification.
Board level design using Cadence
Pspice, Orcad, Mentor Graphics
Boardstation, Altium Designer, tape and
foils, and pen and paper
8. PMIC
Highly integrate Power Management devices.
Mainly Analogue with Digital control, power sequencing,
monitoring with I2C, SPI and DWI interfaces to host.
Many LDO’s, Bucks and Buck/Boost converters.
Extensive use of gated clocks, latches and
asynchronous logic.
Limited (often none) digital test access.
Micro BGA package, bumped die hard to probe.
Field failures, application issues difficult to diagnose.
Extremely high volume, right first time, field failures not
an option.
9. PMIC Emulation
Zynq’s ARM core can emulate the host processor on a Phone or Tablet platform,
with networking, running Linux and Python + Ctypes interface to FPGA fabric.
Exposed to the same stimulus as evaluation Silicon, issues can be identified,
enabling simulation test case to be written in Python, C, and SystemVerilog.
Initial evaluation using Altera,
having also reviewed Actel and
Xilinx.
Interest from a customer required
a moved from Altera to Xilinx.
Developed an automated flow
from ASIC SystemVerilog RTL to
FPGA using Vivado, or,
Vivado with Synplify_Premier.
USB-
JTAG
Config
and
Debug
Predictor-Observer
Device under Test
Application Board
Evaluation Silicon
nOnKey,
TA,
GPIO,
VBAT,
ETC.
LDO’s,
Bucks,
GPIO,
Audio?
Probes
Emulated
LDO’s,
Bucks,
GPIO
FPGA Board
10. PMIC Emulation using Zynq
Xilinx Zedboard, Zynq XC7Z020
http://www.dialog-semiconductor.com/products/power-management/da9063
11. What can I offer?
Practical hands on design
Broad skill base
Alternative, approach
Willingness to learn
Desire to innovative
