COMPUTER FUNCTION
T S PRADEEP KUMAR
Assistant Professor (SG)
VIT University – Chennai Campus
http://www.pradeepkumar.org
tspembedded@gmail.com
Computer Specifications
Processor            Core i3
Variant              370M
Clock Speed          2.4GHz
Cache                3MB L2 Cache
System Memory        2GB DDR3
Graphics Processor   Intel HD Graphics
Hard Disk            500GB SATA Disk
Ports                RJ45, HDMI, USB, COM, ThunderBolt
Network              Wi-Fi 802.11, Bluetooth
Random Access Memory (RAM)
Processor
Cache Memory
Tuesday, March 06, 2012   PRADEEP KUMAR TS   6




Computer Function
Computer Function
• Program Counter
  • Contains the address of the next Instruction
• Instruction Register
   • Contains the address of the current instruction
• Memory Buffer Register (MBR)
  • contains the data to be written into memory or receives the data
    read from memory.
• Memory Address Register (MAR)
  • specifies the address in memory for the next read or write
Computer Function
• I/O Address register
   • specifies a particular I/O device
• IO Buffer register
   • is used for the exchange of data between an I/O module and the
     CPU.
• Memory Module
  • consists of a set of locations, defined by sequentially numbered
    addresses.
• IO Module
   • An I/O module transfers data from external devices to CPU and
     memory, and vice versa. It contains internal buffers for temporarily
     holding these data until they can be sent on..
Computer Function
• Processor-memory
  • Data may be transferred from processor to memory or from memory to
    processor.
• Processor-I/O
  • Data may be transferred to or from a peripheral device by transferring
    between the processor and an I/O module.
• Data processing
  • The processor may perform some arithmetic or logic operation on
    data.
• Control
  • An instruction may specify that the sequence of execution be altered.
    For example, the processor may fetch an instruction from location 149,
    which specifies that the next instruction be from location 182. The
    processor will remember this fact by setting the program counter to
    182.Thus, on the next fetch cycle, the instruction will be fetched from
    location 182 rather than 150.
Computer Function
Tuesday, March 06, 2012   PRADEEP KUMAR TS   11




Instruction Fetch and Execute
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Instruction Fetch and Execute
Tuesday, March 06, 2012                     PRADEEP KUMAR TS              13




Interrupts and their effects
• Classes of Interrupts
  • Program
       • Generated by some condition that occurs as a result of an instruction
         execution, such as arithmetic overflow, division by zero, attempt to
         execute an illegal machine instruction,
   • Timer
            Interrupts generated by the OS to take some special actions
   • I/O
       • Generated by the I/O Controllers like signals, errors, etc
   • Hardware Failure
       • Power failure or memory parity error
Tuesday, March 06, 2012   PRADEEP KUMAR TS   14




Interrupts and Instruction Cycle
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Interrupts and Instruction Cycle
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Interrupts and Instruction Cycle
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Sequential Interrupts
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Nested Interrupts
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Time Sequence of Multiple Interrupts
CONTINUED…..

Lecture 2 computer function

  • 1.
    COMPUTER FUNCTION T SPRADEEP KUMAR Assistant Professor (SG) VIT University – Chennai Campus http://www.pradeepkumar.org tspembedded@gmail.com
  • 2.
    Computer Specifications Processor Core i3 Variant 370M Clock Speed 2.4GHz Cache 3MB L2 Cache System Memory 2GB DDR3 Graphics Processor Intel HD Graphics Hard Disk 500GB SATA Disk Ports RJ45, HDMI, USB, COM, ThunderBolt Network Wi-Fi 802.11, Bluetooth
  • 3.
  • 4.
  • 5.
  • 6.
    Tuesday, March 06,2012 PRADEEP KUMAR TS 6 Computer Function
  • 7.
    Computer Function • ProgramCounter • Contains the address of the next Instruction • Instruction Register • Contains the address of the current instruction • Memory Buffer Register (MBR) • contains the data to be written into memory or receives the data read from memory. • Memory Address Register (MAR) • specifies the address in memory for the next read or write
  • 8.
    Computer Function • I/OAddress register • specifies a particular I/O device • IO Buffer register • is used for the exchange of data between an I/O module and the CPU. • Memory Module • consists of a set of locations, defined by sequentially numbered addresses. • IO Module • An I/O module transfers data from external devices to CPU and memory, and vice versa. It contains internal buffers for temporarily holding these data until they can be sent on..
  • 9.
    Computer Function • Processor-memory • Data may be transferred from processor to memory or from memory to processor. • Processor-I/O • Data may be transferred to or from a peripheral device by transferring between the processor and an I/O module. • Data processing • The processor may perform some arithmetic or logic operation on data. • Control • An instruction may specify that the sequence of execution be altered. For example, the processor may fetch an instruction from location 149, which specifies that the next instruction be from location 182. The processor will remember this fact by setting the program counter to 182.Thus, on the next fetch cycle, the instruction will be fetched from location 182 rather than 150.
  • 10.
  • 11.
    Tuesday, March 06,2012 PRADEEP KUMAR TS 11 Instruction Fetch and Execute
  • 12.
    Tuesday, March 06,2012 PRADEEP KUMAR TS 12 Instruction Fetch and Execute
  • 13.
    Tuesday, March 06,2012 PRADEEP KUMAR TS 13 Interrupts and their effects • Classes of Interrupts • Program • Generated by some condition that occurs as a result of an instruction execution, such as arithmetic overflow, division by zero, attempt to execute an illegal machine instruction, • Timer Interrupts generated by the OS to take some special actions • I/O • Generated by the I/O Controllers like signals, errors, etc • Hardware Failure • Power failure or memory parity error
  • 14.
    Tuesday, March 06,2012 PRADEEP KUMAR TS 14 Interrupts and Instruction Cycle
  • 15.
    Tuesday, March 06,2012 PRADEEP KUMAR TS 15 Interrupts and Instruction Cycle
  • 16.
    Tuesday, March 06,2012 PRADEEP KUMAR TS 16 Interrupts and Instruction Cycle
  • 17.
    Tuesday, March 06,2012 PRADEEP KUMAR TS 17 Sequential Interrupts
  • 18.
    Tuesday, March 06,2012 PRADEEP KUMAR TS 18 Nested Interrupts
  • 19.
    Tuesday, March 06,2012 PRADEEP KUMAR TS 19 Time Sequence of Multiple Interrupts
  • 20.