•Designed a two stage OPAMP with a current mirror amplifier and a second CS stage along with miller compensation to provide sufficient Phase margin for stability.The circuit is also provided with temperature independent self-biased startup circuit.
•Our OPAMP exhibited a gain of 82.74dB, OVSR of 1.57V, Slew rate of 9.79V/us, Phase margin of 60 deg, GBW of 18.6 MHz, CMRR of 88.473dB, Power dissipation of 0.22mW with a 1.8V power supply.
•Designed a two stage OPAMP with a current mirror amplifier and a second CS stage along with miller compensation to provide sufficient Phase margin for stability.The circuit is also provided with temperature independent self-biased startup circuit.
•Our OPAMP exhibited a gain of 82.74dB, OVSR of 1.57V, Slew rate of 9.79V/us, Phase margin of 60 deg, GBW of 18.6 MHz, CMRR of 88.473dB, Power dissipation of 0.22mW with a 1.8V power supply.
PARASITIC-AWARE FULL PHYSICAL CHIP DESIGN OF LNA RFIC AT 2.45GHZ USING IBM 13...Ilango Jeyasubramanian
• Analyzed and designed a single stage cascoded LNA with Q-based calculation for desired input matching, output matching, power gain, IIP3 and Noise figure, including all the parasitics in the on-chip and off-chip components using SpectreRF simulations.
• Synthesized the LNA layout for on-chip components with spiral inductor, MOS capacitor, MIM capacitor and Bond-pads with ESD protections.
• Our LNA exhibited a noise figure of 1.23dB, linear gain of 18.54 dB, IIP3 of -4.60dbm, S11 of -31.11db, S22 of -24.91db with the operating range between 2.4-2.5GHZ along with 10% variation tolerance.
PARASITIC-AWARE FULL PHYSICAL CHIP DESIGN OF LNA RFIC AT 2.45GHZ USING IBM 13...Ilango Jeyasubramanian
• Analyzed and designed a single stage cascoded LNA with Q-based calculation for desired input matching, output matching, power gain, IIP3 and Noise figure, including all the parasitics in the on-chip and off-chip components using SpectreRF simulations.
• Synthesized the LNA layout for on-chip components with spiral inductor, MOS capacitor, MIM capacitor and Bond-pads with ESD protections.
• Our LNA exhibited a noise figure of 1.23dB, linear gain of 18.54 dB, IIP3 of -4.60dbm, S11 of -31.11db, S22 of -24.91db with the operating range between 2.4-2.5GHZ along with 10% variation tolerance.
Low power is one of the key research area in today’s electronic industry. Need of low power has created a major pattern shift in the field of electronics where power dissipation is equally important as area, performance etc. Several low power portable electronic equipments, low voltage design techniques have been developed and have driven analog designers to create techniques eg. Self cascode mosfet and stacking technique. For this aim in mind we designed a Folded Cascode using low power techniques and analyzed its various properties through the Spice simulations for 0.13 micron CMOS technology from TSMC and the supply voltage 1.8V.
Converter Transformers manufactured to the Slovenian RailwaysJuso Ikanovic
The paper contains an overview of the most significant
technical characteristics of converter transformers
manufactured to modernize of Slovenian Railways. The main
features and characteristics of this type of the traction drives
with various intersected winding configurations are described.
The referenced projects include the first application of axial
winding crossing, i.e. a technological innovation resolving the
strong magnetic coupling requirement of low-voltage
windings. The solution is referred to as an intersected winding.
With one, two and three winding crossings coupling factors of
0.920 and 0.967 are achieved. The results meet the
specifications, of the SIST EN standard.
Comparison of time-domain S-parameters of RG58 cable computed by Theory, CST,...Piero Belforte
A comparison of time-domain S-parameters of a RG58 cable computed by different methods including Theory, CST simulator , SPICE (MC10) and DWS simulators. The good agreement among methods is shown as well as DWS advantages for fast modeling and simualtions of lossy lines using both circuital, BTM and hybrid methods.
Design consideration of an mmc hvdc system based on 4500 v:4000a emitter turn...Ghazal Falahi
Excessive power loss is a major concern in high voltage and high power applications and is considered one of the main drawbacks of VSC-HVDC system when compared with traditional HVDC system based on thyristor technology. This is primarily caused by high switching loss associated with switching devices used in the VSC-HVDC. This issue can be largely addressed by using the emerging MMC-HVDC topology, which requires much lower switching frequency than traditional VSC-HVDC. Emitter turn-off thyristor (ETO) is one of the best high power switching devices packed with many advanced features. ETO thyristor based MMC-HVDC system is therefore an extremely attractive choice for ultra-high voltage and high power HVDCs. This paper discusses the operation principle of ETO based MMC-HVDC as well as its design and loss comparison with other solutions.
On the Impact of Timer Resolution in the Efficiency Optimization of Synchrono...IJPEDS-IAES
Excessive dead time in complementary switches causes significant energy losses in DC-DC
power conversion. The optimization of dead time prevents the degradation of overall efficiency
by minimizing the body diode conduction of power switches and, as a consequence,
also reduces reverse recovery losses. The present work aims at analyzing the influence of
one of the most important characteristics of a digital controller, the timer resolution, in the
context of dead-time optimization for synchronous buck converters. In specific, the analysis
quantifies the efficiency dependency on the timer resolution, in a parameter set that comprises
duty-cycle and dead-time, and also converter frequency and analog-to-digital converter
accuracy. Based on a sensorless optimization strategy, the relationship between all
these limiting factors is described, such as the number of bits of timer and analog-to-digital
converter. To validate our approach experimental results are provided using a 12-to-1.8V
DC-DC converter, controlled by low- and high-resolution pulse-width modulation signals
generated with an XMC4200 microcontroller from Infineon Technologies. The measured
results are consistent with our analysis, which predicts the power efficiency improvements
not only with a fixed dead time approach, but also with the increment of timer resolution.