Excessive power loss is a major concern in high voltage and high power applications and is considered one of the main drawbacks of VSC-HVDC system when compared with traditional HVDC system based on thyristor technology. This is primarily caused by high switching loss associated with switching devices used in the VSC-HVDC. This issue can be largely addressed by using the emerging MMC-HVDC topology, which requires much lower switching frequency than traditional VSC-HVDC. Emitter turn-off thyristor (ETO) is one of the best high power switching devices packed with many advanced features. ETO thyristor based MMC-HVDC system is therefore an extremely attractive choice for ultra-high voltage and high power HVDCs. This paper discusses the operation principle of ETO based MMC-HVDC as well as its design and loss comparison with other solutions.
Thd minimization of modular multilevel converter with unequal dc valuesGhazal Falahi
Different modulation techniques used to control multilevel converters can be classified based on the selected converter topology and optimization goals. Among all proposed modulation methods low switching frequency modulation techniques are very popular for multilevel converters yet non-real time low switching frequency methods cannot be applied to multilevel converters with unequal or varying DC values because these modulation techniques rely on look up tables and the size of look up tables will be huge in this case. This paper proposes a new modular multilevel converter (MMC) structure with unequal DC values. Some well-known low switching frequency modulation techniques and the commonly used PWM based methods are compared and using the new low switching frequency modulation technique called minimal total harmonic distortion (THD) modulation for MMC with unequal DC values is proposed. The PSCAD simulation results show that the new converter topology with unequal DC values has much lower THD compared to the typical MMC. Modulation algorithm is implemented in digital signal processor (DSP) and controller hardware in the loop (CHIL) implementation in RTDS verifies the real-time performance of the algorithm.
Control of modular multilevel converter based hvdc systems during asymmetrica...Ghazal Falahi
Modular multilevel converter (MMC) is a relatively new and promising topology for HVDC systems. HVDC systems should remain connected during grid faults and isolate the fault. This paper studies the dynamic performance of transformer-less MMC integrated HVDC systems during unbalanced conditions and asymmetrical grid faults. It proposes a new control technique to improve unbalanced system’s performance. The objective of the proposed controller is eliminating negative and zero sequence currents and to improve the overall performance. The controller calculates zero and negative sequence reference voltages and eliminates zero and negative sequence currents without using any current regulator. Therefore the controller is very fast and robust. The effectiveness of the proposed control technique has been validated by EMTDC /PSCAD simulations.
Low voltage ride through control of modular multilevel converter based hvdc s...Ghazal Falahi
Low Voltage Ride Through (LVRT) is an important grid requirement for Voltage Source Converter (VSC) based HVDC links. This paper studies the performance of the modular multilevel converter (MMC) VSC based HVDC systems during faults or voltage dips and proposes a new control strategy to improve the LVRT performance. The proposed algorithm controls the system to generate the required active and reactive powers that are calculated mathematically based on the ratings of the MMC-HVDC system and LVRT requirements. The injected active and reactive power values obey the LVRT guidelines and are adaptable to different grid codes. The mathematical calculations are presented and EMTDC/PSCAD simulation evaluates the performance of the proposed method.
Design, Modeling and control of modular multilevel converters (MMC) based hvd...Ghazal Falahi
Modular multilevel converter (MMC) is a relatively new and promising topology, which has gained a lot of interest in industry in the recent years due to its modular design and easy adaption for applications that require different power and voltage level, such as power transmission through HVDC. This presentation investigates the operation of MMC based HVDC systems and proposes new solutions to improve the performance of the system by using new devices and improving the control strategies.
Performance improvement of parallel active power filters using droop control ...Ghazal Falahi
In this paper, a new method based on droop control scheme is proposed for controlling parallel operation of active filters. The harmonic components of the load current are extracted by an enhanced phase-locked loop (EPLL). In the parallel group, each filter operates as a conductance and the harmonic workload is shared among them. A droop relationship between the conductance and non-fundamental apparent power controls the operation of each unit. The non-fundamental apparent power has been calculated based on IEEE Std 1459. Principles of operation are explained in this paper and simulation results which are presented approve the effectiveness of this method. The results indicate a significant reduction in Total Harmonic Distortion (THD) in a rectifier application.
The power electronics device which converts DC power to AC power at required output voltage and frequency level is known as inverter. Multilevel inverter is to synthesize a near sinusoidal voltage from several levels of dc voltages. In order to maintain the different voltage levels at appropriate intervals, the conduction time intervals of MOSFETS have been maintained by controlling the pulse width of gating pulses. In this paper single phase to three phase power conversion using PWM technique. The simulation is carried out in MATLAB/Simulink environment which demonstrate the feasibility of proposed scheme.
Thd minimization of modular multilevel converter with unequal dc valuesGhazal Falahi
Different modulation techniques used to control multilevel converters can be classified based on the selected converter topology and optimization goals. Among all proposed modulation methods low switching frequency modulation techniques are very popular for multilevel converters yet non-real time low switching frequency methods cannot be applied to multilevel converters with unequal or varying DC values because these modulation techniques rely on look up tables and the size of look up tables will be huge in this case. This paper proposes a new modular multilevel converter (MMC) structure with unequal DC values. Some well-known low switching frequency modulation techniques and the commonly used PWM based methods are compared and using the new low switching frequency modulation technique called minimal total harmonic distortion (THD) modulation for MMC with unequal DC values is proposed. The PSCAD simulation results show that the new converter topology with unequal DC values has much lower THD compared to the typical MMC. Modulation algorithm is implemented in digital signal processor (DSP) and controller hardware in the loop (CHIL) implementation in RTDS verifies the real-time performance of the algorithm.
Control of modular multilevel converter based hvdc systems during asymmetrica...Ghazal Falahi
Modular multilevel converter (MMC) is a relatively new and promising topology for HVDC systems. HVDC systems should remain connected during grid faults and isolate the fault. This paper studies the dynamic performance of transformer-less MMC integrated HVDC systems during unbalanced conditions and asymmetrical grid faults. It proposes a new control technique to improve unbalanced system’s performance. The objective of the proposed controller is eliminating negative and zero sequence currents and to improve the overall performance. The controller calculates zero and negative sequence reference voltages and eliminates zero and negative sequence currents without using any current regulator. Therefore the controller is very fast and robust. The effectiveness of the proposed control technique has been validated by EMTDC /PSCAD simulations.
Low voltage ride through control of modular multilevel converter based hvdc s...Ghazal Falahi
Low Voltage Ride Through (LVRT) is an important grid requirement for Voltage Source Converter (VSC) based HVDC links. This paper studies the performance of the modular multilevel converter (MMC) VSC based HVDC systems during faults or voltage dips and proposes a new control strategy to improve the LVRT performance. The proposed algorithm controls the system to generate the required active and reactive powers that are calculated mathematically based on the ratings of the MMC-HVDC system and LVRT requirements. The injected active and reactive power values obey the LVRT guidelines and are adaptable to different grid codes. The mathematical calculations are presented and EMTDC/PSCAD simulation evaluates the performance of the proposed method.
Design, Modeling and control of modular multilevel converters (MMC) based hvd...Ghazal Falahi
Modular multilevel converter (MMC) is a relatively new and promising topology, which has gained a lot of interest in industry in the recent years due to its modular design and easy adaption for applications that require different power and voltage level, such as power transmission through HVDC. This presentation investigates the operation of MMC based HVDC systems and proposes new solutions to improve the performance of the system by using new devices and improving the control strategies.
Performance improvement of parallel active power filters using droop control ...Ghazal Falahi
In this paper, a new method based on droop control scheme is proposed for controlling parallel operation of active filters. The harmonic components of the load current are extracted by an enhanced phase-locked loop (EPLL). In the parallel group, each filter operates as a conductance and the harmonic workload is shared among them. A droop relationship between the conductance and non-fundamental apparent power controls the operation of each unit. The non-fundamental apparent power has been calculated based on IEEE Std 1459. Principles of operation are explained in this paper and simulation results which are presented approve the effectiveness of this method. The results indicate a significant reduction in Total Harmonic Distortion (THD) in a rectifier application.
The power electronics device which converts DC power to AC power at required output voltage and frequency level is known as inverter. Multilevel inverter is to synthesize a near sinusoidal voltage from several levels of dc voltages. In order to maintain the different voltage levels at appropriate intervals, the conduction time intervals of MOSFETS have been maintained by controlling the pulse width of gating pulses. In this paper single phase to three phase power conversion using PWM technique. The simulation is carried out in MATLAB/Simulink environment which demonstrate the feasibility of proposed scheme.
Modular Multilevel Converters Part-I: A Review on Topologies, Modulation, Mod...IJPEDS-IAES
This article is devoted to the Multi-level inverters review and in particular to the form and function of modular multilevel inverters (MMI), with their different topologies, modulation, modeling and control schemes Detailed analysis with their functions of MMI has been made in comprehensive manner with existing literature available till date. All existing methods are compared in detail with proposal for the best methods available. The article has made strategic conclusions on MMI to make the system more robust in operation with less complexity in design and control.
This paper addresses a novel approach for designing and modeling of the isolated
flyback converter. Modeling is done without parasitic as well as with parasitic components.
A detailed analysis, simulation and different control strategy are conferred for flyback
converter in continuous conduction mode (CCM). To verify the design and modeling at
primary stage, study of the converter is practiced in CCM operation for input AC voltage
230V at 50Hz and output DC voltage of 5V and 50W output power rating using PSIM 6.0
software. Simulation result shows a little ripple in output of the converter in open loop. Finally
in order to evaluate the system as well as response of the controller, flyback converter is
simulated using MATLAB. This work, highlighting the modeling when the system have
transformer and facilitate designers to go for it when they need one or more than one output
for a given application upto 150W
Torque Ripple Minimization of a BLDC Motor Drive by Using Electronic Commutat...AI Publications
Brushless DC motors are having a major problem with harmonics in torque. The variations in speed and production of noise should be minimized by using proper topologies. BLDC motors have been gaining attention from different Industrial and domestic appliance manufacturers, because of their high efficiency, high power density and easy maintenance and low cost. This paper presents a three phase BLDC motor with low cost drive to be driven without DC link capacitor. The proposed technique uses an electronic commutation and operates the machine exclusive of the intermediate DC link capacitor. The designing of Brushless DC motor drive system along with control system for torque ripple minimization, speed controller and current controllers are presented using MATLAB / SIMULINK and results are evaluated.
Digital Current Mode Controller for Buck ConverterIJMREMJournal
Power electronics applications are widely used in different fields of engineering like computer,
Telecommunication, electrical power and Mechanical), one of the most useful power electronics converters is
DC-DC buck converter. Owing to its numerous applications, its performance needs to be improved through a
suitable controller. In this Paper, A digital current mode controller is proposed and implemented for Buck
converter. Proposed current mode control technique is simulated in MATLAB/SIMULINK and results are
validated through hardware implementation. Both simulation and experimental analysis show effectiveness of
the proposed controller.
PID Controller Response to Set-Point Change in DC-DC Converter ControlIAES-IJPEDS
Power converter operations and efficiency is affected by variation in supply
voltage, loads current, circuit elements, ageing and temperature. To meet the
objective of tight voltage regulation, power converters circuit module and the
control unit must be robust to reject disturbances arising from supply, load
variation and changes in circuit elements. PID controller has been the most
widely used in power converter control. This paper presents studies of
robustness of PID controller tuning methods to step changes in the set point
and disturbance rejection in power converter control. A DC-DC boost
converter was modelled using averaged state-space mothod and PID
controllers were designed with five different tuning methods. The study
reveals the transient response and disturbance rejection capability of each
tuning methods for their suitability in power supply design applications.
discusses about the reduction of commutation torque ripple in BLDC motor and various convention methods and the proposed method for 2 level inverter and 3 level inverter
Common Mode Voltage Control in Three Level Diode Clamped InverterIJERA Editor
This paper presents simple sinusoidal PWM technique to reduced common mode voltage (CMV) at output terminal of the inverter. Multilevel inverter (MLI) is more suitable in high & medium power application, CMV is produced at the time of operation in output terminal of inverter. In this paper, an approach to reduced CMV at output terminal of MLI by using SPWM technique in three level diode clamped inverter (DCMLI) is proposed. A good transaction between the quality of the output voltage & the magnitude of CMV is achieved in this paper. The paper presents phase opposition & phase opposition disposition SPWM technique to reduced CMV in DCMLI. Simulation & experimental result presented to confirm the effectiveness of the proposed technique to control CMV.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Modular Multilevel Converters Part-I: A Review on Topologies, Modulation, Mod...IJPEDS-IAES
This article is devoted to the Multi-level inverters review and in particular to the form and function of modular multilevel inverters (MMI), with their different topologies, modulation, modeling and control schemes Detailed analysis with their functions of MMI has been made in comprehensive manner with existing literature available till date. All existing methods are compared in detail with proposal for the best methods available. The article has made strategic conclusions on MMI to make the system more robust in operation with less complexity in design and control.
This paper addresses a novel approach for designing and modeling of the isolated
flyback converter. Modeling is done without parasitic as well as with parasitic components.
A detailed analysis, simulation and different control strategy are conferred for flyback
converter in continuous conduction mode (CCM). To verify the design and modeling at
primary stage, study of the converter is practiced in CCM operation for input AC voltage
230V at 50Hz and output DC voltage of 5V and 50W output power rating using PSIM 6.0
software. Simulation result shows a little ripple in output of the converter in open loop. Finally
in order to evaluate the system as well as response of the controller, flyback converter is
simulated using MATLAB. This work, highlighting the modeling when the system have
transformer and facilitate designers to go for it when they need one or more than one output
for a given application upto 150W
Torque Ripple Minimization of a BLDC Motor Drive by Using Electronic Commutat...AI Publications
Brushless DC motors are having a major problem with harmonics in torque. The variations in speed and production of noise should be minimized by using proper topologies. BLDC motors have been gaining attention from different Industrial and domestic appliance manufacturers, because of their high efficiency, high power density and easy maintenance and low cost. This paper presents a three phase BLDC motor with low cost drive to be driven without DC link capacitor. The proposed technique uses an electronic commutation and operates the machine exclusive of the intermediate DC link capacitor. The designing of Brushless DC motor drive system along with control system for torque ripple minimization, speed controller and current controllers are presented using MATLAB / SIMULINK and results are evaluated.
Digital Current Mode Controller for Buck ConverterIJMREMJournal
Power electronics applications are widely used in different fields of engineering like computer,
Telecommunication, electrical power and Mechanical), one of the most useful power electronics converters is
DC-DC buck converter. Owing to its numerous applications, its performance needs to be improved through a
suitable controller. In this Paper, A digital current mode controller is proposed and implemented for Buck
converter. Proposed current mode control technique is simulated in MATLAB/SIMULINK and results are
validated through hardware implementation. Both simulation and experimental analysis show effectiveness of
the proposed controller.
PID Controller Response to Set-Point Change in DC-DC Converter ControlIAES-IJPEDS
Power converter operations and efficiency is affected by variation in supply
voltage, loads current, circuit elements, ageing and temperature. To meet the
objective of tight voltage regulation, power converters circuit module and the
control unit must be robust to reject disturbances arising from supply, load
variation and changes in circuit elements. PID controller has been the most
widely used in power converter control. This paper presents studies of
robustness of PID controller tuning methods to step changes in the set point
and disturbance rejection in power converter control. A DC-DC boost
converter was modelled using averaged state-space mothod and PID
controllers were designed with five different tuning methods. The study
reveals the transient response and disturbance rejection capability of each
tuning methods for their suitability in power supply design applications.
discusses about the reduction of commutation torque ripple in BLDC motor and various convention methods and the proposed method for 2 level inverter and 3 level inverter
Common Mode Voltage Control in Three Level Diode Clamped InverterIJERA Editor
This paper presents simple sinusoidal PWM technique to reduced common mode voltage (CMV) at output terminal of the inverter. Multilevel inverter (MLI) is more suitable in high & medium power application, CMV is produced at the time of operation in output terminal of inverter. In this paper, an approach to reduced CMV at output terminal of MLI by using SPWM technique in three level diode clamped inverter (DCMLI) is proposed. A good transaction between the quality of the output voltage & the magnitude of CMV is achieved in this paper. The paper presents phase opposition & phase opposition disposition SPWM technique to reduced CMV in DCMLI. Simulation & experimental result presented to confirm the effectiveness of the proposed technique to control CMV.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Preventing circulating current in parallel generator applicationsMirus International
As the need for secure and reliable electricity has gown, many opportunities for distributed generation have appeared. Diesel, Natural Gas, Biofuel or other generators used for these applications often run in parallel with themselves or with Utility transformers. This can result in high levels of triple frequency (180Hz in 60Hz systems) circulating current in the common neutrals or ground connections. These circulating currents can cause overheating in the generator windings and false tripping of overcurrent protection devices, especially ground fault schemes.
Mirus’ GenLink Dissimilar Pitch Neutral Limiter (DPNL) is a uniquely wound, multiple coil reactor which can be very effective in blocking the flow of circulating current without negatively impacting system fault levels.
MIRUS’ President & CEO, Tony Hoevenaars P.Eng, covered how paralleling generators can lead to very high neutral circulating currents and what can be done to control them. The problem is particularly evident when the generators are built with dissimilar pitches but is also very common when generators are paralleled with Utility transformers for Distributed Generation.
In the webinar, attendees learned about:
- Understanding Generator Pitch and Harmonics
- How Circulating Current Problems Start
- Effective Method for Reducing Circulating Current
- Adding Circulating Path Impedance without Effecting Ground Fault Path
- Sizing Neutral Blocking Solution for Specific Applications
- Real-World Case Studies
The OP1200, Lab-Scale Modular Multilevel Converters Test Bench, is dedicated to the hardware verification of new control algorithms for new and existing power electronic converter topologies. It is used for experimental work on converter interactions and network control.
Design and Simulation of Efficient DC-DC Converter Topology for a Solar PV Mo...Sajin Ismail
Modulated Integrated Converter systems are considered to be the new and global turning point in the field of
Solar PV systems. These converters are highly recognised for its modular size and compact nature and they are supposed to
be attached directly with each PV module and since one PV module is having the power rating of a few watts ranging from
0-500Ws, the design rating would be in the same range and thus the most vital condition in such a design is efficiency
under these relatively low loads. In this paper an isolated interleaved boost converter topology is considered in the DC-DC
section and which is designed and simulated for a specific power rating (250W) and the efficiency is analysed with varying
load conditions and compared with the target efficiency of the system.
Comparative performance of modular with cascaded H-bridge three level invertersIJECEIAES
The conventional two-level inverter becomes no longer has the ability to cope with the high-power requirement, so this paper discusses two very common topologies of multilevel inverter like modular multilevel converter (MMC) and cascaded H-bridge (CHB) multilevel inverter for induction motor drive applications. This work attempts to investigate the comparison between MMC and CHB. The comparison is done in aspects of the configuration, concept of operation, advantages and disadvantages, the comparison is also considering output voltage (line to line) waveform, total harmonic distortion (THD) of the output line voltage waveform and the current drawn by both inverters. The performance of the inverters under carrier-based pulse width modulation (PWM) technique and mainly in-phase disposition (IPD), level shifted pulse width modulation is viewed. The paper discusses the comparison between the two multilevel inverters (MLIs) with motor drive applications especially induction motor. The operation of the motor is studied under certain value of load torque. The simulation results for the induction motor with the two inverters (modular multilevel and Cascaded H-bride) for three numbers of levels using MATLAB/Simulink are provided). The obtained results are encouraging and promising especially in the improvement of the THD% results.
Closed Loop Analysis of Multilevel Inverter Fed Drives IJPEDS-IAES
This paper deals with the simulation and implementation of multilevel inverter for drives application. Here the focuses will be onimproving the efficiency of the multilevel inverter and quality of output voltage waveform. The circuit is developed towards high efficiency, high performance, and low cost, simple control scheme. Harmonics Elimination was implemented to reduce the Total Harmonics Distortion (THD) value which is achieved by selecting appropriate switching angles. In this paper to determine the performance of rectifier, steady state analysis is done. Furthermore, the merits of multilevel inverter topology are inherited.Closed loop control is done to analysis the stability of the system.
Phase-Shifted Full-Bridge Zero Voltage Switching DC-DC Converter Design with ...IJECEIAES
Design of phase-shifted full bridge zero voltage switching DC-DC converter has been very challenging due to circuit parasitic effect on the system dynamics. This paper presents steady-state analysis and iterative approach for the systemic design of phase-shifted full bridge DC-DC converter with improved dynamic performance and satisfactory operational requirement in terms of zero-voltage switching range, operating switching frequency and switching resonance. A 3 kW DC-DC converter is designed using the iterative design approach and the system dynamics performance was investigated in the MATLAB/Simulink environment. The converter zerovoltage switching simulation results were satisfactory with 90% efficiency under full load condition.
DESIGN, SIMULATION, IMPLEMENTATION AND CONTROL OF PLC BASED INTEGRAL CYCLE CO...IAEME Publication
The Class of ac power controllers consists of Solid State Power Controller (SSPC) which connects and disconnects the load to the supply according to the required power. Two important voltage control techniques are commonly used for heating power control in ac power controller are Phase Control Switching and Integral Cycle Control. In case that a PCS is used for the resistive load, it can produce higher order harmonics and heavy inrush current while switching on in a cold start. In the proposed method, a disadvantage of phase controlled is removed. In this paper authors have reported simulated results, design methodology, implementation and Control of PLC Based Integral Cycle Control (ICC) method for Resistance Spot Welding (RSW).
This paper presents parameters analysis of 4-level capacitor-clamped boost converter with hard-switching and soft-switching implementation. Principally, by considering the selected circuit structure of the 4-level capacitor-clamped boost converter and appropriate pulse width modulation (PWM) switching strategy, the overall converter volume able to be reduced. Specifically, phase-shifted of 120° of each switching signal is applied in the 4-level capacitor-clamped boost converter in order to increase the inductor current ripple frequency, thus the charging and discharging times of the inductor is reduced. Besides, volume of converters is greatly reduced if very high switching frequency is considered. However, it causes increasing of semiconductor losses and consequently the converter efficiency is affected. The results show that the efficiency of 2-level conventional boost converter and 4-level capacitor-clamped boost converter are 98.59% and 97.67%, respectively in hard-switching technique, and 99.31% and 98.15%, respectively in soft-switching technique. Therefore, by applying soft-switching technique, switching loss of the semiconductor devices is greatly minimized although high switching frequency is applied. In this study, passive lossless snubber circuit is selected for the soft-switching implementation in the 4-level capacitor-clamped boost converter. Based on the simulation results, the switching loss is approximately eliminated by applying soft-switching technique compared to the hard-switching technique implementation.
Simulation of 3-phase matrix converter using space vector modulationIJECEIAES
This paper illustrates the simulation of 3-phase matrix converter using Space Vector Modulation (SVM). Variable AC output voltage engendered using matrix converter with bidirectional power switches controlled by appropriate switching pulse. The conventional PWM converter engenders switching common mode voltage across the load system terminals, which cause to common mode current and its leads to bearing failure in load drive. These problems can be rectified using SVM and which minimize the effect on the harmonic fluctuation in AC output voltage and stress on the power switch is reduced using bidirectional switch for proposed 3-phase matrix converter. The simulation results have been presented to validate the proposed system using matlab / simulink.
This paper presents a novel simplied PWM technique to drive switched capacitor type multi-level inverter fed from isolated type DC-DC converter for distributed generation. Distributed generation (DG) is renowned power generation at point of utility with no environmental aects and reduces transmission line losses. Photo-voltaic system is considered as renewable energy source for DG and the low voltage from PV system is boosted to required voltage using an isolated type single-input multi-output (SIMO) DC-DC converter. DC output from isolated SIMO DC-DC converter is fed to switched capacitor type multi-level inverter (SC-MLI) to feed the AC load. Isolated SIMO DC-DC converter apart from boosting the DG output voltage, also eliminates the problem of voltage unbalancing in SC-MLI topology. Closed loop operation of SIMO DC-DC converter employs only single PI controller instead of three controllers was presented in this paper. Modes of operation of SC-MLI and Novel PWM switching pattern was explained. Simulation of proposed system was developed using MATLAB/SIMULINK software. The prototype was developed for the proposed system and hardware results are also shown.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Study and implementation of comparator in cmos 50 nm technologyeSAT Journals
Abstract This paper describes the comparator circuits used in FLASH Analog to digital converter (ADC). The performance of FLASH ADC is greatly influenced by the choice of comparator. In this paper, first a single ended “Threshold Inverter Quantizer” (TIQ) is presented. The TIQ comparator is based on a CMOS inverter cell, in which voltage transfer characteristics (VTC) are changed by systematic transistor sizing. However, TIQ comparator is very sensitive to power supply noise. Another comparator circuit presented in this paper is “Two stage open loop comparator”. It is implemented in 50 nm CMOS Technology. Pre-simulation of comparator is done in LT-Spice and post layout simulation is done in Microwind 3.1. Keywords: CMOS, Comparator, TIQ (Threshold Inverter Quantizer), LT-Spice.
Similar to Design consideration of an mmc hvdc system based on 4500 v:4000a emitter turn-off (eto) thyristor (20)
Immunizing Image Classifiers Against Localized Adversary Attacksgerogepatton
This paper addresses the vulnerability of deep learning models, particularly convolutional neural networks
(CNN)s, to adversarial attacks and presents a proactive training technique designed to counter them. We
introduce a novel volumization algorithm, which transforms 2D images into 3D volumetric representations.
When combined with 3D convolution and deep curriculum learning optimization (CLO), itsignificantly improves
the immunity of models against localized universal attacks by up to 40%. We evaluate our proposed approach
using contemporary CNN architectures and the modified Canadian Institute for Advanced Research (CIFAR-10
and CIFAR-100) and ImageNet Large Scale Visual Recognition Challenge (ILSVRC12) datasets, showcasing
accuracy improvements over previous techniques. The results indicate that the combination of the volumetric
input and curriculum learning holds significant promise for mitigating adversarial attacks without necessitating
adversary training.
Hierarchical Digital Twin of a Naval Power SystemKerry Sado
A hierarchical digital twin of a Naval DC power system has been developed and experimentally verified. Similar to other state-of-the-art digital twins, this technology creates a digital replica of the physical system executed in real-time or faster, which can modify hardware controls. However, its advantage stems from distributing computational efforts by utilizing a hierarchical structure composed of lower-level digital twin blocks and a higher-level system digital twin. Each digital twin block is associated with a physical subsystem of the hardware and communicates with a singular system digital twin, which creates a system-level response. By extracting information from each level of the hierarchy, power system controls of the hardware were reconfigured autonomously. This hierarchical digital twin development offers several advantages over other digital twins, particularly in the field of naval power systems. The hierarchical structure allows for greater computational efficiency and scalability while the ability to autonomously reconfigure hardware controls offers increased flexibility and responsiveness. The hierarchical decomposition and models utilized were well aligned with the physical twin, as indicated by the maximum deviations between the developed digital twin hierarchy and the hardware.
Student information management system project report ii.pdfKamal Acharya
Our project explains about the student management. This project mainly explains the various actions related to student details. This project shows some ease in adding, editing and deleting the student details. It also provides a less time consuming process for viewing, adding, editing and deleting the marks of the students.
NUMERICAL SIMULATIONS OF HEAT AND MASS TRANSFER IN CONDENSING HEAT EXCHANGERS...ssuser7dcef0
Power plants release a large amount of water vapor into the
atmosphere through the stack. The flue gas can be a potential
source for obtaining much needed cooling water for a power
plant. If a power plant could recover and reuse a portion of this
moisture, it could reduce its total cooling water intake
requirement. One of the most practical way to recover water
from flue gas is to use a condensing heat exchanger. The power
plant could also recover latent heat due to condensation as well
as sensible heat due to lowering the flue gas exit temperature.
Additionally, harmful acids released from the stack can be
reduced in a condensing heat exchanger by acid condensation. reduced in a condensing heat exchanger by acid condensation.
Condensation of vapors in flue gas is a complicated
phenomenon since heat and mass transfer of water vapor and
various acids simultaneously occur in the presence of noncondensable
gases such as nitrogen and oxygen. Design of a
condenser depends on the knowledge and understanding of the
heat and mass transfer processes. A computer program for
numerical simulations of water (H2O) and sulfuric acid (H2SO4)
condensation in a flue gas condensing heat exchanger was
developed using MATLAB. Governing equations based on
mass and energy balances for the system were derived to
predict variables such as flue gas exit temperature, cooling
water outlet temperature, mole fraction and condensation rates
of water and sulfuric acid vapors. The equations were solved
using an iterative solution technique with calculations of heat
and mass transfer coefficients and physical properties.
CW RADAR, FMCW RADAR, FMCW ALTIMETER, AND THEIR PARAMETERSveerababupersonal22
It consists of cw radar and fmcw radar ,range measurement,if amplifier and fmcw altimeterThe CW radar operates using continuous wave transmission, while the FMCW radar employs frequency-modulated continuous wave technology. Range measurement is a crucial aspect of radar systems, providing information about the distance to a target. The IF amplifier plays a key role in signal processing, amplifying intermediate frequency signals for further analysis. The FMCW altimeter utilizes frequency-modulated continuous wave technology to accurately measure altitude above a reference point.
6th International Conference on Machine Learning & Applications (CMLA 2024)ClaraZara1
6th International Conference on Machine Learning & Applications (CMLA 2024) will provide an excellent international forum for sharing knowledge and results in theory, methodology and applications of on Machine Learning & Applications.
2. Figure 1. Principal circuit and picture of Gen-4 ET
III. ETO BASED MMC STRUCTURE A
PRINCIPAL
The equivalent circuit of a three-phase MM
the ETO based sub-module is shown in
based sub-module is basically a half bridge
ETO switches and a clamp circuit. Equatio
arm voltage of MMC based of sub-modu
and their switching states.
The arm current in MMC is derived from
DC current and the AC current. Also the re
arm voltage is derived from (3) assu
modulation [2, 3].
Figure 2. Modular multilevel converter, ETO
Where is the current phase angle. Switch
module depends by the arm current and
TO 4.5KV/4KA
AND OPERATION
MC converter and
Figure 2. ETO
e converter using
on (1) defines the
ules DC voltages
(1)
(2) based on the
ference value for
uming a cosine
(2)
(3)
sub-modules
hing state of sub-
d reference arm
voltage. The upper arm current d
points of zero crossing in one cycle
t3
. When the arm current is positive
diode D2
can conduct and when the
t2
to t1
, switch S2
or diode D1
can con
voltage will define the active device
If arm current is positive and refere
is decreasing, t3
to 0, sub-module
conducts and when the reference ar
0 to t2
, sub-module is inserted
Similarly when the arm current is
inserted when the reference arm vo
(t1
+t2
)/2, so diode D1
conducts and
when the reference arm voltage is d
so switch S2
conducts. The s
conduction intervals change fo
modulation index (m) and angle ( ).
IV. MODULATION AND C
BALANCING
A modified nearest level modulatio
to operate ETO based MMC. To i
of fundamental frequency base
calculation of switching angels h
method. The algorithm inputs th
waveform from the system contr
switching angels such that the g
MMC is very close to the reference
Figure 3 shows a zoomed in p
waveform and discrete steps gen
modules. Real-time modulation has
is the generation of the switching an
is the capacitor voltage balancin
capacitor voltage balancing, indiv
are measured at each controller ti
controller. The measured voltages
switching instant ( i) and the swi
with respect to the index of sorted c
Sub-modules are inserted or b
switching state of two switching dev
Two switches are complementary a
each device depends on the directio
reference modulation waveform.
diode (S1 or D1) conduct the s
defined by (2) has three
e referred to as t1
, t2
, and
, t3
to t2
, only switch S1
or
e arm current is negative,
nduct. The reference arm
e in each interval.
ence value of arm voltage
is bypassed so diode D2
rm voltage is increasing,
so switch S1
conducts.
negative, sub-module is
oltage is increasing, t2
to
sub-module is bypassed
decreasing, (t1
+t2
)/2 to t1
,
switching instants and
or different values of
(4)
CAPACITOR VOLTAGE
G
n (NLM) method is used
mprove the performance
ed NLM, a real-time
has been added to the
he reference modulation
oller and calculates the
generated waveform by
waveform.
ortion of the reference
nerated by MMC sub-
s two parts; the first part
ngels and the second part
ng. In order to achieve
vidual capacitor voltages
ime-step and sent to the
are sorted and at each
tching decision is made
capacitor voltage matrix.
ypassed based on the
vices in each half bridge.
and the switching state of
on of the arm current and
When upper switch or
sub-module capacitor is
3463
3. inserted in the arm and conduction of the l
or D2) results in bypassing the sub-module c
The sub-modules are in charging or d
according to the direction of current flow
sub-module. When the upper device is con
module capacitor is inserted into the arm
Figure 4 when D1 is conducting the sub-m
will be in charging state. The sub-modul
discharge when S1 conducts. Thus to ac
when the sub-modules are in charging sta
lowest capacitor voltages have to turn
discharging condition the capacitors with
have higher priority.
Figure 5 summarizes the operation of the pr
modulation technique. In the proposed co
remaining sub-modules are considered at e
to reduce the equivalent switching frequ
excessive switching losses. The circulating
also added to the modulation reference sig
capacitor balancing faster.
Number of active sub-modules is calcu
average measured capacitor voltages inst
constant value to increase accuracy.
Figure 3. Output and reference voltage of the propo
Figure 4. Switching state of sub-modu
D1
D2
S1
S2
ipa
Vc
S1
S2
Vc
D1
D2
S1
S2
ipa
Vc
S1
S2
Vc
ower devices (S2
capacitor.
discharging state
wing through the
nducting the sub-
and as shown in
module capacitor
le capacitor will
chieve balancing
ate the ones with
on first and in
highest voltage
roposed real-time
onfiguration only
each discrete step
uency and avoid
g current error is
gnal to make the
ulated by using
tead of using a
osed NLM method
ules
Figure 5. Real-time NLM with capa
V. DETAILED LOSS
The main part of power device l
MMC-HVDC system is conductio
losses. The conduction loss mainly
diode conduction losses. Accordi
results of Gen-4 ETO, the turn-off
temperature under 2.5kV dc-bus vo
which yields the turn-off energy in
Ampere. The ETO on-state voltag
temperature is expressed by (6) whe
in Volts and current I is in Ampe
losses are given by (7).
Conduction losses of four devices
calculated during four intervals d
explained before. The magnitude o
change with time hence the accurat
and modulation is required to c
losses precisely. During each in
conduction loss of the active device
First the conduction interval is
intervals. Number of small interv
defined by changes in the number
interval by (8).
D1
D2
ipa
D1
D2
ipa
Vdc1
Vdc2
.
.
.
Vdcn
Sorting
Vdcmax
.
.
.
Vdcmin
+
(Index)
1
2
.
.
.
n
+
Nactive
(number of
active SMs)
NLM criteria
Varm,ref
1Vdc
2Vdc
.
.
.
nVdc
( Discrete
Voltage
Steps)
Vdcmin
.
.
.
Vdcmax
+
(Index)
citor voltage balancing
CALCULATIONS
losses in an ETO based
on losses and switching
y includes the ETO and
ng to experimental test
ff loss at 125°C junction
oltage is expressed by (5)
n Joule and current is in
ge under 125°C junction
ere the on-state voltage is
eres [7]. The conduction
(5)
(6)
(7)
in each sub-module are
defined in Figure 6 and
of current and modulation
te information of current
calculate the conduction
nterval in Figure 6 the
e is calculated as follows:
s divided into smaller
vals or discrete levels is
of active devices in each
S1
S2
.
.
.
Sn
(Switching
signals)
x
)
3464
4. Where tup
is the upper time limit of the inter
lower time limit. The conduction loss is th
small intervals and added together for the n
cells in to find the total conduction loss o
MMC arm. Losses are calculated usin
modulation for MMC. The arms of MMC
the losses are calculated for one arm and
Reduced switching frequency nearest le
(NLM) is used in this design, which is base
the required number of the sub-modules
output waveform that follows the refere
waveform.
As mentioned before, the sub-modules are o
once during each switching cycle and switc
each discrete step is made by considerin
sub-modules to avoid excessive switchi
switching loss is calculated for ETO and
the four regions with respect to switchin
devices. To calculate the number of device
or off during each interval nactive
must be c
beginning and end of the time interval.
equation as an example shows the numb
during (t3
, 0) time interval.
Where nSW
is the total number of devices t
off that occur during each region assumin
status of only one of the sub-modules cha
discrete step. Similarly, nSW
and switch
calculated for D2
, S2
, S1
during the time int
(t1
+t2
)/2) and ((t1
+t2
)/2, t1
).
Adding the calculated losses for four re
switching losses for reduced switching
modulation used in this design. The devic
includes turn-on loss and turn-off loss. Due
di/dt inductor, ETO turn-on loss is sm
neglected. Therefore the switching losses p
ETO and diode turn-off losses.
Figure 8 shows the overall diagram
Reference modulation waveform genera
controller is the input to capacitor voltag
loss calculation systems. Loss calculation
the individual device losses for all sub-modu
(8)
rval and tlow
is the
hen calculated for
number of active
of each device in
ng nearest level
C are identical so
multiplied by 6.
evel modulation
ed on calculating
s to generate an
ence modulation
only switched on
ching decision at
ng the remaining
ing losses. The
diode in each of
ng status of the
es that switch on
calculated at the
. The following
ber of switching
(9)
that switch on or
ng that switching
ange during each
hing losses are
tervals (0, t2
), (t2
,
egions results in
frequency NLM
ce switching loss
e to the use of the
mall and can be
primarily include
(10)
of the system.
ated by system
ge balancing and
n system outputs
ules.
Figure. 6 Proposed loss estimation metho
switching state
Accurate individual device losses a
using the proposed loss calculatio
shows the power losses of S1, D1,
module in the upper arm for mor
example and the same waveforms c
devices in other sub-modules.
technique swaps sub-modules and
losses amongst sub-modules.
Table 1 summarizes the device and
500MW ETO based MMC-HVD
operating conditions. The DC link
system is 320KV and there are 1
arm of the converter. Conventiona
have around 1% semiconductor lo
total semiconductor loss of the pro
16% less than conventional MMC-H
Figure 7. Proposed modulation and re
od, arm voltage, current and
es
are calculated and plotted
on technique. Figures 8
S2 and D2 the first sub-
e than 100 cycles as an
can be plotted for all four
. Capacitor balancing
will eventually balance
d sub-module losses of a
DC system for different
k voltage of the modeled
28 sub-modules in each
al MMC-HVDC systems
sses per station [1]. The
oposed system is around
HVDC systems.
eal time loss calculation
3465
5. Figure 8. Real time loss of the four devices in the first sub-module
I. THERMAL ANALYSIS
Each sub-module of MMC has two ETOs and two diodes
and the losses of the switching components need to be
removed out by a cooling system. The heat pipe based air
cooling system can be used to remove the heat from ETO
stacks. Use of heat pipe helps with cost, reliability and
comact structure and allows us to avoid the drawbacks of
conventional water cooling systems such as the need of
good electrical isolation. A basic pricipal in optimal design
of ETO stacks is to use the stray inductance to limit the turn
on current.
Figure 10 shows heat pipe based cooling and ETO based
MMC sub-module structure. The cooling system of half-
bridge MMC sub-module is first designed for the MMC-
HVDC system at 500MW operation and the junction
temperatures are still much lower than 100°C.
Table II shows the individual device losses for designed
500MW operation. Since the junction temperature of all
sub-module devices is well below 125°C the ETO based
system is capable to operate at higher powers. The
possibility of 1000MW operation is examined and losses are
calculated, table III shows the junction temperature of four
devices. Device temperatures are still lower than 125°C
which indicates that the proposed system has potential to
reach 1000MW which is much higher than IGBT based
MMC-HVDC systems.
TABLE I. LOSS CALCULATION FOR A 500MW ETO BASED MMC-
HVDC SYSTEM
Figure 9. Average device losses over 200 cycles
Figure 10. Heat pipe based cooling (left), MMC sub-module (right)
0 10 20 30 40 50 60 70 80 90 100 110
0
50
100
150
200
250
300
Number of cycles (N)
DiodeD1(SM1)losses(Watt)
0 10 20 30 40 50 60 70 80 90 100 110
0
200
400
600
800
Number of cycles (N)
SwitchS1(SM1)losses(Watt)
0 10 20 30 40 50 60 70 80 90 100 110
0
200
400
600
800
1000
1200
Number of cycle (N)
DiodeD2(SM1)losses(Watt)
0 10 20 30 40 50 60 70 80 90 100 110
0
50
100
150
200
250
300
Number of cycles (N)
SwitchS2(SM1)losses(Watt)
Device Loss (PF= -0.95) Loss (PF= 1) Loss(PF=+0.95)
D1 155 132 181
D2 310 705 632
S2 446 167 162
S1 816 596 719
Each sub-module losses 1727 1600 1694
Each sub-module losses [1]
design with IGBT
(400 MW, Vdc=200KV, nsm=200)
2330 1850 2167
0
500
1000
1500
2000
D1 D2 S2 S1 SM loss
PF=-0.95
PF=+0.95
PF=1
c
D1c
c
c
S1
S2
D2
ETO
Heat pipe
Antiparallel
diode
cc
cc
S1
S2
D1
D2
3466
6. TABLE II. DEVICE TEMPERATURE FOR DESIGNED 500MW MMC-
HVDC
Device Junction temperature (°C)
D
2
61.9
S
2
67.4
S
1
81.6
D
1
54.4
TABLE III. DEVICE TEMPERATURE FOR A POTENTIAL 1000MW MMC-
HVDC
Device Junction temperature (°C)
D
2
82.9
S
2
90.6
S
1
109.2
D
1
70.1
II. CONCLUSION
This paper proposed a new ETO based MMC-HVDC
system and discussed modulation, capacitor voltage
balancing and detailed valve loss calculation based on
reduced switching frequency NLM for the proposed system.
The MMC-HVDC system loss is more than 1% per station
[1], yet proposed MMC-HVDC system based on the
4500V/4000A ETO thyristor has higher capacity and more
than 16% lower losses per station compared to IGBT based
MMC-HVDC. Besides, the system has the controllability of
the VSC based HVDC systems.
Thermal analysis shows that power capacity of ETO based
MMC-HVDC can reach higher than 1000MW which is
more than power capacity of conventional MMC-HVDC
systems.
REFERENCES
[1] Jones, P.S. and C.C. Davidson. Calculation of power losses for
MMC-based VSC HVDC stations. in Power Electronics and
Applications (EPE), 2013 15th European Conference on. 2013. IEEE.
[2] Rohner, S., et al., Modulation, losses, and semiconductor
requirements of modular multilevel converters. Industrial Electronics,
IEEE Transactions on, 2010. 57(8): p. 2633-2642.
[3] Zhang, Z., Z. Xu, and Y. Xue, Valve Losses Evaluation Based on
Piecewise Analytical Method for MMC–HVDC Links. 2014.
[4] Oates, C. and C. Davidson. A comparison of two methods of
estimating losses in the Modular Multi-Level Converter. in Power
Electronics and Applications (EPE 2011), Proceedings of the 2011-
14th European Conference on. 2011. IEEE.
[5] Yang, L., C. Zhao, and X. Yang. Loss calculation method of modular
multilevel HVDC converters. in Electrical Power and Energy
Conference (EPEC), 2011 IEEE. 2011. IEEE.
[6] Li, Y., A.Q. Huang, and K. Motto, Experimental and numerical study
of the emitter turn-off thyristor (ETO). Power Electronics, IEEE
Transactions on, 2000. 15(3): p. 561-574.
[7] Li, J., et al. ETO light multilevel converters for large electric vehicle
and hybrid electric vehicle drives. in Vehicle Power and Propulsion
Conference, 2009. VPPC'09. IEEE. 2009. IEEE.
[8] TEWARI, K., Investigation of High Temperature Operation Emitter
Turn Off Thyristor (ETO) and Electro Thermal Design of Heatpipe
Based High Power Voltage Source Converter Using ETO, in ECE
North Carolina State: 2006.
[9] Etemadrezaei, M., et al. "Precise calculation and optimization of rotor
eddy current losses in high speed permanent magnet machine."
Electrical Machines (ICEM), 2012 XXth International Conference on.
IEEE, 2012.
[10] Falahi, Ghazal. PhD Dissertation, "Design, Modeling and Control of
Modular Multilevel Converter based HVDC Systems." North
Carolina State University, (2014).
3467