The document describes the design of an oscillator using a CMOS operational transconductance amplifier (OTA). It discusses different current mirror circuits used to design the CMOS OTA and selects the cascode current mirror as most suitable. RC phase shift and Wien bridge oscillators are then created using the CMOS OTA. Simulation results show the oscillators generate sine waves close to their calculated frequencies. The CMOS OTA provides advantages like high bandwidth and slew rate over traditional op-amps.
APPLICATIONS OF FLOATING-GATE MOSFET IN THE DESIGN OF INVERTER AND RING OSCIL...elelijjournal
This paper presents the application of floating-gate MOSFET (FGMOS) in the design of low voltage and
high speed digital circuits wherein threshold voltage tunability of FGMOS has been exploited to enhance
the performance of inverter in terms of various parameters like switching threshold voltage, noise margins,
propagation delay and energy delay product. It has been observed that by varying the bias voltage in
FGMOS, the voltage transfer characteristics can be altered that result in lowering of switching threshold
voltage, increased noise margins, reduced propagation delay and less energy delay product as compared to
the standard CMOS inverter. This paper also demonstrates the design of ring oscillator using FGMOS and
it has been found that FGMOS based ring oscillator exhibits higher frequency of oscillation as compared to
its CMOS counterpart. The performance of these circuits has been verified through PSpice simulations
carried out using level 7 parameters in 0.13 µm CMOS technology with a supply voltage of 1 V.
FAST TRANSIENT RESPONSE LOW DROPOUT VOLTAGE REGULATORijseajournal
This paper presents the design of Low Drop-Out (LDO) voltage regulator has fast transient response and which exploits a few current else low quiescent current in the operational amplifier PMOS type. We use band-gap reference for eliminate the temperature dependence. The proposed LDO voltage regulator implemented in 0.18-μm CMOS technology, we use Folded cascode CMOS amplifiers high performance in the stability , provide fast transient response which explains a fast settling, the LDO itself should provide in the output regulator voltages at t equal 2ps with transient variation of the voltage less than 170mV. High accuracy in the DC response terms, the simulation results show that the accuracy of the output regulator voltages is 1.54±0.009V, and power consumption of 1.51 mW.
A High-Swing OTA with wide Linearity for design of self-tunable linear resistorVLSICS Design
Low power consumption, long battery life and portability are essential requirements of modern health monitoring products. Operational Transconductance Amplifier (OTA) operating in subthreshold region is an basic building block for low power health monitoring products design. An modified design of OTA which incorporates better linearity and increased output impedance has been discussed in this paper. The proposed OTA uses High-swing improved-Wilson current mirror for low power and low-frequency applications. The achieved linearity is about ± 1.9 volt and unity gain bandwidth (UGB) of 342.30 KHz at power supply of 0.9 volt which makes OTA to consume power in range of nanowatts. The proposed low voltage OTA implementation in design of self- tunable linear resistor has been presented in this paper. The circuit implementation has been done using standard 0.18 micron technology provided by TSMC on BSIM 3v3 level-53 model parameter and verified results through use of ELDO Simulator.
An improved design of CMOS dynamic latch comparator with dual input dual output with a simple
design of three stages is represented. The basic disadvantages of latch type comparators are overcome by
producing an edge triggered comparison. The circuit is designed for a resolution of 300nV and the power
consumption is reduced to 450uW. It is designed for 1.8V DC supply voltage and 1 MHz clock frequency for
PVT variations. The simulation of the comparator is done in Cadence® Virtuoso Analog Design Environment
using 180nm technology. The error quotient is reduced less than 5% by adding a buffer stage. The delay is
brought down to 5nS. The active area appreciably is reduced. Layout of the proposed comparator has been
simulated in Cadence® Virtuoso Layout XL Design Environment. DRC and LVS have been verified.
APPLICATIONS OF FLOATING-GATE MOSFET IN THE DESIGN OF INVERTER AND RING OSCIL...elelijjournal
This paper presents the application of floating-gate MOSFET (FGMOS) in the design of low voltage and
high speed digital circuits wherein threshold voltage tunability of FGMOS has been exploited to enhance
the performance of inverter in terms of various parameters like switching threshold voltage, noise margins,
propagation delay and energy delay product. It has been observed that by varying the bias voltage in
FGMOS, the voltage transfer characteristics can be altered that result in lowering of switching threshold
voltage, increased noise margins, reduced propagation delay and less energy delay product as compared to
the standard CMOS inverter. This paper also demonstrates the design of ring oscillator using FGMOS and
it has been found that FGMOS based ring oscillator exhibits higher frequency of oscillation as compared to
its CMOS counterpart. The performance of these circuits has been verified through PSpice simulations
carried out using level 7 parameters in 0.13 µm CMOS technology with a supply voltage of 1 V.
FAST TRANSIENT RESPONSE LOW DROPOUT VOLTAGE REGULATORijseajournal
This paper presents the design of Low Drop-Out (LDO) voltage regulator has fast transient response and which exploits a few current else low quiescent current in the operational amplifier PMOS type. We use band-gap reference for eliminate the temperature dependence. The proposed LDO voltage regulator implemented in 0.18-μm CMOS technology, we use Folded cascode CMOS amplifiers high performance in the stability , provide fast transient response which explains a fast settling, the LDO itself should provide in the output regulator voltages at t equal 2ps with transient variation of the voltage less than 170mV. High accuracy in the DC response terms, the simulation results show that the accuracy of the output regulator voltages is 1.54±0.009V, and power consumption of 1.51 mW.
A High-Swing OTA with wide Linearity for design of self-tunable linear resistorVLSICS Design
Low power consumption, long battery life and portability are essential requirements of modern health monitoring products. Operational Transconductance Amplifier (OTA) operating in subthreshold region is an basic building block for low power health monitoring products design. An modified design of OTA which incorporates better linearity and increased output impedance has been discussed in this paper. The proposed OTA uses High-swing improved-Wilson current mirror for low power and low-frequency applications. The achieved linearity is about ± 1.9 volt and unity gain bandwidth (UGB) of 342.30 KHz at power supply of 0.9 volt which makes OTA to consume power in range of nanowatts. The proposed low voltage OTA implementation in design of self- tunable linear resistor has been presented in this paper. The circuit implementation has been done using standard 0.18 micron technology provided by TSMC on BSIM 3v3 level-53 model parameter and verified results through use of ELDO Simulator.
An improved design of CMOS dynamic latch comparator with dual input dual output with a simple
design of three stages is represented. The basic disadvantages of latch type comparators are overcome by
producing an edge triggered comparison. The circuit is designed for a resolution of 300nV and the power
consumption is reduced to 450uW. It is designed for 1.8V DC supply voltage and 1 MHz clock frequency for
PVT variations. The simulation of the comparator is done in Cadence® Virtuoso Analog Design Environment
using 180nm technology. The error quotient is reduced less than 5% by adding a buffer stage. The delay is
brought down to 5nS. The active area appreciably is reduced. Layout of the proposed comparator has been
simulated in Cadence® Virtuoso Layout XL Design Environment. DRC and LVS have been verified.
Analysis and Design of A Low-Voltage Low-Power Double-Tail Comparator. This is a final semester Mtech project on VLSI design implementation of dual tail comparator in a modifyied version. This design is implemented using VHDL Language with 100% Source code synthesizable available. Software for free to download and knowledge transfer for the same project is also being implemented..The design is implemented using FSM technology, low power is achieved in this project.area utilization is the major advantage in this project.Low power techniques such as Clock gating, power gating is implemented in this project.,ieee reference paper is used for the base.
SINGLE PHASE SYMMETRICAL MULTILEVEL INVERTER DESIGN FOR VARIOUS LOADSelelijjournal
This paper presents a single phase symmetrical multilevel inverter with various loads. This proposed
topology is connected with R-load, RL-load and induction motor drive with unipolar Phase disposition
PWM technique. Among the four modulation technique it gives reduced harmonic. This proposed topology
has less number of switches than the conventional one. In conventional cascaded multilevel inverter have
twelve switches and the proposed topology have eight switches. Totally the four switches have been
reduced from the conventional one. It is designed to produce a seven level output. The simulation analysis
has been done by a MATLAB/SIMULINK model.
Design of Low Power & High Speed Comparator with 0.18μm Technology for ADC Ap...IJERA Editor
In Analog to Digital Converter (ADC), high speed comparator influences the overall performance of ADC directly. This paper presents the high speed & low power design of a CMOS comparator. Schematic design of this comparator is fabricated in a 0.18μm UMC Technology with 1.8V power supply and simulated in cadence Virtuoso. Simulation results are presented and it shows that this design can work under high speed of 0.8108 GHz. The design has a low offset voltage, low power dissipation 108.0318μw. In addition we have verified present results with schematic view design and also compared these results with earlier reported work and got improvement in this reported work.
Simulated Analysis of Resonant Frequency Converter Using Different Tank Circu...IJERD Editor
LLC resonant frequency converter is basically a combo of series as well as parallel resonant ckt. For
LCC resonant converter it is associated with a disadvantage that, though it has two resonant frequencies, the
lower resonant frequency is in ZCS region [5]. For this application, we are not able to design the converter
working at this resonant frequency. LLC resonant converter existed for a very long time but because of
unknown characteristic of this converter it was used as a series resonant converter with basically a passive
(resistive) load. . Here, it was designed to operate in switching frequency higher than resonant frequency of the
series resonant tank of Lr and Cr converter acts very similar to Series Resonant Converter. The benefit of LLC
resonant converter is narrow switching frequency range with light load[6] . Basically, the control ckt plays a
very imp. role and hence 555 Timer used here provides a perfect square wave as the control ckt provides no
slew rate which makes the square wave really strong and impenetrable. The dead band circuit provides the
exclusive dead band in micro seconds so as to avoid the simultaneous firing of two pairs of IGBT’s where one
pair switches off and the other on for a slightest period of time. Hence, the isolator ckt here is associated with
each and every ckt used because it acts as a driver and an isolation to each of the IGBT is provided with one
exclusive transformer supply[3]. The IGBT’s are fired using the appropriate signal using the previous boards
and hence at last a high frequency rectifier ckt with a filtering capacitor is used to get an exact dc
waveform .The basic goal of this particular analysis is to observe the wave forms and characteristics of
converters with differently positioned passive elements in the form of tank circuits. The supported simulation
is done through PSIM 6.0 software tool
In this paper Low power low voltage CMOS analog multiplier circuit is proposed. It is based on flipped voltage
follower. It consists of four voltage adders and a multiplier core. The circuit is analyzed and designed in 0.18um
CMOS process model and simulation results have shown that, under single 0.9V supply voltage, and it
consumes only 31.8μW quiescent power and 110MHZ bandwidth.
Design of Ota-C Filter for Biomedical ApplicationsIOSR Journals
Abstract-This paper presents design of operational transconductance amplifier is to amplify the ECG signal
having low frequency of 300Hz, with the supply voltage of 0.8v. To reduce the power dissipation of 779nW, by
using fifth order low pass filter. The OTA-C filter is to eliminate noise voltage and increases the reliability of
the system. A chip is fabricated in a 0.18μm CMOS process is simulated and measured to validate the system
performance using HSPICE.
Design of very large scale analog integrated circuit (analog VLSI) is very much complex and requires
much compromising nature to achieve application specific objective. With maximizing the efforts to reduce
power consumption and to reduce W/L ratio, the analog integrated circuit industry is constantly
developing smaller power supplies. Now days, challenges of analog integrated circuit designer are to
make block of small power supplies with little or no reduction in performance. The CMOS OTA is
designed in 25.5nm CMOS technology with 1.0V power supply to observe the configurations. In design of
CMOS OTA TANNER EDA TOOL is used. Coding and simulation is done in T-Spice and layout is
prepared in L-Edit. D.C analysis, A.C analysis, slew rate and analysis of transient response have been
done in T-Spice. Waveforms are observed in W-Edit.
Electronically Tunable Current-Mode SIMO/MISO Universal Biquad Filter Using M...IDES Editor
This paper presents an electronically tunable
current-mode SIMO/MISO universal biquad filter using multioutput
current controlled current conveyor transconductance
amplifiers (MO-CCCCTAs). The proposed filter employs only
two CCCCTAs and two grounded capacitors. The proposed
configuration can be used as either single input multi-output
(SIMO) or multi (three) input single output (MISO) current
mode filter. It can realize all five different standard filter
functions i.e. low-pass (LP), band-pass (BP), high-pass (HP),
band-reject (BR) and all-pass (AP). The circuit enjoys an
independent current control of pole frequency and bandwidth.
Both the active and passive sensitivities are no more than
unity. The validity of proposed filter is verified through
computer simulations using PSPICE, the industry standard
tool.
Electronically Tunable Current/Voltage- mode Universal Biquad Filter using CC...IDES Editor
This paper presents an electronically tunable
current/voltage mode universal biquad filter using current
controlled current conveyor transconductance amplifiers
(CCCCTAs). The proposed filter employs only two CCCCTAs
and two grounded capacitors. The proposed filter can
simultaneously realize low pass (LP), band pass (BP) and high
pass (HP) responses. Realization of band reject (BR) and all pass
(AP) responses are also feasible. The circuit can also be
operated in mixed mode with either voltage or current input and
current or/and voltage outputs, thus the configuration is
versatile. The circuit enjoys an independent current control of
pole frequency and bandwidth. Moreover, the LP and BP gain
can be independently tuned by external biasing current of
active elements without disturbing the pole frequency, quality
factor and bandwidth. Both the active and passive sensitivities
are no more than unity. The validity of proposed filter is
verified through PSPICE simulations. The total power
consumption is about 0.641mW at ±1.85V supply voltages
Analysis and Design of A Low-Voltage Low-Power Double-Tail Comparator. This is a final semester Mtech project on VLSI design implementation of dual tail comparator in a modifyied version. This design is implemented using VHDL Language with 100% Source code synthesizable available. Software for free to download and knowledge transfer for the same project is also being implemented..The design is implemented using FSM technology, low power is achieved in this project.area utilization is the major advantage in this project.Low power techniques such as Clock gating, power gating is implemented in this project.,ieee reference paper is used for the base.
SINGLE PHASE SYMMETRICAL MULTILEVEL INVERTER DESIGN FOR VARIOUS LOADSelelijjournal
This paper presents a single phase symmetrical multilevel inverter with various loads. This proposed
topology is connected with R-load, RL-load and induction motor drive with unipolar Phase disposition
PWM technique. Among the four modulation technique it gives reduced harmonic. This proposed topology
has less number of switches than the conventional one. In conventional cascaded multilevel inverter have
twelve switches and the proposed topology have eight switches. Totally the four switches have been
reduced from the conventional one. It is designed to produce a seven level output. The simulation analysis
has been done by a MATLAB/SIMULINK model.
Design of Low Power & High Speed Comparator with 0.18μm Technology for ADC Ap...IJERA Editor
In Analog to Digital Converter (ADC), high speed comparator influences the overall performance of ADC directly. This paper presents the high speed & low power design of a CMOS comparator. Schematic design of this comparator is fabricated in a 0.18μm UMC Technology with 1.8V power supply and simulated in cadence Virtuoso. Simulation results are presented and it shows that this design can work under high speed of 0.8108 GHz. The design has a low offset voltage, low power dissipation 108.0318μw. In addition we have verified present results with schematic view design and also compared these results with earlier reported work and got improvement in this reported work.
Simulated Analysis of Resonant Frequency Converter Using Different Tank Circu...IJERD Editor
LLC resonant frequency converter is basically a combo of series as well as parallel resonant ckt. For
LCC resonant converter it is associated with a disadvantage that, though it has two resonant frequencies, the
lower resonant frequency is in ZCS region [5]. For this application, we are not able to design the converter
working at this resonant frequency. LLC resonant converter existed for a very long time but because of
unknown characteristic of this converter it was used as a series resonant converter with basically a passive
(resistive) load. . Here, it was designed to operate in switching frequency higher than resonant frequency of the
series resonant tank of Lr and Cr converter acts very similar to Series Resonant Converter. The benefit of LLC
resonant converter is narrow switching frequency range with light load[6] . Basically, the control ckt plays a
very imp. role and hence 555 Timer used here provides a perfect square wave as the control ckt provides no
slew rate which makes the square wave really strong and impenetrable. The dead band circuit provides the
exclusive dead band in micro seconds so as to avoid the simultaneous firing of two pairs of IGBT’s where one
pair switches off and the other on for a slightest period of time. Hence, the isolator ckt here is associated with
each and every ckt used because it acts as a driver and an isolation to each of the IGBT is provided with one
exclusive transformer supply[3]. The IGBT’s are fired using the appropriate signal using the previous boards
and hence at last a high frequency rectifier ckt with a filtering capacitor is used to get an exact dc
waveform .The basic goal of this particular analysis is to observe the wave forms and characteristics of
converters with differently positioned passive elements in the form of tank circuits. The supported simulation
is done through PSIM 6.0 software tool
In this paper Low power low voltage CMOS analog multiplier circuit is proposed. It is based on flipped voltage
follower. It consists of four voltage adders and a multiplier core. The circuit is analyzed and designed in 0.18um
CMOS process model and simulation results have shown that, under single 0.9V supply voltage, and it
consumes only 31.8μW quiescent power and 110MHZ bandwidth.
Design of Ota-C Filter for Biomedical ApplicationsIOSR Journals
Abstract-This paper presents design of operational transconductance amplifier is to amplify the ECG signal
having low frequency of 300Hz, with the supply voltage of 0.8v. To reduce the power dissipation of 779nW, by
using fifth order low pass filter. The OTA-C filter is to eliminate noise voltage and increases the reliability of
the system. A chip is fabricated in a 0.18μm CMOS process is simulated and measured to validate the system
performance using HSPICE.
Design of very large scale analog integrated circuit (analog VLSI) is very much complex and requires
much compromising nature to achieve application specific objective. With maximizing the efforts to reduce
power consumption and to reduce W/L ratio, the analog integrated circuit industry is constantly
developing smaller power supplies. Now days, challenges of analog integrated circuit designer are to
make block of small power supplies with little or no reduction in performance. The CMOS OTA is
designed in 25.5nm CMOS technology with 1.0V power supply to observe the configurations. In design of
CMOS OTA TANNER EDA TOOL is used. Coding and simulation is done in T-Spice and layout is
prepared in L-Edit. D.C analysis, A.C analysis, slew rate and analysis of transient response have been
done in T-Spice. Waveforms are observed in W-Edit.
Electronically Tunable Current-Mode SIMO/MISO Universal Biquad Filter Using M...IDES Editor
This paper presents an electronically tunable
current-mode SIMO/MISO universal biquad filter using multioutput
current controlled current conveyor transconductance
amplifiers (MO-CCCCTAs). The proposed filter employs only
two CCCCTAs and two grounded capacitors. The proposed
configuration can be used as either single input multi-output
(SIMO) or multi (three) input single output (MISO) current
mode filter. It can realize all five different standard filter
functions i.e. low-pass (LP), band-pass (BP), high-pass (HP),
band-reject (BR) and all-pass (AP). The circuit enjoys an
independent current control of pole frequency and bandwidth.
Both the active and passive sensitivities are no more than
unity. The validity of proposed filter is verified through
computer simulations using PSPICE, the industry standard
tool.
Electronically Tunable Current/Voltage- mode Universal Biquad Filter using CC...IDES Editor
This paper presents an electronically tunable
current/voltage mode universal biquad filter using current
controlled current conveyor transconductance amplifiers
(CCCCTAs). The proposed filter employs only two CCCCTAs
and two grounded capacitors. The proposed filter can
simultaneously realize low pass (LP), band pass (BP) and high
pass (HP) responses. Realization of band reject (BR) and all pass
(AP) responses are also feasible. The circuit can also be
operated in mixed mode with either voltage or current input and
current or/and voltage outputs, thus the configuration is
versatile. The circuit enjoys an independent current control of
pole frequency and bandwidth. Moreover, the LP and BP gain
can be independently tuned by external biasing current of
active elements without disturbing the pole frequency, quality
factor and bandwidth. Both the active and passive sensitivities
are no more than unity. The validity of proposed filter is
verified through PSPICE simulations. The total power
consumption is about 0.641mW at ±1.85V supply voltages
Implementation of Fully Differential OTA based on Commercially Available IC f...IDES Editor
This article presents a realization of a recently basic
building block for analog signal processing, namely fully
differential operation transconductance amplifier (FD-OTA)
using the commercially available ICs (LT1228). The proposed
element has very simple internal instruction. The
performances are examined through PSpice simulations. The
description include example as biquadratic filter topology.
They show good agreement as theoretically depicted.
Design and analysis of operational transconductance amplifier using pspiceeSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
The paper introduces a multi-pass loop voltage controlled ring oscillator. The proposed structure uses cross-coupled PMOS transistors and replica bias with coarse/fine control signal. The design implemented in TSMC 90 nm CMOS technology, 0.9V power supply with frequency tuning range 481MHz to 4.08GHz and -94.17dBc/Hz at 1MHz offset from 4.08GHz with 26.15mW power consumption.
Distortion Analysis of Differential AmplifierIOSR Journals
Abstract: The linearity of the CMOS is of major concern in the design of many analog circuits. In this paper the nonlinearity behavior of CMOS analog integrated circuits is investigated.The basic building block of analog integrated circuits such as differential amplifier with current mirror load have been chosen for harmonic distortion analysis.A mechanism to analyze the distortion of CMOS circuits in deep submicron technology that can be easily used to detect the distortion is built.The MOSFET model used for simulation is TSMC BSIM3 SPICE model from 0.13-μm CMOS process technology. HSPICE circuit simulator tool is used for distortion analysis of CMOS circuits. The MOS model used in this paper includes short-channel effects and gate-source capacitance, gate-drain capacitance, output resistance of MOS transistor. Analytical results are compared with simulation results and the influences of circuit parameters on circuit linearity are discussed.
Keywords: Analog Integrated Circuits, CMOSanalog integrated circuits, harmonic distortion, HSPICE, Short-channel effects, small signal analysis, transient analysis.
An operational amplifier with recycling folded cascode topology and adaptive ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed
and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing
circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew
rate (SR). This single stage op-amp has been designed in 0.18μm technology with a power supply of 1.8V
and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain
Bandwidth of 247.1MHz and a slew rate of 92.8V/μs.
A High-Swing OTA with wide Linearity for design of self-tunable linear resistorVLSICS Design
Low power consumption, long battery life and portability are essential requirements of modern health monitoring products. Operational Transconductance Amplifier (OTA) operating in subthreshold region is an basic building block for low power health monitoring products design. An modified design of OTA which incorporates better linearity and increased output impedance has been discussed in this paper. The proposed OTA uses High-swing improved-Wilson current mirror for low power and low-frequency applications. The achieved linearity is about ± 1.9 volt and unity gain bandwidth (UGB) of 342.30 KHz at power supply of 0.9 volt which makes OTA to consume power in range of nanowatts. The proposed low voltage OTA implementation in design of self- tunable linear resistor has been presented in this paper. The circuit implementation has been done using standard 0.18 micron technology provided by TSMC on BSIM 3v3 level-53 model parameter and verified results through use of ELDO Simulator.
AN OPERATIONAL AMPLIFIER WITH RECYCLING FOLDED CASCODE TOPOLOGY AND ADAPTIVE ...VLSICS Design
This paper presents a highly adaptive operational amplifier with high gain, high bandwidth, high speed and low power consumption. By adopting the recycling folded cascode topology along with an adaptivebiasing circuit, this design achieves high performance in terms of gain-bandwidth product (GBW) and slew rate (SR). This single stage op-amp has been designed in 0.18µm technology with a power supply of 1.8V and a 5pF load. The simulation results show that the amplifier achieved a GBW of 335.5MHz, Unity Gain Bandwidth of 247.1MHz and a slew rate of 92.8V/µs.
A LOW POWER, LOW PHASE NOISE CMOS LC OSCILLATORIJEEE
In this paper a Double Cross Coupled Inductor capacitor based Voltage Control Oscillator (LC-VCO) is designed. In the proposed circuit the phase noise, tuning range with respect to control voltage, output power and the power dissipation of the circuit is analysed. Phase noise of approximate -96 dBc/Hz at frequency of 1MHz, frequency tuning range of 4.8 to 8.3 GHz (corresponding to 53.0% tuning range) obtained by varying the control voltage from 0 to 2.0 V, Output power of circuit -8.92 dBm at 50 Ohm resistance terminal and the power consumption of Circuit is 3.8 mW. This VCO are designed for 5.5 GHz. The circuit is designed on the UMC 180nm CMOS technology and all the simulation results are obtained using cadence SPECTRE Simulator.
Compact low power high slew-rate cmos buffer amplifier with power gating tech...VLSICS Design
A qualitative analysis of different parameters such as Phase noise, Slew rate and tranconductance by using
power gating reduction technique is presented. The circuit achieves the large driving capability by
employing simple comparators to sense the transients of the input to turn on the output stages, which are
statically off in the stable state. The effect of the different number of transistors and their topologies on the
phase noise and Slew rate is analyzed. Good agreement between qualitative and quantitative measurements
is observed. Scope of reducing of Noise and avoidance of Leakage due to various sources is discussed.
Design of Low Voltage Low Power CMOS OP-AMPIJERA Editor
Operational amplifiers are an integral part of many analog and mixed signal systems. As the demand for mixed
mode integrated circuits increases, the design of analog circuits such as operational amplifiers in CMOS
technology becomes more critical. This paper presents a two stage CMOS operational amplifier, which operates
at ±1.8V power supply using TSMC 0.18um CMOS technology. The OP-AMP designed exhibit unity gain
frequency of 12.6 MHz, and gain of 55.5db with 300uw power dissipation. The gain margin and phase margin
of OP-AMP is 45˚ and 60˚ respectively. Design and simulation has been carried out in P Spice tool.
Design of Two CMOS Differential Amplifiersbastrikov
High performance, 0.6u process CMOS differential amplifiers were designed in Cadence. Design specifications included differential gain, 3-db bandwidth, output swing, input common mode range, phase margin, total static power consumption, slew rate, and common mode rejection ratio.
Study of Low Voltage Cascode Current Mirror with Enhance Dynamic Rangeijsrd.com
The current mirror is one of most common building blocks both in analog and mixed mode VLSI circuits and the performance of analog structures largely depends on their characteristics. The current mirror can be used as an active element and as a biasing circuit. In this paper we study about the current mirror, cascode current mirror and different low voltage current mirror topology and study the literature survey. After that we study, analysis and design of convention Level shifted low voltage current mirror and TSPICE simulation technology. Presented analysis low voltage current mirror input –output characteristic, high output swing capability and wide input -output swing capabilities, suitable for low voltage operation and minimum power dissipation.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
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Terzaghi's soil bearing capacity theory, developed by Karl Terzaghi, is a fundamental principle in geotechnical engineering used to determine the bearing capacity of shallow foundations. This theory provides a method to calculate the ultimate bearing capacity of soil, which is the maximum load per unit area that the soil can support without undergoing shear failure. The Calculation HTML Code included.
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1. International Journal of Electrical and Computing Engineering
Vol. 1, Issue. 1, July – 2014 ISSN (Online): 2349-8218
23
Design of an Oscillator Using CMOS Operational
Transconductance Amplifier (OTA)
Raja Sen1
, Arko Banerjee2
, Satyaki Banerjee3
, Sayanta Roychowdhury4
1,2,3,4
Future Institute of Engineering and Management, Kolkata, INDIA.
Abstract - Our goal for this project is to
design a Signal Generator using CMOS
Operational Transconductance Amplifier
(OTA). We found out different parameters
of CMOS OTA using different current
mirror circuits and selected the best suitable
circuit. In case of the CMOS OTA, we
designed the current mirror circuit using
PMOS and the driver circuit using NMOS.
We have created a model of the CMOS
OTA using MATLAB R2013a and
implemented the RC Phase Shift Oscillator
and Wien Bridge Oscillator with satisfactory
results. Finally, we have generated the
layout of the CMOS OTA model for
industrial fabrication. Thus the flexibility of
the design and the practicality of the circuit
have been confirmed.
Keywords – CMOS, OTA, Current Mirror,
Oscillator.
A. Introduction - Low power dissipation in
any circuit is attractive, and perhaps even
essential in mobile devices to have
reasonable battery life and weight. The
ultimate goal in design is close to having
low-battery systems, because the battery
contributes greatly to volume and weight
[1]. The current mode approach proves a
better alternative for low voltage high
performance analog circuit design in which
the circuit designer is more concerned with
current levels for the operation of the
circuits [2]. The CMOS structure achieves
very low power dissipation due to its
insulated gate. This feature can be used to
design analog circuits like oscillators,
amplifiers etc., which have low power
dissipation and hence can be used in analog
circuits of mobile devices. We have used the
CMOS structure to design an Operational
Transconductance Amplifier (OTA) and
then used that OTA to design RC Phase
Shift oscillator and Wien Bridge oscillator.
B. Current Mirror - A current mirror is a
circuit designed to copy a current through
one active device by controlling the current
in another active device of a circuit, keeping
the output current constant regardless of
loading [3].
Different types of current mirrors that we
have used are –
1. The Simple Current Mirror – It is
composed of two transistors of which one
M1 is diode connected. M1 receives the
reference current Iref and measures it by
developing at its gate the voltage Vgs1. This
voltage biases the gate voltage of M2 [9].
Fig.1 Simple Current Mirror
2. International Journal of Electrical and Computing Engineering
Vol. 1, Issue. 1, July – 2014 ISSN (Online): 2349-8218
24
2. The Wilson Current Mirror – The
relatively low value of the output resistance
of the simple current mirror can be
improved with the Wilson scheme shown in
the figure. The gate to source voltage M1 to
M2 is equal, therefore ensuring similar
operation to the circuit. However we see that
the addition of M3 and the established local
feedback allow us to increase the output
resistance [9].
Fig.2 Wilson Current Mirror
3. The Improved Wilson Current Mirror
– The systematic current mismatch in the
Wilson current mirror in compensated by the
improved solution shown in the figure. One
additional transistor is used, M4 which shifts
down the voltage of the gate transistor M3
[4]. Therefore, the drain voltage of M1 is
given by
Vds1=Vgs3+Vds2-Vgs4
If the gate to source voltage of M3 and M4
are equal, the Vds voltage of M1 and M2 will
result as equal. The addition of transistor M4
slightly changes the output resistance small
signal analysis. The transistor M4, diode
connected, adds a resistance 1/gm4 in series
4. The Cascode Current Mirror – An
alternative way to increase the output
resistance is to use the cascode
configuration. The output stage consists of
two transistors M2 and M3 in the cascode
arrangement [11]. Their biases result from
two other transistors M1 and M4 which are
diode connected. Again, as for the
previously stated current mirror the Vgs
voltage of M1 and M2 are set equal.
Therefore a replica of current in M1 is
generated by M2. The output resistance
increases because of the cascode
arrangement [11].
with the resistance, Rl of the reference
current.
Fig.4 Cascode Current Mirror
3. International Journal of Electrical and Computing Engineering
Vol. 1, Issue. 1, July – 2014 ISSN (Online): 2349-8218
25
Fig.3 Improved Wilson Current Mirror
C. CMOS OTA - An OTA is a voltage
controlled current source, more specifically
the term “operational” comes from the fact
that it takes the difference of two voltages as
the input for the current conversion. The
ideal transfer characteristic is therefore,
Iout = gm. (Vin+ − Vin−) = gm.Vin
where gm is the transconductance. An ideal
OTA has infinite impedance (i.e. there is no
input current). The common mode input
range is also infinite, while the differential
signal between these two inputs is used to
control an ideal current source (i.e. the
output current does not depend on the output
voltage) that functions as an output. [5 &
10].
Fig.5 Ideal OTA
CMOS is an electronic device with high
noise immunity and low static power
consumption. CMOS also allows a high
density of logic functions on a chip. It was
primarily for this reason that CMOS became
the most used technology to be implemented
in VLSI chips [6]. Here the P Channel
MOSFETs of the current mirror along with
the N Channel MOSFETs of the driver
circuit constitute the CMOS Operational
Transconductance Amplifier [7]. Here port
1 is the non-inverting terminal and port 3
is the inverting terminal of the CMOS
OTA. The output port is port 2. Since
there is no existence of constant current
source practically, so we have used a NMOS
with Vgs=Vds such that the NMOS is in
saturation [8]. This acts as a constant current
source as the current through the NMOS is
constant and independent of the voltage
across it.
Parameter
Current
Mirrors
Input
Offset
Voltage
Output
Offset
Voltage
CMRR
(dB)
Bandwidth
(Hz)
Slew
Rate
(V/µs)
Unity Gain
Bandwidth
Product
(Hz)
SIMPLE 0.005pV -220.4nV 141.2 15.85M 77.23 15.85M
WILSON 9.242mV -9.924mV 14.98 15.9K 101 15.9K
IMPROVED
WILSON
10pV 86.60nV 3.94 3.95M 0.09 3.95M
CASCODE 0.001pV 52.15nV 154.17 8M 80.35 8M
4. International Journal of Electrical and Computing Engineering
Vol. 1, Issue. 1, July – 2014 ISSN (Online): 2349-8218
26
Fig.6 CMOS OTA
D. Comparative Study of CMOS OTA
using different current mirrors – We
obtained different parameters like Output
offset voltage, Input offset voltage, CMRR,
Slew Rate, frequency response, unity gain
bandwidth using different current mirrors.
We changed the inputs to the driver circuit
for calculating different parameters. The
results that we have got are shown in the
table below.
Fig.7 Frequency Response Curve using
Cascode Current Mirror
Fig.8 Output Plot of Slew Rate using
Cascode Current Mirror
Thus by analyzing all the parameters for different configurations of the current mirror
circuit we can conclude that the CMOS OTA using Cascode Current mirror circuit offers best
performance and is suitable for operations required for the intention of our project, which is to
design a signal generator using CMOS OTA.
5. International Journal of Electrical and Computing Engineering
Vol. 1, Issue. 1, July – 2014 ISSN (Online): 2349-8218
27
Fig.9 CMOS OTA using Cascode Current Mirror Fig.10 Layout of CMOS OTA using
Cascode Current Mirror
E. Oscillator using CMOS OTA -
1. RC Phase Shift Oscillator -
2. Wien Bridge Oscillator -
Fig.11 RC Phase Shift Oscillator
using CMOS OTA
Fig.13 Wien Bridge Oscillator
using CMOS OTA
6. International Journal of Electrical and Computing Engineering
Vol. 1, Issue. 1, July – 2014 ISSN (Online): 2349-8218
28
This is the schematic diagram of the RC
phase shift oscillator using CMOS OTA.
The CMOS OTA shown in the circuit is
nothing but the CMOS OTA using Cascode
Current Mirror. The components values that
we have used here are
Resistor3 =1.5 MΩ,
Resistor2 = 100Ω,
Resistor1 = Resistor4 = Resistor5 =
R=10KΩ,
Capacitor = C = 10nF.
fo = Wo/2π = 1/2π.√6.RC
Putting the values of R and C in the above
equation we get f0 = 649 Hz. Practically, we
get the oscillation frequency to be near
about 600 Hz. So we can say the value that
we got is close to the ideal value.
From the diagram shown above it is very
clear that the components required in this
type of oscillator are less compared to that
of RC phase shift oscillator. The Wien bridge
network is connected to the positive
terminal of the CMOS OTA. The component
values that we have used here are
Resistor3 = 3KΩ, Resistor1 = 1KΩ,
Resistor2 = Resistor4 = R = 10KΩ
Capacitor3 = Capacitor1 = C = 16nF
fo = Wo/2π = 1/2π.RC
Putting the values of R and C we get the
oscillation frequency 994.72 Hz. Practically,
we get the value of oscillation frequency
850 Hz approximately.
F. Results and Discussion –We can observe
that calculated frequency and frequency
from graph are different. This is due to the
lack of any frequency measurement tool in
the Simulink file that we have used to design
the wave generator. We had to calculate it
from the output curve manually. This caused
some discrepancy. The bandwidth that we
got is 8MHz which is very high compared to
the traditional OP-AMP (LM 741) which
has 1.5MHz bandwidth. Moreover the slew
rate is also very high in case of CMOS OTA
using Cascode current mirror, 80.35 V/µs
whereas in case of OP-AMP it is 0.7 V/µs
[12]. The objective of our project was to
create a functional OTA using CMOS and
use it to make a signal generator which can
generate sine waveforms. We used Matlab
R2013a to design the oscillator. We have
also used Orcad Cadence version V16.0 to
measure the various performance parameters
of the CMOS OTA and also designed the
layout of CMOS OTA using Microwind 3.1.
References –
[1] Design of A Low Voltage Low Power
CMOS Current Mirror with Enhanced
Dynamic Range, IJEAT Journal, Volume-2,
Issue-3, February 2013.
[2] Current Mode Computational Circuits
for Analog Signal Processing, IJAREEIE,
Fig.12 Output of RC Phase Shift
Oscillator
Fig.14 Output of Wien Bridge
Oscillator
7. International Journal of Electrical and Computing Engineering
Vol. 1, Issue. 1, July – 2014 ISSN (Online): 2349-8218
29
Volume 3, Issue 4, April 2014.
[3] Analysis and Design of Analog
Integrated Circuits, 5th Edition by Paul
Gray, Paul Hurst, Stephen Lewis, Robert
Meyer.
[4] A High Performance Novel PMOS
Wilson Current Mirror, International Journal
of Electronics Engineering.
[5] Operational Transconductance Amplifier
by Achim Gratz.
[6] Transistor Level Implementation of
CMOS Basic Gates in 0.18μm Technology,
International Journal of Advanced Scientific
and Technical Research Issue 3 volume 6,
Nov.-Dec. 2013.
[7] Basic Circuit Cells of Analog MOSFET
Technology by Dr. John Choma.
[8] Constant-Current Threshold Voltage
Extraction in HSPICE for Nanoscale CMOS
Analog Design by Alvin Loke presented at
the Synopsys User Group (SNUG) San Jose
2010 Conference.
[9] Bias circuit Outline CMOS by Alber
Vargas
[10] Active Filter Design Using Operational
Transconductance Amplifiers: A Tutorial,
IEEE Circuits and Devices Magazine, Vol.1,
pp.20-32, March 1985.
[11] Analog Design for CMOS VLSI
Systems by Franco Malobert.
[12] LM 741 Operational Amplifier,
SNOSC25C by Texas Instruments–May
1998–Revised March 2013