This document summarizes the design of a low noise amplifier (LNA) operating at 2.45GHz. The LNA uses a cascode topology with inductive source degeneration implemented in a 120nm CMOS process. Simulation results show the LNA meets specifications for gain, return loss, output match, noise figure, and linearity over 2.4-2.5GHz. Variability analysis demonstrates performance remains within specifications with +/-10% parameter variations. The compact layout achieves good matching through careful device placement and use of appropriate passive components to minimize parasitics.

1. THE UNIVERSITY OF TEXAS AT DALLAS
ERIK JONSSON SCHOOL OF ENGINEERING &
COMPUTER SCIENCE
EERF 6330 RFIC DESIGN
SPRING 2016
PARASITIC-AWARE FULL CHIP DESIGN OF LNA RFIC AT
2.45GHZ USING IBM 130NM TECHNOLOGY
Professor: Kenneth O.
ILANGO JEYASUBRAMANIAN (ixj150230)
RAMKISHAN GUJULUVA NAGARAJAN DHANALAKSHMI (rxg154730)
SENIKAANTH KARTHIKEYAN (sxk150731)
SUMITHA THILAGARAJ (sxt151130)

2. Table of Contents
1 Circuit Description.......................................................................................................................... 3
2 Layout Description and philosophies behind the layout...................................................................... 4
3 Bonding diagram of the IC .............................................................................................................. 5
4 Instructions for how the circuit should be used. External components may be needed.......................... 5
5 Initial hand analysis of the circuit..................................................................................................... 7
6 Parasitic extraction/estimation.......................................................................................................... 8
7 Circuit simulation results................................................................................................................. 9
8 Comparison between hand analyses and simulation result................................................................ 10
8.1 Reason that might leads to the variation between hand calculation and simulation:....................... 10
9 Variability analysis........................................................................................................................ 11
9.1 -10% variation simulation:....................................................................................................... 11
9.2 +10% variation simulation:...................................................................................................... 12
10 Conclusion/Summary................................................................................................................... 14

3. 1 Circuit Description
The circuit topology we used for this project is a cascode LNA with inductive source degeneration
by using IBM 130nm CMOS technology. The designated operating frequency range is 2.4GHz-
2.5GHz.
Figure 1 shows the circuit of this LNA design. 6 bond pads with 80um*80um size are included in
this circuit. Each of these bond pads has two diodes connected inside for ESD protection.
For the input matching, a compensation capacitor is connected between the gate and source terminals of
the input device in order to tune the resonant frequency and input quality factor.
For the cascode device, a biasing voltage source is needed.
An inductor is connected between the voltage supply VDD and the cascode device which is used for 1)
blocking AC signal to AC ground; 2) output matching. Another two capacitors - one series and one shunt
are connected to the output for output matching.
ON_CHIP SCHEMATICOF LNA:

4. OFF_CHIP SCHEMATIC OF LNA:
Figure 1 LNA CIRCUIT
2 Layout Descriptionand philosophies behind the layout
The main focus lies in reducing the parasitic in order to keep the manufactured circuit as close as
possible to the simulated one. In this process choosing proper type of components as well as
implementing the routing with minimum resistance, inductance and capacitance is the target.
 The connection to the inductor is also shortened by placing the cascode device as closely to the main
inductor. The input capacitor was chosen from MOM type. The reason lies in well-defined
capacitance,low parasitic resistor and acceptable size in layout for the required value of 370.8fF.
 The output matching network capacitors are MIM type. This type of capacitor does not have the
capacitance density of MOS capacitors but instead, does not suffer from biasing challenges.
Hence,combinations of parallel MIM caps were implemented to obtain values of series cap and
shunt cap.
 The inductors are available in severalforms in the PDK. The chosen inductor is ind_inh which
has 2 terminals in the layout and schematic and is implemented in top metal layer (MA).
 Two GND bond-pads are placed in layout to minimize the chip ground connection inductance
and also minimizing on chip resistance for ground connection to all of components. The reason
for location of source bond-wire connection is to provide required 1.1 nH inductance, we had to
place is further from the pertaining GND connection to have enough length.
Total size of the chip is 720 µm * 720 µm which is a very compact design. ESD protection is provided by
the diode structure in the bond-pad cell provided by the TA and is included in the design. A snapshot of
the layout is shown in the figure 2 to illustrate the location of bond-pads and passive devices.

5. 3 Bonding diagram of the IC
Figure 2 shows the bonding diagram of the IC
From above bonding diagram, we defined the parasitic inductances associated with each port.
Port Vbias Source VDD RF_IN RF_OUT GND
Wire Length 1mm 1.1mm 1mm 1mm 1mm 1mm
Parasitic 1nH 1.1nH 1nH 1nH 1nH 1nH
Table 1 Parasitic Inductances Associated with Package
RF_INPUT
VBIAS
GND
VDD
RF_OUT

6. DRC_REPORT:
4 .Instructions on circuit design
Figure 3 shows the simulation circuit including the LNA and other external components .

7. Figure 4 : On chip components included in the design
 Two ports are placed at the input and output of this IC. These two ports simulate the input
source and output load. They both have characteristic impedance of 50 ohms.
 Three voltage sources are needed,VDD and Vbias1, and Vbias2. VDD is the voltage supply of
LNA,which is 1.2V in this design. Vbias1 is used for DC input of LNA,which is 550mV in this
design. Vbias2 is used to supply biasing voltage for cascode device which is 1.68V in this design.
The biasing voltage can be adjusted in a small range in order to optimize the transconductance
and current of the LNA circuit.
 Besides parasitic inductance as given above, a 4nH inductor (on PCB) should be connected to the
IC. This is used for both input matching and quality factor tuning. Including both parasitic
inductance and 6nH inductance, the total inductance of input is 8nH. It’s necessary to be aware
that any change in this inductance value will affect the input matching network and the input
quality factor, which means the variability, noise figure and linearity of this design might be
changed accordingly.

8. 5 Initial hand analysis of the circuit
Normally, we expect to get a high Q in the design in order to improve the power efficiency. But at the
meanwhile, some compromises between power and noise figure (or linearity) must be taken into account.
According to the given specifications for the operating frequency range 2.4GHz-2.5GHz, S11 should be
smaller than -10dB, then quality factor of inductor can be calculated:
Qin = Qgs/2 = |S11| / [sqrt(1-|S11|^2)*(w/w0-w0/w)]
Qin = 1.2 (assuming S11 = -15Db )
Calculation of Lg:
Lg = 2*Z0*Qin/w0, where Z0= 50ohms, Qin = 1.2, w0= 2.45GHz
Hence Lg = 5nH
Ls = Z0/(gm1*Qin*2*Z0*w0)
Assuming gm1= 20mS
Ls = 1nH
From the formula :
F= 1+[ (gemma *(1/gm1)*(1/Qin^2)/z0]
Gemma= 2/3 , Qin= 1.2, hence F= 1dB
Now, to calculate the value of compensation capacitor at gate-source of input transistort1:
Cgs(for tuning) = [Ct- Cin]
Ct= 1/w0*2Z0*Qin
Ct= 371.1202f
Cin is computed by DC simulation for input transistort1:
Cin = Cgs + 2Cgd = 72.96f + 2(24.49f)
Cin = 0.1202f
Therefore, Cgs = 371f
Let current Id= 10mA , W/L= 80um/0.12um , unCox= 666uA/V^2
Gain Gm= gm1^2 * Qin^2*L*w0*Ql*Z0
G= 18.9dB
For IIP3 calculation:
IIP3 = 1/ (4Qin^2 *z0) [(8/3theta)*(Vgs- Vth)] ; theta = 0.1
IIP3 = -4dB

9. 6 Parasitic extraction/estimation
Cgbo=17.06p;Cgdl=330p;Cgsl=330p;cj=1.05m; cjd=1.05m; cjs=1.05m; cjsw=50p; dlc=34.47n
Cox=3.9*8.85*10E-12/3.12*E-9=0.011
Cgso=Cox*dlc-Cgsl=Cox*34.47*E-9-3.3*E-10= 5.13E-11 F/m
Cgs=2/3CoxW*(L-2Lov)+Cgso*w=2/3*Cox*80E-6*(0.12E-6-2*1.4E-8)+ Cgso*80E-6 + NfCgb0L=
58f+4.104f+0.0818f=62.2fF
Cgdo=Cox*dlc-Cgdl= Cox*34.47E-9-3.3E-10= Cgso = 5.13E-11 F/m
Cgbo=2*dwc*Cox=3.76E-11F/m
Cgd = CgdoW = -5.13E-11 x80E-6=4.104fF
Cgs+2Cgd = 70.408fF
Cdb=Area*Cjo*(1-Vbd/ φb) mj+Perimeter* Cjswo*(1-Vbd/ φbsw)mjsw
=25*6E-6*0.36E-6*1E-4*(1+1.093/0.6)^0.5+(2*6+0.36*25)E-6*2E-10*(1+1.093/0.6)^0.5=63.44fF
7 Circuit simulation results
Figure 5: shows the simulation result for GT, S11, S22, noise figure and IIP3 simulation

10. According to the simulation result, we summarized all the specifications in table below.
Frequency GT (dB) S11 (dB) S22 (dB)
Noise Figure Linearity
(dB) (dBm)
2.4GHz 18.54 -22.8 -13.12 1.253
-4.60
2.45GHz 18.52 -31.11 -15.36 1.236
2.5GHz 18.06 -24.91 -12.71 1.236
Spec 12 -10 -10 2 -7dBm
Table 2 LNA Simulation Result
8 Comparisonbetweenhand analyses and simulation result
Frequency GT (dB) S11 (dB) S22 (dB)
Noise Figure Linearity
(dB) (dBm)
2.45GH
z
Hand Calc. 18.9 -15 <-20 1 -4
Simulation 18.52 -31.11 -15.36 1.236 -4.60
Spec 12 -10 -10 2 -7
Table 3 Comparison between hand calculation and simulation
9 Variability analysis
The strategy of variability analysis is to find out the worst case of frequency shift. Relationship between
each parameter and frequency is found according to the modeling of this LNA design. Since the circuit is
not purely unilateral, both input and output should be considered together for variability analysis.
9.1 -10% variation simulation:
Since S11 will be mainly affected by input parameters and S22 will be mainly affected by output
parameters,we will check the worst case of input and output separately.
 For S11, the input inductance and capacitance are lowered by 10% of initial value, which will
approximately move the resonant frequency to 10% higher.
 Then considering the feedback from output, we changed the output parameters (Ld, series cap and
shunt cap) by either 10% or -10% to find out the worst case combination. Below figure shows the
worst case when shunt cap reduced by 10%, series C increased by 10% and Ld increased by 10%.

11. Figure 6 :-10% variation simulation for S11 (worst case)
From above figure, we can see that the highest S11 is -10.56dB which is still higher than -10dB. But the
frequency has been shifted to 2.71GHz.
For S22, since Ld, shunt cap and series cap are all reverse proportional to resonant frequency, so their
values are lowered 10%, which means the resonant frequency of S22 is moved to 10% higher. Then we
changed the input parameters (Lg, compensation cap Cb) to find out the worst case combination. Below
figure shows the worst case we found out when Lg increased by 10%, compensation cap Cb increased by
10%.
Figure 7: -10% variation simulation for S22 (worst case)

12. From above figure, we can see that the highest S22 is -10.54dB which is still higher than -10dB. But the
frequency has been shifted to 2.57GHz.
9.2 +10% variation simulation:
Since S11 will be mainly affected by input parameters and S22 will be mainly affected by output
parameters,we will check the worst case of input and output separately.
For S11, the input inductance and capacitance increase by 10% of initial value, which will approximately
move the resonant frequency to 10% lower. Then considering the feedback from output, we changed the
output parameters (Ld, series cap and shunt cap) by either 10% or -10% to find out the worst case
combination. Below figure shows the worst case when shunt cap induced by 10%, series C decreased by
10% and Ld decreased by 10%.
Figure 8 : +10% variation simulation for S11 (worst case)
From above figure, we can see that the highest S11 is -14.07dB which is still higher than -10dB. But the
frequency has been shifted to 2.4GHz.
For S22, since Ld, shunt cap and series cap are all reverse proportional to resonant frequency, so their
values increase by 10%, which means the resonant frequency of S22 is moved to 10% lower. Then we
changed the input parameters (Lg, compensation cap Cb) to find out the worst case combination. Below
figure shows the worst case we found out when Lg decreased by 10%, compensation cap Cb decreased by
10%.

13. Figure 9: +10% variation simulation for S22 (worst case)
From above figure, we can see that the highest S22 is -16.1dB which is still higher than -10dB. But the
frequency has been shifted to 2.33GHz.
10 Conclusion/Summary
A low noise amplifier with inductive source degeneration has been presented. Philosophies of circuit
level design and layout are discussed to achieve the circuit specifications. Cadence simulation and
variability analysis shows that the designed CMOS circuit satisfied the system specifications.
Realized in 120nm CMOS technology, this LNA design shows relatively flat gain response, low noise,
linear and good impedance matching from 2.4GHz to 2.5GHz. The total DC current consumption of
LNA is around 10mA.
Furth more, one of the directions to further improve this design may point to the power efficiency. The
power gain we can get currently is around 2dB higher than the specification, if seems there’s still room to
further tune the circuit and get lower power consumption.
The authors would thank Professor O. for his instructions and suggestions during the project development