This document discusses register transfer language and microoperations in a central processing unit. It describes how data is transferred between registers and memory through bus and memory transfers. It also explains different types of microoperations including arithmetic operations like addition and subtraction, logic operations, and shift operations. Diagrams and tables are provided to illustrate register transfer, bus structure, arithmetic circuits, logic functions, and the function of an arithmetic logic shift unit.
This document provides information about register transfer and microoperations in a computer system. It includes definitions of register transfer language and different types of microoperations like register transfer, arithmetic, logic, and shift operations. Diagrams and examples of hardware components that perform these operations like arithmetic logic units, multiplexers, and buses are presented. Tables with details of the operations like truth tables and function tables are also included.
This document contains a syllabus for a Microprocessor and Microcontroller Laboratory course. It outlines experiments using 8-bit microprocessors and microcontrollers, including arithmetic operations, sorting arrays, interfacing with peripherals, and studying basic digital logic. Students will write assembly language programs for the 8085 microprocessor and 8051 microcontroller to perform tasks like addition, subtraction, multiplication, division, sorting arrays in ascending and descending order, and finding the largest and smallest values in an array. Experiments also include interfacing the microprocessors and microcontrollers with devices like ADCs, DACs, stepper motors, and logic gates.
This document provides an overview of register transfer and microoperations in computer architecture. It discusses register transfer language, register transfer, bus and memory transfers, and different types of microoperations including arithmetic, logic, and shift operations. Diagrams and examples are provided to illustrate concepts like register transfer, bus structure, arithmetic circuits, logic functions, and shift operations. The document is intended to teach fundamental concepts related to the low-level implementation of operations in a computer's central processing unit.
Microprocessor and Microcontroller Lab Manual!PRABHAHARAN429
The document describes experiments to be performed on an 8-bit microprocessor and microcontroller. It includes aims, block diagrams, flowcharts and assembly language programs for arithmetic operations, sorting an array, and interfacing experiments. Experiments cover topics like addition, subtraction, multiplication, division, ascending/descending order, maximum/minimum values, and interfacing components like ADCs, DACs, stepper motors. Similar experiments are outlined for an 8-bit microcontroller.
The document discusses different types of adders including ripple carry adder, carry look ahead adder, carry save adder, and carry select adder. It provides details on their working principles, test benches used for verification, gate counts, delays obtained from implementation, and a comparison of their performances. The objectives are to design and implement various adders and analyze their power and delay characteristics. Implementation of the different adders is completed while configuration on FPGA is pending.
The document discusses combinational logic circuits including adders, subtractors, and their design process. It begins with an overview of combinational vs sequential circuits. The design procedure is then outlined as starting with a specification, formulating a truth table, optimizing with K-maps or algebra, and developing the logic diagram. Examples are provided to design a 3-input/1-output circuit, BCD to excess-3 converter, half and full adders/subtractors. Exercise problems are also listed at the end involving designing incrementers, decrementers, and equality comparators.
This document discusses register transfer language and microoperations in a central processing unit. It describes how data is transferred between registers and memory through bus and memory transfers. It also explains different types of microoperations including arithmetic operations like addition and subtraction, logic operations, and shift operations. Diagrams and tables are provided to illustrate register transfer, bus structure, arithmetic circuits, logic functions, and the function of an arithmetic logic shift unit.
This document provides information about register transfer and microoperations in a computer system. It includes definitions of register transfer language and different types of microoperations like register transfer, arithmetic, logic, and shift operations. Diagrams and examples of hardware components that perform these operations like arithmetic logic units, multiplexers, and buses are presented. Tables with details of the operations like truth tables and function tables are also included.
This document contains a syllabus for a Microprocessor and Microcontroller Laboratory course. It outlines experiments using 8-bit microprocessors and microcontrollers, including arithmetic operations, sorting arrays, interfacing with peripherals, and studying basic digital logic. Students will write assembly language programs for the 8085 microprocessor and 8051 microcontroller to perform tasks like addition, subtraction, multiplication, division, sorting arrays in ascending and descending order, and finding the largest and smallest values in an array. Experiments also include interfacing the microprocessors and microcontrollers with devices like ADCs, DACs, stepper motors, and logic gates.
This document provides an overview of register transfer and microoperations in computer architecture. It discusses register transfer language, register transfer, bus and memory transfers, and different types of microoperations including arithmetic, logic, and shift operations. Diagrams and examples are provided to illustrate concepts like register transfer, bus structure, arithmetic circuits, logic functions, and shift operations. The document is intended to teach fundamental concepts related to the low-level implementation of operations in a computer's central processing unit.
Microprocessor and Microcontroller Lab Manual!PRABHAHARAN429
The document describes experiments to be performed on an 8-bit microprocessor and microcontroller. It includes aims, block diagrams, flowcharts and assembly language programs for arithmetic operations, sorting an array, and interfacing experiments. Experiments cover topics like addition, subtraction, multiplication, division, ascending/descending order, maximum/minimum values, and interfacing components like ADCs, DACs, stepper motors. Similar experiments are outlined for an 8-bit microcontroller.
The document discusses different types of adders including ripple carry adder, carry look ahead adder, carry save adder, and carry select adder. It provides details on their working principles, test benches used for verification, gate counts, delays obtained from implementation, and a comparison of their performances. The objectives are to design and implement various adders and analyze their power and delay characteristics. Implementation of the different adders is completed while configuration on FPGA is pending.
The document discusses combinational logic circuits including adders, subtractors, and their design process. It begins with an overview of combinational vs sequential circuits. The design procedure is then outlined as starting with a specification, formulating a truth table, optimizing with K-maps or algebra, and developing the logic diagram. Examples are provided to design a 3-input/1-output circuit, BCD to excess-3 converter, half and full adders/subtractors. Exercise problems are also listed at the end involving designing incrementers, decrementers, and equality comparators.
A Novel Efficient VLSI Architecture for IEEE 754 Floating point multiplier us...IJERA Editor
Due to advancement of new technology in the field of VLSI and Embedded system, there is an increasing
demand of high speed and low power consumption processor. Speed of processor greatly depends on its
multiplier as well as adder performance. In spite of complexity involved in floating point arithmetic, its
implementation is increasing day by day. Due to which high speed adder architecture become important. Several
adder architecture designs have been developed to increase the efficiency of the adder. In this paper, we
introduce an architecture that performs high speed IEEE 754 floating point multiplier using modified carry
select adder (CSA). Modified CSA depend on booth encoder (BEC) Technique. Booth encoder, Mathematics is
an ancient Indian system of Mathematics. Here we are introduced two carry select based design. These designs
are implementation Xilinx Vertex device family.
- The document discusses register transfer language and micro operations, which involve transferring binary data between registers and performing arithmetic, logic, and shift operations on data stored in registers.
- It describes the basic components of a central processing unit, including registers, arithmetic logic units, multiplexers, and control units that coordinate micro operations.
- Micro operations include arithmetic operations like addition, subtraction, and increment/decrement, as well as logic operations like AND, OR, XOR, and shifts that manipulate data at the bit level.
This document discusses combinational circuit design and provides examples of various combinational logic circuits. It begins with an introduction that defines combinational and sequential circuits. The remainder of the document provides details on specific combinational logic circuits including half adders, full adders, subtractors, encoders, decoders, multiplexers, comparators, and code converters. Worked examples are provided for each circuit type using truth tables, Karnaugh maps, and logic diagrams. Applications of decoders for implementing functions like a full adder are also described.
This document discusses combinational logic circuits. It begins by defining combinational circuits as those with no storage or feedback, so their outputs depend only on current inputs. It then provides the steps to analyze a combinational circuit by labeling outputs and determining Boolean functions until reaching the outputs. Design procedures are also outlined. Specific combinational circuits discussed include half and full adders used for binary addition, with their truth tables and logic implementations shown. Subtraction using borrow is also briefly introduced.
Implementation and Simulation of Ieee 754 Single-Precision Floating Point Mul...inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
This document outlines the syllabus for the subject Digital Principles and System Design. It contains 5 units that cover topics such as Boolean algebra, logic gates, combinational logic, sequential logic, asynchronous sequential logic, memory and programmable logic. The objectives of the course are to understand logic simplification methods, design combinational and sequential logic circuits using HDL, understand various types of memory and programmable devices. The syllabus allocates 45 periods to cover all the units in depth. Relevant textbooks and references are also provided.
This document discusses various methods for improving the performance of multiplication operations, including using shifts and adds instead of actual multiplication, and Booth's algorithm. It examines these methods through examples of multiplying pairs of hexadecimal numbers. Booth's algorithm works by repeatedly adding or subtracting the multiplicand based on examining pairs of bits in the multiplier, allowing multiplication to be performed with only shifts. The document also covers non-restoring and non-performing division algorithms.
Adapted from Harris & Harris Digital Design and Computer Arch.docxnettletondevon
Adapted from Harris & Harris “Digital Design and Computer Architecture” resources
EECE 343 Advanced Logic Design
Assignment 1
Introduction
In this assignment, you will design a simple digital circuit called a full adder. Along the way,
you will learn to use the Altera field-programmable gate array (FPGA) tools to enter a schematic,
simulate your design, and download your design onto a chip.
After completing the assignment, you are required to turn in something from each part. Refer to
the “Deliverables” section at the end of this handout before beginning the assignment.
Note:
For additional information about how to use Quartus II, refer to the following tutorials on
BbLearn under the tutorials section:
• Getting Started with DE series boards
• Quartus II Introduction
• ModelSim GUI Introduction
• Using ModelSim
• DE2_Pin Table
Background: Adders
An adder, not surprisingly, is a circuit whose output is the binary sum of its inputs. Since adders
are needed to perform arithmetic, they are an essential part of any computer. The full adder will
be an integral part of the microprocessor that you design in later assignments.
A full adder has three inputs (A, B, Cin) and two outputs (S, Cout), as shown in Figure 1. Inputs A
and B each represent 1-bit binary numbers that are being added, and S represents a bit of the
resulting sum.
A B
S
C
out
C
in+
Figure 1. Full adder
The Cin (carry in) and Cout (carry out) signals are used when adding numbers that are more than
one bit long. To understand how these signals are used, consider how you would add the binary
numbers 101 and 001 by hand:
1
101
+ 001
110
As with decimal addition, you first add the two least significant bits. Since 1+1=10 (in binary),
you place a zero in the least significant bit of the sum and carry the 1. Then you add the next
two bits with the carry, and place a 1 in the second bit of the sum. Finally, you add the most
significant bits (with no carry) and get a 1 in the most significant bit of the sum.
When a sum is performed using full adders, each adder handles a single column of the sum.
Figure 2 shows how to build a circuit that adds two 3-digit binary numbers using three full
adders. The Cout for each bit is connected to the Cin of the next most significant bit. Each bit of
the 3-bit numbers being added is connected to the appropriate adder’s inputs and the three sum
outputs (S2:0) make up the full 3-bit sum result.
S
2
A
1
B
1
S
1
A
0
B
0
S
0
C
1
C
0
C
out +++
A
2
B
2
C
in
Figure 2. 3-bit adder
Note that the rightmost Cin input is unnecessary, since there can never be a carry into the first
column of the sum. This would allow us to use a half adder for the first bit of the sum. A half
adder is similar to a full adder, except that it lacks a Cin and is thus simpler to implement. To
save you design time, however, you will only build a full adder in.
The document describes a 4-bit synchronous ALU design project including schematics and layouts. Key components designed were logic gates, a carry lookahead adder, D flip-flop, 4-bit register, and multiplexer. Layouts were extracted and LVS was performed to verify the layouts matched the schematics. Simulation shows the ALU performs 4-bit addition, 2's complement, add-traction, 4-input NAND, 4-input NOR, and 1's complement as required for different input codes.
This document provides an introduction to a digital design course. It discusses the recommended textbook, course description, grading breakdown, and course outline. The course focuses on fundamental digital concepts like number systems, Boolean algebra, logic gates, combinational and sequential logic. It will cover topics such as binary numbers, Boolean functions, logic gate minimization, adders/subtractors, multiplexers, flip-flops, and finite state machines. Students are expected to attend every lecture and participate in classroom discussions. Grades will be based on projects, midterm exams, and quizzes/assignments.
This document outlines the key topics covered in Chapter 1 of a course on digital systems and computer design fundamentals. It includes:
- An introduction to digital systems and information representation.
- Details on number systems like binary, octal, and hexadecimal, along with arithmetic operations and base conversion between these systems.
- Overviews of topics like binary coded decimal, Gray codes, alphanumeric codes, and parity bits.
- Explanations of binary addition, subtraction, multiplication, and the conversion between decimal and binary numbers.
- Information on the course instructor, textbook, grading policy, exam dates, and course content which includes topics on combinational logic circuits, sequential circuits, and computer architecture.
Computer organization and architecture lab manual Shankar Gangaju
This document contains information about a computer organization and architecture lab. It includes details about the lab report format, integer representation using fixed point, two's complement, addition and subtraction algorithms and hardware. It also discusses logical operations, and provides MATLAB code examples for 4-bit binary addition, subtraction, multiplication and restoring division algorithms.
Ec2203 digital electronics questions anna university by www.annaunivedu.organnaunivedu
EC2203 Digital Electronics Anna University Important Questions for 3rd Semester ECE , EC2203 Digital Electronics Important Questions, 3rd Sem Question papers,
http://www.annaunivedu.org/digital-electronics-ec-2203-previous-year-question-paper-for-3rd-sem-ece-anna-univ-question/
Chapter 07 Digital Alrithmetic and Arithmetic CircuitsSSE_AndyLi
This document discusses digital arithmetic and arithmetic circuits. It covers topics such as signed and unsigned binary numbers, addition, subtraction, overflow, binary-coded decimal codes, and the implementation of adders using full adders in VHDL. Specifically, it defines common digital arithmetic concepts like carries, sums, overflow, and binary number representations. It also describes half adders, full adders, ripple carry adders, and how to construct multi-bit adders using full adder components in VHDL.
Lab 9 D-Flip Flops: Shift Register and Sequence CounterKatrina Little
This document describes an experiment involving designing a 4-bit shift register and sequence counter using D-flip flops. It includes building the circuits in an FPGA tool, simulating their operation, and downloading them to a development board. A debouncing circuit is added to prevent erroneous output from noisy button inputs. The objectives of introducing sequential circuit design and implementing a shift register and sequence counter are met.
Digital devices like computers, watches, and phones use binary numbers encoded as signals with two values, 0 and 1. Basic logic gates like AND, OR, and NOT are used to build more complex digital circuits. Boolean algebra describes the logic operations performed by these circuits using rules for binary true/false values. Circuits add binary numbers by performing full adder logic on corresponding bits with sum and carry outputs.
The document discusses combinational logic circuits. It describes combinational logic design procedures including specification, formulation, optimization, technology mapping, and verification. It also discusses analysis procedures for logic diagrams, including labeling gate outputs and determining Boolean functions. Additional topics covered include half adders, full adders, binary adders, decoders, encoders, multiplexers, priority encoders, and binary-coded decimal to seven-segment displays. Diagrams and truth tables are provided for various logic gates and circuits.
This document provides an outline for a course on digital logic design. It includes the course title and credit hours, topics that will be covered such as Boolean algebra, logic gates, combinational and sequential circuits, programmable logic devices, and memory. It also lists recommended textbooks and provides the grading breakdown. Examples of analogue and digital quantities, signals, and number systems are given. Common logic gates such as AND, OR, NOT, NAND and NOR are described along with their truth tables and applications. Combinational circuits, functional devices, sequential circuits and memory are also introduced.
The document introduces computer architecture and system software. It discusses the differences between computer organization and computer architecture. It describes the basic components of a computer based on the Von Neumann architecture, which consists of four main sub-systems: memory, ALU, control unit, and I/O. The document also discusses bottlenecks of the Von Neumann architecture and differences between microprocessors and microcontrollers. It covers computer arithmetic concepts like integer representation, floating point representation using IEEE 754 standard, and number bases conversion. Additional topics include binary operations like addition, subtraction using complements, and multiplication algorithms like Booth's multiplication.
A Novel Efficient VLSI Architecture for IEEE 754 Floating point multiplier us...IJERA Editor
Due to advancement of new technology in the field of VLSI and Embedded system, there is an increasing
demand of high speed and low power consumption processor. Speed of processor greatly depends on its
multiplier as well as adder performance. In spite of complexity involved in floating point arithmetic, its
implementation is increasing day by day. Due to which high speed adder architecture become important. Several
adder architecture designs have been developed to increase the efficiency of the adder. In this paper, we
introduce an architecture that performs high speed IEEE 754 floating point multiplier using modified carry
select adder (CSA). Modified CSA depend on booth encoder (BEC) Technique. Booth encoder, Mathematics is
an ancient Indian system of Mathematics. Here we are introduced two carry select based design. These designs
are implementation Xilinx Vertex device family.
- The document discusses register transfer language and micro operations, which involve transferring binary data between registers and performing arithmetic, logic, and shift operations on data stored in registers.
- It describes the basic components of a central processing unit, including registers, arithmetic logic units, multiplexers, and control units that coordinate micro operations.
- Micro operations include arithmetic operations like addition, subtraction, and increment/decrement, as well as logic operations like AND, OR, XOR, and shifts that manipulate data at the bit level.
This document discusses combinational circuit design and provides examples of various combinational logic circuits. It begins with an introduction that defines combinational and sequential circuits. The remainder of the document provides details on specific combinational logic circuits including half adders, full adders, subtractors, encoders, decoders, multiplexers, comparators, and code converters. Worked examples are provided for each circuit type using truth tables, Karnaugh maps, and logic diagrams. Applications of decoders for implementing functions like a full adder are also described.
This document discusses combinational logic circuits. It begins by defining combinational circuits as those with no storage or feedback, so their outputs depend only on current inputs. It then provides the steps to analyze a combinational circuit by labeling outputs and determining Boolean functions until reaching the outputs. Design procedures are also outlined. Specific combinational circuits discussed include half and full adders used for binary addition, with their truth tables and logic implementations shown. Subtraction using borrow is also briefly introduced.
Implementation and Simulation of Ieee 754 Single-Precision Floating Point Mul...inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online.
This document outlines the syllabus for the subject Digital Principles and System Design. It contains 5 units that cover topics such as Boolean algebra, logic gates, combinational logic, sequential logic, asynchronous sequential logic, memory and programmable logic. The objectives of the course are to understand logic simplification methods, design combinational and sequential logic circuits using HDL, understand various types of memory and programmable devices. The syllabus allocates 45 periods to cover all the units in depth. Relevant textbooks and references are also provided.
This document discusses various methods for improving the performance of multiplication operations, including using shifts and adds instead of actual multiplication, and Booth's algorithm. It examines these methods through examples of multiplying pairs of hexadecimal numbers. Booth's algorithm works by repeatedly adding or subtracting the multiplicand based on examining pairs of bits in the multiplier, allowing multiplication to be performed with only shifts. The document also covers non-restoring and non-performing division algorithms.
Adapted from Harris & Harris Digital Design and Computer Arch.docxnettletondevon
Adapted from Harris & Harris “Digital Design and Computer Architecture” resources
EECE 343 Advanced Logic Design
Assignment 1
Introduction
In this assignment, you will design a simple digital circuit called a full adder. Along the way,
you will learn to use the Altera field-programmable gate array (FPGA) tools to enter a schematic,
simulate your design, and download your design onto a chip.
After completing the assignment, you are required to turn in something from each part. Refer to
the “Deliverables” section at the end of this handout before beginning the assignment.
Note:
For additional information about how to use Quartus II, refer to the following tutorials on
BbLearn under the tutorials section:
• Getting Started with DE series boards
• Quartus II Introduction
• ModelSim GUI Introduction
• Using ModelSim
• DE2_Pin Table
Background: Adders
An adder, not surprisingly, is a circuit whose output is the binary sum of its inputs. Since adders
are needed to perform arithmetic, they are an essential part of any computer. The full adder will
be an integral part of the microprocessor that you design in later assignments.
A full adder has three inputs (A, B, Cin) and two outputs (S, Cout), as shown in Figure 1. Inputs A
and B each represent 1-bit binary numbers that are being added, and S represents a bit of the
resulting sum.
A B
S
C
out
C
in+
Figure 1. Full adder
The Cin (carry in) and Cout (carry out) signals are used when adding numbers that are more than
one bit long. To understand how these signals are used, consider how you would add the binary
numbers 101 and 001 by hand:
1
101
+ 001
110
As with decimal addition, you first add the two least significant bits. Since 1+1=10 (in binary),
you place a zero in the least significant bit of the sum and carry the 1. Then you add the next
two bits with the carry, and place a 1 in the second bit of the sum. Finally, you add the most
significant bits (with no carry) and get a 1 in the most significant bit of the sum.
When a sum is performed using full adders, each adder handles a single column of the sum.
Figure 2 shows how to build a circuit that adds two 3-digit binary numbers using three full
adders. The Cout for each bit is connected to the Cin of the next most significant bit. Each bit of
the 3-bit numbers being added is connected to the appropriate adder’s inputs and the three sum
outputs (S2:0) make up the full 3-bit sum result.
S
2
A
1
B
1
S
1
A
0
B
0
S
0
C
1
C
0
C
out +++
A
2
B
2
C
in
Figure 2. 3-bit adder
Note that the rightmost Cin input is unnecessary, since there can never be a carry into the first
column of the sum. This would allow us to use a half adder for the first bit of the sum. A half
adder is similar to a full adder, except that it lacks a Cin and is thus simpler to implement. To
save you design time, however, you will only build a full adder in.
The document describes a 4-bit synchronous ALU design project including schematics and layouts. Key components designed were logic gates, a carry lookahead adder, D flip-flop, 4-bit register, and multiplexer. Layouts were extracted and LVS was performed to verify the layouts matched the schematics. Simulation shows the ALU performs 4-bit addition, 2's complement, add-traction, 4-input NAND, 4-input NOR, and 1's complement as required for different input codes.
This document provides an introduction to a digital design course. It discusses the recommended textbook, course description, grading breakdown, and course outline. The course focuses on fundamental digital concepts like number systems, Boolean algebra, logic gates, combinational and sequential logic. It will cover topics such as binary numbers, Boolean functions, logic gate minimization, adders/subtractors, multiplexers, flip-flops, and finite state machines. Students are expected to attend every lecture and participate in classroom discussions. Grades will be based on projects, midterm exams, and quizzes/assignments.
This document outlines the key topics covered in Chapter 1 of a course on digital systems and computer design fundamentals. It includes:
- An introduction to digital systems and information representation.
- Details on number systems like binary, octal, and hexadecimal, along with arithmetic operations and base conversion between these systems.
- Overviews of topics like binary coded decimal, Gray codes, alphanumeric codes, and parity bits.
- Explanations of binary addition, subtraction, multiplication, and the conversion between decimal and binary numbers.
- Information on the course instructor, textbook, grading policy, exam dates, and course content which includes topics on combinational logic circuits, sequential circuits, and computer architecture.
Computer organization and architecture lab manual Shankar Gangaju
This document contains information about a computer organization and architecture lab. It includes details about the lab report format, integer representation using fixed point, two's complement, addition and subtraction algorithms and hardware. It also discusses logical operations, and provides MATLAB code examples for 4-bit binary addition, subtraction, multiplication and restoring division algorithms.
Ec2203 digital electronics questions anna university by www.annaunivedu.organnaunivedu
EC2203 Digital Electronics Anna University Important Questions for 3rd Semester ECE , EC2203 Digital Electronics Important Questions, 3rd Sem Question papers,
http://www.annaunivedu.org/digital-electronics-ec-2203-previous-year-question-paper-for-3rd-sem-ece-anna-univ-question/
Chapter 07 Digital Alrithmetic and Arithmetic CircuitsSSE_AndyLi
This document discusses digital arithmetic and arithmetic circuits. It covers topics such as signed and unsigned binary numbers, addition, subtraction, overflow, binary-coded decimal codes, and the implementation of adders using full adders in VHDL. Specifically, it defines common digital arithmetic concepts like carries, sums, overflow, and binary number representations. It also describes half adders, full adders, ripple carry adders, and how to construct multi-bit adders using full adder components in VHDL.
Lab 9 D-Flip Flops: Shift Register and Sequence CounterKatrina Little
This document describes an experiment involving designing a 4-bit shift register and sequence counter using D-flip flops. It includes building the circuits in an FPGA tool, simulating their operation, and downloading them to a development board. A debouncing circuit is added to prevent erroneous output from noisy button inputs. The objectives of introducing sequential circuit design and implementing a shift register and sequence counter are met.
Digital devices like computers, watches, and phones use binary numbers encoded as signals with two values, 0 and 1. Basic logic gates like AND, OR, and NOT are used to build more complex digital circuits. Boolean algebra describes the logic operations performed by these circuits using rules for binary true/false values. Circuits add binary numbers by performing full adder logic on corresponding bits with sum and carry outputs.
The document discusses combinational logic circuits. It describes combinational logic design procedures including specification, formulation, optimization, technology mapping, and verification. It also discusses analysis procedures for logic diagrams, including labeling gate outputs and determining Boolean functions. Additional topics covered include half adders, full adders, binary adders, decoders, encoders, multiplexers, priority encoders, and binary-coded decimal to seven-segment displays. Diagrams and truth tables are provided for various logic gates and circuits.
This document provides an outline for a course on digital logic design. It includes the course title and credit hours, topics that will be covered such as Boolean algebra, logic gates, combinational and sequential circuits, programmable logic devices, and memory. It also lists recommended textbooks and provides the grading breakdown. Examples of analogue and digital quantities, signals, and number systems are given. Common logic gates such as AND, OR, NOT, NAND and NOR are described along with their truth tables and applications. Combinational circuits, functional devices, sequential circuits and memory are also introduced.
The document introduces computer architecture and system software. It discusses the differences between computer organization and computer architecture. It describes the basic components of a computer based on the Von Neumann architecture, which consists of four main sub-systems: memory, ALU, control unit, and I/O. The document also discusses bottlenecks of the Von Neumann architecture and differences between microprocessors and microcontrollers. It covers computer arithmetic concepts like integer representation, floating point representation using IEEE 754 standard, and number bases conversion. Additional topics include binary operations like addition, subtraction using complements, and multiplication algorithms like Booth's multiplication.
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Digital Twins Computer Networking Paper Presentation.pptxaryanpankaj78
A Digital Twin in computer networking is a virtual representation of a physical network, used to simulate, analyze, and optimize network performance and reliability. It leverages real-time data to enhance network management, predict issues, and improve decision-making processes.
1. International Islamic University, Islamabad
Faculty of Engineering & Technology
Department of Electrical and Computer Engineering
CO 202 L
Computer Architecture and Organization
Lab Manual
Subject Teacher:
Lab Instructor:
Prepared by:
Engr. Rashid Farid Chishti
Lecturer, Department of Electrical and Computer Engineering.
Faculty of Engineering and Technology.
International Islamic University, Islamabad.
2. Page i
Names of Group Members
Student
Name
Reg.
No.
Student
Name
Reg.
No.
Student
Name
Reg.
No.
Student
Name
Reg.
No.
3. Page ii
CO 202 L
Computer Architecture and Organization
Lab Manual
OBJECTIVE
The objective of this lab is to make students learn about fundamental concepts
of Object-Oriented Programming and its implementation in C++ language.
The lab covers the concepts of classes, objects, attributes, operator
overloading, inheritance, virtual functions, and friend functions.
CLO CLO Description DOMAIN PLO
01 Apply the concepts of Microprocessor in SAP-1 C3 01
02 Demonstrate the skills to design and analyze
Microprocessor based designs.
P3 02
03 Participate actively in performing the
procedure.
A2 09
CLO: Course Learning Outcome.
PLO: Program Learning Outcome.
4. Page iii
Microprocessor and Microcontroller Lab Rubrics
Name: Reg. No.: Signature: Instructor:
a) PSYCHOMOTOR (To be judged in the field/lab during experiment)
Sr.
No.
Criteria
Level 1
(0%)
Level 2
(25%)
Level 3
(50%)
Level 4
(75%)
Level 5
(100%)
Lab
Lab
1
Lab
2
Lab
3
Lab
4
Lab
5
Lab
6
Lab
7
Lab
8
Lab
9
Lab
10
Lab
11
Lab
12
Lab
13
Lab
14
1
Practical
Implementation/
Arrangement of
Equipment
0 1.25 2.5 3.75 5 Weightage 5 5 5 5 5 5 5 5 5 5 5 5 5 5
Absent
With several
critical errors,
incomplete and
not neat
With few
errors,
incomplete
and not
neat
With some
errors,
complete
but not neat
Without
errors,
complete
and neat
Obtained
2
Use of
Equipment or
Simulation/
Programming
Tool
0 0.5 1 1.5 2 Weightage 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Absent
Limited
competence
Some
competence
Considerable
competence
Competence Obtained
(b) COGNITIVE (To be judged on the copy of experiment submitted)
Sr.
No.
Criteria
Level 1
(0%)
Level 2
(25%)
Level 3
(50%)
Level 4
(75%)
Level 5
(100%)
Lab
Lab
1
Lab
2
Lab
3
Lab
4
Lab
5
Lab
6
Lab
7
Lab
8
Lab
9
Lab
10
Lab
11
Lab
12
Lab
13
Lab
14
3
Algorithm Design
or Data Record,
Analysis and
Evaluation
0 0.25 0.5 0.75 1 Weightage 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Absent Incorrect
Complete
with some
errors
Complete
with few
errors
Complete
and
Accurate
Obtained
(c) AFFECTIVE (To be judged in the field/lab during experiment)
Sr.
No.
Criteria
Level 1
(0%)
Level 2
(25%)
Level 3
(50%)
Level 4
(75%)
Level 5
(100%)
Lab
Lab
1
Lab
2
Lab
3
Lab
4
Lab
5
Lab
6
Lab
7
Lab
8
Lab
9
Lab
10
Lab
11
Lab
12
Lab
13
Lab
14
4
Level of
Participation &
Attitude to
Achieve
Individual/Group
Goals
0 0.5 1 1.5 2 Weightage 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Absent
Rare sensible
interaction
Some
sensible
interaction
Good
sensible
interaction
Encouraging
sensible
interaction
Obtained
5 TOTAL OBTAINED MARKS (Out of 10):
5. Page iv
Table of Contents
Lab 01: Design of Half adder, Full Adder, 4 bit Adder and 4 bit Adder Subtractor ........................ 1
Lab 02: Design of 8 bit Arithmetic Circuit....................................................................................... 4
Lab 03: Design of 8 bit Logic Circuit................................................................................................ 6
Lab 04: Design of 8 bit Shifter......................................................................................................... 8
Lab 05: Design of 1 bit Arithmetic Logic Shift Unit ....................................................................... 10
Lab 06: Design of 16 bit Arithmetic Logic Shift Unit ..................................................................... 12
Lab 07: Design of a Program Counter........................................................................................... 15
Lab 08: Design of T State Generator............................................................................................. 16
Lab 09: Introduction to Assembly Language and Assembler........................................................ 19
Lab 10: Assembly Programming: Using Jump and Loop............................................................... 24
Lab 11: Assembly Programming: 32 bit Addition and Multiplication........................................... 26
Lab 12: Assembly Programming: Subroutines.............................................................................. 28
Lab 13: Assembly Programming: Input and Output Programming .............................................. 30
Lab 14: Assembly Programming: Packing and Comparing Numbers............................................ 31
Lab 15: Implementation of SAP-1 Part-A...................................................................................... 32
Lab 16: Implementation of SAP-1 Part-B...................................................................................... 33
6. Page 1
Lab 01: Design of Half adder, Full Adder, 4 bit Adder and 4 bit Adder
Subtractor
Figure 1.1: Logic Diagram of Half Adder
Input Output
A B C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Table 1.1: Truth table of Half Adder
Figure 1.2: Logic Diagram Full Adder
Input Output
A B Cin Carry Sum
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Table 1.2: Truth table of Full Adder
A
B
S
C
A
B
Cin
Carry
Sum
7. Page 2
Figure 1.3: Logic Diagram of 4 bit Adder
Figure 1.4: Block Diagram of 4 bit Adder
Cin
Cout
A3 A2 A1 A0
B3 B2 B1 B0
S3 S2 S1 S0
8. Page 3
Figure 1.5: Logic Diagram of 4 bit Adder and Subtractor
Figure 1.6: Block Diagram of 4 bit Adder and Subtractor
Cin
Cout
A3 A2 A1 A0
B3 B2 B1 B0
S3 S2 S1 S0
9. Page 4
Lab 02: Design of 8 bit Arithmetic Circuit
Figure 2.1: Logic Diagram of 4 to 1 Multiplexer
Select Output
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
Table 2.1: Truth Table of 4 to 1 Multiplexer
S1 S0 Cin Operation Function
0 0 0 F = A Transfer A
0 0 1 F = A + 1 Increment A
0 1 0 F = A + B Addition
0 1 1 F = A + B + 1 Add with carry
1 0 0 F = A + B’ Subtract with borrow
1 0 1 F = A + B’ + 1 Subtraction
1 1 0 F = A - 1 Decrement A
1 1 1 F = A Transfer A
Table 2.2: Function Table of 8 bit Arithmetic Circuit
11. Page 6
Lab 03: Design of 8 bit Logic Circuit
Figure 3.1: Logic Diagram of 1 bit Logic Unit
S1 S0 Output Operation
0 0 E = A & B AND
0 1 E = A | B OR
1 0 E = A ^ B XOR
1 1 E = A' Complement A
Table 3.1: Operation Table of 1 bit Logic Unit
15. Page 10
Lab 05: Design of 1 bit Arithmetic Logic Shift Unit
Figure 5.1: Logic Diagram of 1 bit Arithmetic Unit
Figure 5.2: Logic Diagram of 1 bit Logic Unit
16. Page 11
Figure 5.3: Logic Diagram of 1 bit Arithmetic and Logic Unit
S3 S2 S1 S0 Cin Operation Function
0 0 0 0 0 F = A Transfer A
0 0 0 0 1 F = A + 1 Increment A
0 0 0 1 0 F = A + B Addition
0 0 0 1 1 F = A + B + 1 Add with Carry
0 0 1 0 0 F = A + B’ Subtract with borrow
0 0 1 0 1 F = A + B’ + 1 Subtraction
0 0 1 1 0 F = A – 1 Decrement A
0 0 1 1 1 F = A Transfer A
0 1 0 0 X F = A & B Bitwise AND
0 1 0 1 X F = A | B Bitwise OR
0 1 1 0 X F = A ^ B Bitwise XOR
0 1 1 1 X F = A’ Bitwise A NOT
1 0 X X X F = shr A Shift Right A
1 1 X X X F = shl A Shift Left A
Table 5.1: Function table for Arithmetic Logic Shift Unite
17. Page 12
Lab 06: Design of 16 bit Arithmetic Logic Shift Unit
S3 S2 S1 S0 Cin Operation Function
0 0 0 0 0 F = A Transfer A
0 0 0 0 1 F = A + 1 Increment A
0 0 0 1 0 F = A + B Addition
0 0 0 1 1 F = A + B + 1 Add with Carry
0 0 1 0 0 F = A + B’ Subtract with borrow
0 0 1 0 1 F = A + B’ + 1 Subtraction
0 0 1 1 0 F = A – 1 Decrement A
0 0 1 1 1 F = A Transfer A
0 1 0 0 X F = A & B Bitwise AND
0 1 0 1 X F = A | B Bitwise OR
0 1 1 0 X F = A ^ B Bitwise XOR
0 1 1 1 X F = A’ Bitwise A NOT
1 0 X X X F = shl A Shift Left A
1 1 X X X F = shr A Shift Right A
Table 6.1: Function Table for Arithmetic Logic Shift Unite
Figure 6.1: Logic diagram of 16 bit Arithmetic Logic Shift Unite on Next two Pages
20. Page 15
Lab 07: Design of a Program Counter.
Figure 7.1: Logic Diagram of 1 bit JK Flip Flop
Figure 7.2: Logic Diagram of 4 bit Program Counter
Lab Task: Similarly make an 8 bit Program Counter
K J
Q
CLK
21. Page 16
Lab 08: Design of T State Generator
Figure 8.1: Logic Diagram of 3 to 8 Decoder
22. Page 17
Figure 8.2: Logic Diagram of 4 to 16 Decoder
Figure 8.3: Logic and Block Diagram of 1 bit JK Flip Flop
J K CLK
R
Q
23. Page 18
Figure 8.4: Logic Diagram of 4 bit Sequence Counter (SC)
Figure 8.5: Logic Diagram of 16 T State Generator
24. Page 19
Lab 09: Introduction to Assembly Language and Assembler
Figure 9.1: Block Diagram Basic Computer Registered to Common Bus
25. Page 20
Memory Reference Instructions
Hexadecimal Code
Symbol I = 0 I = 1 Description
AND 0xxx 8xxx AND memory word to AC
AC ← AC & M[AR]
ADD 1xxx 9xxx Add memory word to AC
AC ← AC & M[AR] , E ← Cout
LDA 2xxx Axxx Load memory word to AC
AC ← M[AR]
STA 3xxx Bxxx Store content of AC in memory
M[AR] ← AC
BUN 4xxx Cxxx Branch unconditionally
PC ← AR
BSA 5xxx Dxxx Branch and save return address
M[AR] ← PC , PC ← AR + 1
ISZ 6xxx Exxx Increment and skip if zero
M[AR] ← M[AR] + 1
If( M[AR] + 1=0 ) then PC ← PC + 1
Register Reference Instructions
CLA 7800 Clear AC
CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instruction if AC positive
SNA 7008 Skip next instruction if AC negative
SZA 7004 Skip next instruction if AC zero
SZE 7002 Skip next instruction if E is 0
HLT 7001 Halt Computer
IO Instructions
INP F800 Input character to AC
OUT F400 Output character from AC
SKI F200 Skip on input flag
SKO F100 Skip on output flag
ION F080 Interrupt on
IOF F040 Interrupt off
TABLE 9.1: Basic Computer Instructions
26. Page 21
Instruction T State Micro Operation
Instruction
Cycle
T0 AR←PC
T1 IR ← M[AR] , AR ← PC + 1
T2 AR ← IR(0-11) , I ← IR(15) , Decode ← IR(12-14)
Register Reference Instructions
CLA T3 AC ← 0 , SC ← 0
CLE T3 E ← 0 , SC ← 0
CMA T3 AC ← AC_Bar , SC ← 0
CME T3 E ← E_Bar , SC ← 0
CIR T3 AC ← shr AC , AC(15) ← E , E ← AC(0) , SC ← 0
CIL T3 AC ← shl AC , AC(0) ← E , E ← AC(15) , SC ← 0
INC T3 AC ← AC + 1, SC ← 0
SPA T3 if(AC(15)=0) then PC ← PC + 1 , SC ← 0
SNA T3 if(AC(15)=1) then PC ← PC + 1 , SC ← 0
SZA T3 if(AC=0) then PC ← PC + 1, SC ← 0
SZE T3 if(E=0) then PC ← PC + 1 , SC ← 0
HLT T3 S ← 0 , SC ← 0
Memory Reference Instructions
AND T3
T4
T5
If(I-=1) AR ← M[AR] else “do nothing”
DR ← M[AR]
AC ← AC & DR, 0 ← SC
ADD T3
T4
T5
If(I-=1) AR ← M[AR] else “do nothing”
DR ← M[AR]
AC ← AC + DR , 0 ← SC
LDA T3
T4
T5
If(I-=1) AR ← M[AR] else “do nothing”
DR ← M[AR]
AR ← DR , 0 ← SC
STA T3
T4
If(I-=1) AR ← M[AR] else “do nothing”
M[AR] ← AC , 0 ← SC
BUN T3
T4
If(I-=1) AR ← M[AR] else “do nothing”
PC ← AR , 0 ← SC
BSA T3
T4
T5
If(I-=1) AR ← M[AR] else “do nothing”
M[AR] ← PC , AR← AR + 1
PC ← AR , 0 ← SC
ISZ T3
T4
T5
T6
If(I-=1) AR ← M[AR] else “do nothing”
DR ← M[AR]
DR ← DR + 1
M[AR] ← DR , if(DR=0) then PC ← PC + 1 , 0 ← SC
TABLE 9.2: Basic Computer Instructions with T States
27. Page 22
Please Download “Mano Simulator” App from Google Play Store
Screenshot 9.1: Assembly Program to Add Two Numbers
Screenshot 9.1: Machine Code
28. Page 23
Screenshot 9.3: Micro Operations of each command
Lab 09 Task: Write a program to add these three numbers: 68 + 51 – 34 = 85 = 0x55
29. Page 24
Lab 10: Assembly Programming: Using Jump and Loop
Program 10.1: Program to subtract two Numbers
/ 83 - (-23) = 106 = 0x6A
ORG 0 /Starting Address is 0
LDA SUB /Load -23 to AC
CMA /Complement AC
INC /Increment AC
ADD MIN /Add 83 to AC
STA DIF /Store difference
HLT /Halt computer
MIN,DEC 83 /Minuend
SUB,DEC -23 /Subtrahend
DIF,HEX 0 /Difference stored here
END /End of symbolic program
/ Sum four numbers
ORG 0 /Starting Address
LDA ADS /Load first address
STA PTR /Store in pointer
LDA NBR /Load -4
STA CTR /Store in counter
CLA /Clear accumulator
LOP, ADD PTR I /Add an operand to AC
ISZ PTR /Increment pointer
ISZ CTR /Increment counter
BUN LOP /Repeat loop again
STA SUM /Store sum
HLT /Halt
ADS, HEX 10 /First address of operand
30. Page 25
Program 10.2: Add four Numbers
Lab 10 Task: Using Loop and Jump Instructions, write a program to add these numbers:
11 + 22 + 33 + 44 + 55 + 66 - 77 - 88
PTR, HEX 0 /Reserved for a pointer
NBR, DEC -4 /loop 4 times
CTR, HEX 0 /Reserved for a counter
SUM, HEX 0 /Sum is stored here
ORG 10 /address of data
HEX 11 /1st operand
HEX 22 /2nd operand
HEX 33 /3rd operand
HEX 44 /Last operand
END /End of symbolic program
31. Page 26
Lab 11: Assembly Programming: 32 bit Addition and Multiplication
Program 11.1: Adding two 32-bit Numbers
/ 0x22221111 + 0x4444F777 = 0x66670888
ORG 0
LDA AL
ADD BL /Add B low, Carry in E
STA CL /Store in C low
CLA /Clear AC
CIL /Circulate to bring carry into AC(16)
ADD AH /Add A high and Carry
ADD BH /Add B high
STA CH /Store in C high
HLT
AL, HEX 1111 /Location of operands
AH, HEX 2222
BL, HEX F777
BH, HEX 4444
CL, HEX 0
CH, HEX 0
END /end of program
32. Page 27
Program 11.2: Multiply Two Numbers
Lab Task: Write a program to subtract two 32-bit numbers: 60,000 – 40,000 = 20,000
/ Program to multiply two numbers F*B = A5, 15*11 = 165
ORG 0
LOP, CLE /Clear E bit
LDA Y /Load multiplier
CIR /Transfer multiplier bit to E
STA Y /Store shifted multiplier
SZE /Check if bit is zero
BUN ONE /Bit is one; go to ONE
BUN ZRO /Bit is zero; go to ZRO
ONE, LDA X /Load multiplicand
ADD P /Add to partial product
STA P /Store partial product
CLE /Clear E
ZRO, LDA X /Load multiplicand
CIL /Shift left
STA X /Store shifted multiplicand
ISZ CTR /Increment counter
BUN LOP /Counter not zero; repeat loop
HLT /Counter is zero; halt
CTR, DEC -8 /loop 8 times
X, HEX 000F /Multiplicand stored here
Y, HEX 000B /Multiplier stored here
P, HEX 0 /Product formed here
END /end of program
33. Page 28
Lab 12: Assembly Programming: Subroutines
Program 12.1: Using Subroutine
ORG 100 / Main program
LDA X / Load X
BSA SH4 / Branch to subroutine
STA X / Store shifted number
LDA Y / Load Y
BSA SH4 / Branch to subroutine again
STA Y / Store shifted number
HLT / halt
X, HEX 1234 / shift left this number
Y, HEX 4321 / shift left this number too
/ This is the Subroutine to shift left a number 4 times
SH4, HEX 0 / Store return address here
CIL / Circulate left 1st time
CIL / Circulate left 2nd time
CIL / Circulate left 3rd time
CIL / Circulate left 4th time
AND MSK / Set AC(0-4) to zero
BUN SH4 I / Return to main program
MSK, HEX FFF0 / Mask operand
END / End of Program
34. Page 29
Program 12.2: Passing Parameters to a Subroutine
Lab Task: Write a subroutine to perform bitwise XOR two numbers
ORG 200 / Main program
LDA X / Load X
BSA OR / Branch to subroutine OR
HEX 3AF6 / Second Operand Stored Here
STA Y / Subroutine returns here
HLT / halt computer
X, HEX 7B95 / First operand stored here
Y, HEX 0 / Result is stored here
OR, HEX 0 / Subroutine OR
CMA / Complement first operand
STA TMP / Store in temporary location
LDA OR I / Load second operand
CMA / Complement second operand
AND TMP / AND complemented first operand
CMA / Complement again to get OR
ISZ OR / Increment return address
BUN OR I / Return to main program
TMP, HEX 0 / Temporary Storage
END