The document is a lab manual for the Computer Architecture and Organization course at the International Islamic University, Islamabad, focusing on object-oriented programming in C++. It includes practical lab exercises on microprocessor design, programming, and assembly language, outlining the objectives, methodologies, and rubrics for evaluation. Each lab covers specific design tasks, such as creating adders, counters, and implementing assembly language programs.

1. International Islamic University, Islamabad
Faculty of Engineering & Technology
Department of Electrical and Computer Engineering
CO 202 L
Computer Architecture and Organization
Lab Manual
Subject Teacher:
Lab Instructor:
Prepared by:
Engr. Rashid Farid Chishti
Lecturer, Department of Electrical and Computer Engineering.
Faculty of Engineering and Technology.
International Islamic University, Islamabad.

2. Page i
Names of Group Members
Student
Name
Reg.
No.
Student
Name
Reg.
No.
Student
Name
Reg.
No.
Student
Name
Reg.
No.

3. Page ii
CO 202 L
Computer Architecture and Organization
Lab Manual
OBJECTIVE
The objective of this lab is to make students learn about fundamental concepts
of Object-Oriented Programming and its implementation in C++ language.
The lab covers the concepts of classes, objects, attributes, operator
overloading, inheritance, virtual functions, and friend functions.
CLO CLO Description DOMAIN PLO
01 Apply the concepts of Microprocessor in SAP-1 C3 01
02 Demonstrate the skills to design and analyze
Microprocessor based designs.
P3 02
03 Participate actively in performing the
procedure.
A2 09
CLO: Course Learning Outcome.
PLO: Program Learning Outcome.

4. Page iii
Microprocessor and Microcontroller Lab Rubrics
Name: Reg. No.: Signature: Instructor:
a) PSYCHOMOTOR (To be judged in the field/lab during experiment)
Sr.
No.
Criteria
Level 1
(0%)
Level 2
(25%)
Level 3
(50%)
Level 4
(75%)
Level 5
(100%)
Lab
Lab
1
Lab
2
Lab
3
Lab
4
Lab
5
Lab
6
Lab
7
Lab
8
Lab
9
Lab
10
Lab
11
Lab
12
Lab
13
Lab
14
1
Practical
Implementation/
Arrangement of
Equipment
0 1.25 2.5 3.75 5 Weightage 5 5 5 5 5 5 5 5 5 5 5 5 5 5
Absent
With several
critical errors,
incomplete and
not neat
With few
errors,
incomplete
and not
neat
With some
errors,
complete
but not neat
Without
errors,
complete
and neat
Obtained
2
Use of
Equipment or
Simulation/
Programming
Tool
0 0.5 1 1.5 2 Weightage 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Absent
Limited
competence
Some
competence
Considerable
competence
Competence Obtained
(b) COGNITIVE (To be judged on the copy of experiment submitted)
Sr.
No.
Criteria
Level 1
(0%)
Level 2
(25%)
Level 3
(50%)
Level 4
(75%)
Level 5
(100%)
Lab
Lab
1
Lab
2
Lab
3
Lab
4
Lab
5
Lab
6
Lab
7
Lab
8
Lab
9
Lab
10
Lab
11
Lab
12
Lab
13
Lab
14
3
Algorithm Design
or Data Record,
Analysis and
Evaluation
0 0.25 0.5 0.75 1 Weightage 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Absent Incorrect
Complete
with some
errors
Complete
with few
errors
Complete
and
Accurate
Obtained
(c) AFFECTIVE (To be judged in the field/lab during experiment)
Sr.
No.
Criteria
Level 1
(0%)
Level 2
(25%)
Level 3
(50%)
Level 4
(75%)
Level 5
(100%)
Lab
Lab
1
Lab
2
Lab
3
Lab
4
Lab
5
Lab
6
Lab
7
Lab
8
Lab
9
Lab
10
Lab
11
Lab
12
Lab
13
Lab
14
4
Level of
Participation &
Attitude to
Achieve
Individual/Group
Goals
0 0.5 1 1.5 2 Weightage 2 2 2 2 2 2 2 2 2 2 2 2 2 2
Absent
Rare sensible
interaction
Some
sensible
interaction
Good
sensible
interaction
Encouraging
sensible
interaction
Obtained
5 TOTAL OBTAINED MARKS (Out of 10):

5. Page iv
Table of Contents
Lab 01: Design of Half adder, Full Adder, 4 bit Adder and 4 bit Adder Subtractor ........................ 1
Lab 02: Design of 8 bit Arithmetic Circuit....................................................................................... 4
Lab 03: Design of 8 bit Logic Circuit................................................................................................ 6
Lab 04: Design of 8 bit Shifter......................................................................................................... 8
Lab 05: Design of 1 bit Arithmetic Logic Shift Unit ....................................................................... 10
Lab 06: Design of 16 bit Arithmetic Logic Shift Unit ..................................................................... 12
Lab 07: Design of a Program Counter........................................................................................... 15
Lab 08: Design of T State Generator............................................................................................. 16
Lab 09: Introduction to Assembly Language and Assembler........................................................ 19
Lab 10: Assembly Programming: Using Jump and Loop............................................................... 24
Lab 11: Assembly Programming: 32 bit Addition and Multiplication........................................... 26
Lab 12: Assembly Programming: Subroutines.............................................................................. 28
Lab 13: Assembly Programming: Input and Output Programming .............................................. 30
Lab 14: Assembly Programming: Packing and Comparing Numbers............................................ 31
Lab 15: Implementation of SAP-1 Part-A...................................................................................... 32
Lab 16: Implementation of SAP-1 Part-B...................................................................................... 33

6. Page 1
Lab 01: Design of Half adder, Full Adder, 4 bit Adder and 4 bit Adder
Subtractor
Figure 1.1: Logic Diagram of Half Adder
Input Output
A B C S
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0
Table 1.1: Truth table of Half Adder
Figure 1.2: Logic Diagram Full Adder
Input Output
A B Cin Carry Sum
0 0 0 0 0
0 0 1 0 1
0 1 0 0 1
0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1
Table 1.2: Truth table of Full Adder
A
B
S
C
A
B
Cin
Carry
Sum

7. Page 2
Figure 1.3: Logic Diagram of 4 bit Adder
Figure 1.4: Block Diagram of 4 bit Adder
Cin
Cout
A3 A2 A1 A0
B3 B2 B1 B0
S3 S2 S1 S0

8. Page 3
Figure 1.5: Logic Diagram of 4 bit Adder and Subtractor
Figure 1.6: Block Diagram of 4 bit Adder and Subtractor
Cin
Cout
A3 A2 A1 A0
B3 B2 B1 B0
S3 S2 S1 S0

9. Page 4
Lab 02: Design of 8 bit Arithmetic Circuit
Figure 2.1: Logic Diagram of 4 to 1 Multiplexer
Select Output
S1 S0 Y
0 0 I0
0 1 I1
1 0 I2
1 1 I3
Table 2.1: Truth Table of 4 to 1 Multiplexer
S1 S0 Cin Operation Function
0 0 0 F = A Transfer A
0 0 1 F = A + 1 Increment A
0 1 0 F = A + B Addition
0 1 1 F = A + B + 1 Add with carry
1 0 0 F = A + B’ Subtract with borrow
1 0 1 F = A + B’ + 1 Subtraction
1 1 0 F = A - 1 Decrement A
1 1 1 F = A Transfer A
Table 2.2: Function Table of 8 bit Arithmetic Circuit

10. Page 5
Figure 2.2: Logic Diagram of 8 bit Arithmetic Circuit

11. Page 6
Lab 03: Design of 8 bit Logic Circuit
Figure 3.1: Logic Diagram of 1 bit Logic Unit
S1 S0 Output Operation
0 0 E = A & B AND
0 1 E = A | B OR
1 0 E = A ^ B XOR
1 1 E = A' Complement A
Table 3.1: Operation Table of 1 bit Logic Unit

12. Page 7
Figure 3.2: Logic Diagram of 8 bit Logic Unit

13. Page 8
Lab 04: Design of 8 bit Shifter
Figure 4.1: Logic Diagram 2 to 1 Multiplexer
.
Select Output
Operation
S H7 H6 H5 H4 H3 H2 H1 H0
0 0 A7 A6 A5 A4 A3 A2 A1 Shift Right
1 A6 A5 A4 A3 A2 A1 A0 0 Shift Left
Table 4.1: Operation Table of 8 bit Shifter

14. Page 9
Figure 4.2: Logic Diagram of 8 bit Shifter

15. Page 10
Lab 05: Design of 1 bit Arithmetic Logic Shift Unit
Figure 5.1: Logic Diagram of 1 bit Arithmetic Unit
Figure 5.2: Logic Diagram of 1 bit Logic Unit

16. Page 11
Figure 5.3: Logic Diagram of 1 bit Arithmetic and Logic Unit
S3 S2 S1 S0 Cin Operation Function
0 0 0 0 0 F = A Transfer A
0 0 0 0 1 F = A + 1 Increment A
0 0 0 1 0 F = A + B Addition
0 0 0 1 1 F = A + B + 1 Add with Carry
0 0 1 0 0 F = A + B’ Subtract with borrow
0 0 1 0 1 F = A + B’ + 1 Subtraction
0 0 1 1 0 F = A – 1 Decrement A
0 0 1 1 1 F = A Transfer A
0 1 0 0 X F = A & B Bitwise AND
0 1 0 1 X F = A | B Bitwise OR
0 1 1 0 X F = A ^ B Bitwise XOR
0 1 1 1 X F = A’ Bitwise A NOT
1 0 X X X F = shr A Shift Right A
1 1 X X X F = shl A Shift Left A
Table 5.1: Function table for Arithmetic Logic Shift Unite

17. Page 12
Lab 06: Design of 16 bit Arithmetic Logic Shift Unit
S3 S2 S1 S0 Cin Operation Function
0 0 0 0 0 F = A Transfer A
0 0 0 0 1 F = A + 1 Increment A
0 0 0 1 0 F = A + B Addition
0 0 0 1 1 F = A + B + 1 Add with Carry
0 0 1 0 0 F = A + B’ Subtract with borrow
0 0 1 0 1 F = A + B’ + 1 Subtraction
0 0 1 1 0 F = A – 1 Decrement A
0 0 1 1 1 F = A Transfer A
0 1 0 0 X F = A & B Bitwise AND
0 1 0 1 X F = A | B Bitwise OR
0 1 1 0 X F = A ^ B Bitwise XOR
0 1 1 1 X F = A’ Bitwise A NOT
1 0 X X X F = shl A Shift Left A
1 1 X X X F = shr A Shift Right A
Table 6.1: Function Table for Arithmetic Logic Shift Unite
Figure 6.1: Logic diagram of 16 bit Arithmetic Logic Shift Unite on Next two Pages

18. Page 13

19. Page 14

20. Page 15
Lab 07: Design of a Program Counter.
Figure 7.1: Logic Diagram of 1 bit JK Flip Flop
Figure 7.2: Logic Diagram of 4 bit Program Counter
Lab Task: Similarly make an 8 bit Program Counter
K J
Q
CLK

21. Page 16
Lab 08: Design of T State Generator
Figure 8.1: Logic Diagram of 3 to 8 Decoder

22. Page 17
Figure 8.2: Logic Diagram of 4 to 16 Decoder
Figure 8.3: Logic and Block Diagram of 1 bit JK Flip Flop
J K CLK
R
Q

23. Page 18
Figure 8.4: Logic Diagram of 4 bit Sequence Counter (SC)
Figure 8.5: Logic Diagram of 16 T State Generator

24. Page 19
Lab 09: Introduction to Assembly Language and Assembler
Figure 9.1: Block Diagram Basic Computer Registered to Common Bus

25. Page 20
Memory Reference Instructions
Hexadecimal Code
Symbol I = 0 I = 1 Description
AND 0xxx 8xxx AND memory word to AC
AC ← AC & M[AR]
ADD 1xxx 9xxx Add memory word to AC
AC ← AC & M[AR] , E ← Cout
LDA 2xxx Axxx Load memory word to AC
AC ← M[AR]
STA 3xxx Bxxx Store content of AC in memory
M[AR] ← AC
BUN 4xxx Cxxx Branch unconditionally
PC ← AR
BSA 5xxx Dxxx Branch and save return address
M[AR] ← PC , PC ← AR + 1
ISZ 6xxx Exxx Increment and skip if zero
M[AR] ← M[AR] + 1
If( M[AR] + 1=0 ) then PC ← PC + 1
Register Reference Instructions
CLA 7800 Clear AC
CLE 7400 Clear E
CMA 7200 Complement AC
CME 7100 Complement E
CIR 7080 Circulate right AC and E
CIL 7040 Circulate left AC and E
INC 7020 Increment AC
SPA 7010 Skip next instruction if AC positive
SNA 7008 Skip next instruction if AC negative
SZA 7004 Skip next instruction if AC zero
SZE 7002 Skip next instruction if E is 0
HLT 7001 Halt Computer
IO Instructions
INP F800 Input character to AC
OUT F400 Output character from AC
SKI F200 Skip on input flag
SKO F100 Skip on output flag
ION F080 Interrupt on
IOF F040 Interrupt off
TABLE 9.1: Basic Computer Instructions

26. Page 21
Instruction T State Micro Operation
Instruction
Cycle
T0 AR←PC
T1 IR ← M[AR] , AR ← PC + 1
T2 AR ← IR(0-11) , I ← IR(15) , Decode ← IR(12-14)
Register Reference Instructions
CLA T3 AC ← 0 , SC ← 0
CLE T3 E ← 0 , SC ← 0
CMA T3 AC ← AC_Bar , SC ← 0
CME T3 E ← E_Bar , SC ← 0
CIR T3 AC ← shr AC , AC(15) ← E , E ← AC(0) , SC ← 0
CIL T3 AC ← shl AC , AC(0) ← E , E ← AC(15) , SC ← 0
INC T3 AC ← AC + 1, SC ← 0
SPA T3 if(AC(15)=0) then PC ← PC + 1 , SC ← 0
SNA T3 if(AC(15)=1) then PC ← PC + 1 , SC ← 0
SZA T3 if(AC=0) then PC ← PC + 1, SC ← 0
SZE T3 if(E=0) then PC ← PC + 1 , SC ← 0
HLT T3 S ← 0 , SC ← 0
Memory Reference Instructions
AND T3
T4
T5
If(I-=1) AR ← M[AR] else “do nothing”
DR ← M[AR]
AC ← AC & DR, 0 ← SC
ADD T3
T4
T5
If(I-=1) AR ← M[AR] else “do nothing”
DR ← M[AR]
AC ← AC + DR , 0 ← SC
LDA T3
T4
T5
If(I-=1) AR ← M[AR] else “do nothing”
DR ← M[AR]
AR ← DR , 0 ← SC
STA T3
T4
If(I-=1) AR ← M[AR] else “do nothing”
M[AR] ← AC , 0 ← SC
BUN T3
T4
If(I-=1) AR ← M[AR] else “do nothing”
PC ← AR , 0 ← SC
BSA T3
T4
T5
If(I-=1) AR ← M[AR] else “do nothing”
M[AR] ← PC , AR← AR + 1
PC ← AR , 0 ← SC
ISZ T3
T4
T5
T6
If(I-=1) AR ← M[AR] else “do nothing”
DR ← M[AR]
DR ← DR + 1
M[AR] ← DR , if(DR=0) then PC ← PC + 1 , 0 ← SC
TABLE 9.2: Basic Computer Instructions with T States

27. Page 22
Please Download “Mano Simulator” App from Google Play Store
Screenshot 9.1: Assembly Program to Add Two Numbers
Screenshot 9.1: Machine Code

28. Page 23
Screenshot 9.3: Micro Operations of each command
Lab 09 Task: Write a program to add these three numbers: 68 + 51 – 34 = 85 = 0x55

29. Page 24
Lab 10: Assembly Programming: Using Jump and Loop
Program 10.1: Program to subtract two Numbers
/ 83 - (-23) = 106 = 0x6A
ORG 0 /Starting Address is 0
LDA SUB /Load -23 to AC
CMA /Complement AC
INC /Increment AC
ADD MIN /Add 83 to AC
STA DIF /Store difference
HLT /Halt computer
MIN,DEC 83 /Minuend
SUB,DEC -23 /Subtrahend
DIF,HEX 0 /Difference stored here
END /End of symbolic program
/ Sum four numbers
ORG 0 /Starting Address
LDA ADS /Load first address
STA PTR /Store in pointer
LDA NBR /Load -4
STA CTR /Store in counter
CLA /Clear accumulator
LOP, ADD PTR I /Add an operand to AC
ISZ PTR /Increment pointer
ISZ CTR /Increment counter
BUN LOP /Repeat loop again
STA SUM /Store sum
HLT /Halt
ADS, HEX 10 /First address of operand

30. Page 25
Program 10.2: Add four Numbers
Lab 10 Task: Using Loop and Jump Instructions, write a program to add these numbers:
11 + 22 + 33 + 44 + 55 + 66 - 77 - 88
PTR, HEX 0 /Reserved for a pointer
NBR, DEC -4 /loop 4 times
CTR, HEX 0 /Reserved for a counter
SUM, HEX 0 /Sum is stored here
ORG 10 /address of data
HEX 11 /1st operand
HEX 22 /2nd operand
HEX 33 /3rd operand
HEX 44 /Last operand
END /End of symbolic program

31. Page 26
Lab 11: Assembly Programming: 32 bit Addition and Multiplication
Program 11.1: Adding two 32-bit Numbers
/ 0x22221111 + 0x4444F777 = 0x66670888
ORG 0
LDA AL
ADD BL /Add B low, Carry in E
STA CL /Store in C low
CLA /Clear AC
CIL /Circulate to bring carry into AC(16)
ADD AH /Add A high and Carry
ADD BH /Add B high
STA CH /Store in C high
HLT
AL, HEX 1111 /Location of operands
AH, HEX 2222
BL, HEX F777
BH, HEX 4444
CL, HEX 0
CH, HEX 0
END /end of program

32. Page 27
Program 11.2: Multiply Two Numbers
Lab Task: Write a program to subtract two 32-bit numbers: 60,000 – 40,000 = 20,000
/ Program to multiply two numbers F*B = A5, 15*11 = 165
ORG 0
LOP, CLE /Clear E bit
LDA Y /Load multiplier
CIR /Transfer multiplier bit to E
STA Y /Store shifted multiplier
SZE /Check if bit is zero
BUN ONE /Bit is one; go to ONE
BUN ZRO /Bit is zero; go to ZRO
ONE, LDA X /Load multiplicand
ADD P /Add to partial product
STA P /Store partial product
CLE /Clear E
ZRO, LDA X /Load multiplicand
CIL /Shift left
STA X /Store shifted multiplicand
ISZ CTR /Increment counter
BUN LOP /Counter not zero; repeat loop
HLT /Counter is zero; halt
CTR, DEC -8 /loop 8 times
X, HEX 000F /Multiplicand stored here
Y, HEX 000B /Multiplier stored here
P, HEX 0 /Product formed here
END /end of program

33. Page 28
Lab 12: Assembly Programming: Subroutines
Program 12.1: Using Subroutine
ORG 100 / Main program
LDA X / Load X
BSA SH4 / Branch to subroutine
STA X / Store shifted number
LDA Y / Load Y
BSA SH4 / Branch to subroutine again
STA Y / Store shifted number
HLT / halt
X, HEX 1234 / shift left this number
Y, HEX 4321 / shift left this number too
/ This is the Subroutine to shift left a number 4 times
SH4, HEX 0 / Store return address here
CIL / Circulate left 1st time
CIL / Circulate left 2nd time
CIL / Circulate left 3rd time
CIL / Circulate left 4th time
AND MSK / Set AC(0-4) to zero
BUN SH4 I / Return to main program
MSK, HEX FFF0 / Mask operand
END / End of Program

34. Page 29
Program 12.2: Passing Parameters to a Subroutine
Lab Task: Write a subroutine to perform bitwise XOR two numbers
ORG 200 / Main program
LDA X / Load X
BSA OR / Branch to subroutine OR
HEX 3AF6 / Second Operand Stored Here
STA Y / Subroutine returns here
HLT / halt computer
X, HEX 7B95 / First operand stored here
Y, HEX 0 / Result is stored here
OR, HEX 0 / Subroutine OR
CMA / Complement first operand
STA TMP / Store in temporary location
LDA OR I / Load second operand
CMA / Complement second operand
AND TMP / AND complemented first operand
CMA / Complement again to get OR
ISZ OR / Increment return address
BUN OR I / Return to main program
TMP, HEX 0 / Temporary Storage
END

35. Page 30
Lab 13: Assembly Programming: Input and Output Programming

36. Page 31
Lab 14: Assembly Programming: Packing and Comparing Numbers

37. Page 32
Lab 15: Implementation of SAP-1 Part-A

38. Page 33
Lab 16: Implementation of SAP-1 Part-B