This document provides information about register transfer and microoperations in a computer system. It includes definitions of register transfer language and different types of microoperations like register transfer, arithmetic, logic, and shift operations. Diagrams and examples of hardware components that perform these operations like arithmetic logic units, multiplexers, and buses are presented. Tables with details of the operations like truth tables and function tables are also included.

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By:
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2. 2
Chapter Four
Register Transfer and Micro operations
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3. 3
Contents
• 4-1 Register Transfer Language
• 4-2 Register Transfer
• 4-3 Bus and Memory transfers
• 4-4 Arithmetic Micro operations
• 4-5 Logic Micro operations
• 4-6 Shift Micro operations
• 4-7 Arithmetic School.edhole. cloogimc shift unit

4. 4
Register Transfer Language
 The set of register it contains and their
functions.
 The sequence of micro operations performed
on the binary information stored in the
register.
 The control that initiated the sequence of
micro operations.
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5. 5
Figure 4-1
Block diagram of register
R1
Register R Showing individual bits
R2
7 6 5 4 3 2 1 0
PC(H) PC(L)
15 0
15 8 7 0
Numbering of bits Divide into two parts
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6. 6
Figure 4-2
Transfer from R1 to R2
P: R2 R1
R2
Contro
l
circuit
P Load
n
Clock
R1
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7. 7
Figure 4-2 b
Timing diagram
Clock
t t+1
load
Transfer occurs
here
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8. 8
Table 4-1
Basic symbols for register transfer
Symbol Description Examples
Letters
(and numerals)
Parentheses ( )
Arrow
Comma ,
Denotes a register
Denotes a part of a
register
Denotes transfer of
information
Separates two micro
operations
MAR,
R2
R2(0-7),R2(L)
R2 R1
R2 R1, R1
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9. 9
Figure 4-3
BUS AND MEMORY TRANSFER
4 – L I N E
C O M M O N
B U S
4 x 1
M U X 0
3 2 1 0
D0 C0 B0 A0
D2 D1 D0 C2 C1 C0 B2 B1 B0 A2 A1 A0
3 2 1 0
4 x 1
M U X 1
3 2 1 0
4 x 1
M U X 2
3 2 1 0
4 x 1
M U X 3
3 2 1 0
D2 C2 B2 A2 D1 C1 B1 A1
3 2 1 0 3 2 1 0 3 2 1 0
REGISTER D REGISTER C REGISTER B REGISTER A
S1
S0
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10. 10
Table 4-2
Function table for bus
s1 s2 Register selected
A
B
C
D
0 0
0 1
1 0
1 1
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11. 11
Figure 4-4
Graphical symbol for Three-state Bus Buffers
Normal input A
Control input C
Output Y=A if C=1
High-impedance if C=0
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12. 12
Figure 4-5
Bus line with three state-buffers
Bus line for bit 0 A0
B0
C0
D0
Select
Enable
0
1
2
3
2 x 4
Decoder
S0
S0
E
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13. 13
Memory Transfer
Read: DR M[AR]
Write: M[AR] R1
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14. 14
Arithmetic Micro operations
 Register transfer micro operations transfer binary
information from one register to another.
 Arithmetic micro operation performs arithmetic operations
on numeric data stored in register.
 Logic micro operations perform bit manipulation operations
on nonnumeric data stored in register.
 Shift micro operations perform shift operations on data
stored register.
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15. 15
Table 4-3
Arithmetic Micro operation
Symbolic
designation
Description
R3 R1+ R2
R3 R1- R2
R2 R2
R2 R2 +
1
R3 ¬ R1+ R2 + 1
R1 R1 +
R1 1 R1 -
1
Contents of R1 plus R2 transferred to
R3
Contents of R1 minus R2 transferred to
R3
Complement the contents of R2( 1’s
complement)
2’s complement the contents of
R2(negate)
R1 plus the2’s complement of
R2(subtraction)
Increment the contents of R1 by one
School.edhole.cDoemcrement the contents of R1 by one

16. 16
Figure 4-6
4 – Bit binary adder
B0 A0
B3 A3 B2 A2 B1 A1
C3 C2 C1
FA FA FA FA
C0
C4 S3 S2 S1 S0
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17. B3 A3 B2 A2 B1 A1 B0 A0 M
17
Figure 4-7
4 – bit adder subtractor
FA C3 FA C2 FA C1 FA C0
C4 S3 S2 S1 S0
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18. A3 A2 A1 A0 1
x y x y x y x y
18
Figure 4-8
4 – Bit binary Incrementer
HA HA HA HA
C S C S C S C S
C4 S3 S2 S1 S0
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19. 19
S1
S0
0
1
23
S1
S0
0
1
3 2
Figure 4-9
4-bit arithmetic circuit
Cin
S0
S1
A0
B0
B1
B2
B3
Xo Co
X1 C1
X2 C2
X3 C3
Do
D1
D2
D3
Cout
yo C1
y1 C2
y2 C3
y3 C4
0 1
S1
S0
0
1
3 2
S1
S0
0
1
3 2
4 x 1
MUX
4 x 1
MUX
4 x 1
MUX
4 x 1
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20. 20
Table 4-4
Arithmetic circuit function table
Select
S1 S0 Cin
Input Output
Y D = A + Y + Cin
Micro operation
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
B
B
B
B
0
0
1
1
D = A + B
D = A + B + 1
D = A + B
D = A + B + 1
D = A
D = A + 1
D = A - 1
D = A
Add
Add with carry
Subt. with borrow
Subtract
Transfer A
Increment A
Decrement A
Transfer A
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21. 21
Table 4 – 5
Truth table for 16 Function of two variables
x y F0 F1 F2 F3 F4
F5 F6 F7 F8 F9F10 F11 F12F13 F14 F15
0
0
1
1
0
1
0
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
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22. 22
TABLE 4-6
SIXTEEN LOGIC MICRO OPERATIONS
Boolean function Micro operations Name
F0 = 0 F  0 Clear
F1 = xy F  A ^ B And
F2 = xy’ F  A ^ B
F3 = x F  A Transfer A
F4 = x’y F  A ^ B
F5 = y F  B Transfer B
F6 = x y F  A B
Exclusive-or
F7 = x + y F A ٧ B OR
F8 = (x + Y)’ F  A V B NOR
F9 = (x Y)’ F A B Exclusive-NOR
F10 = y’ F B Complement B
F11 = x + y ‘ F A V B
F12 = x’ F A Complement A
F13 = x’ + y F  A v B
F14 = (xy)’ F  A ^ B NAND
F15 = 1 F  all 1’s Set to all 1’s School.edhole.com

23. 23
Figure 4-10
One stage of logic circuit
4x1
MUX
S1 S0 Output Operation
0
0
1
1
0
1
0
1
E = A ^ B
E = A v B
E = A B
E = A
AND
OR
XOR
COMPLEMEN
T
E i
S1
S0
A i
B i 0
1
2
3
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24. 24
Figure 4-12
4-bit combinational circuit shifter
S
0
1
S
0
1
S
0
1
S
0
1
Mux
Mux
Mux
Mux
Select
S
0
1
Output
H0
H0
H1
H2
H3
H1 H2 H3
IR
A1
A0
A2
A1
A3
A2
Il
Ao
A1
A3
A4
Serial
input (IR)
Serial
input (IL)
Select
0 for shift right
1 for shift left
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25. 25
Figure 4-13
One stage of arithmetic logic shift unit
Select
0
1
2
3
Di
Ei
shr
shl
S3
S2
S1
Ai -1
Ai+1
Bi
Ai
Ci
One stage of
arithmetic
circuit
Ci+1
S0
One stage of
logic circuit
F i
4 x 1
MUX
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26. 26
Operation Select
S3 S2 S1 S0 Cin Operation Function
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
x
0
1
0
1
x
0
1
1
0
x
0
1
1
1
x
1
0
x
x
x
1
1
x
x
x
F = A
F = A + 1
F = A + B
F = A + B +1
F = A + B
F = A + B + 1
F = A -1
F = A
F = A ^ B
F = A v B
F = A B
F = A
F = shr A
R = shl A
Transfer A
Increment A
Addition
Add with carry
Subtract with
borrow
Subtraction
Decrement A
Transfer A
AND
OR
XOR
Complement A
Shift right A into F
Shift left A into F
Table 4-8
Function table for arithmetic logic shift unit
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