you may know about JFET biasing derivation and its graphical representation and also Q point stability.

1. JFET( VOLTAGE DIVIDER
BIAS )
7-3 Topic # 5 (Group 9)
Sheraz Ahmed
20B-029-CE
Instructor: Sir Anzar Alam

2. OVERVIEW ABOUT JFET
• We know that a bipolar junction transistor is constructed using two PN-junctions in
the main current carrying path between the Emitter and the Collector terminals. The
Junction Field Effect Transistor (JUGFET or JFET) has no PN-junctions but instead has
a narrow piece of high resistivity semiconductor material forming a “Channel” of
either N-type or P-type silicon for the majority carriers to flow through with two
ohmic electrical connections at either end commonly called the Drain and the
Source respectively.
• There are two basic configurations of junction field effect transistor, the N-channel
JFET and the P-channel JFET.

3. VOLTAGE DIVIDER BIASING OF A
JFET
• Two series connected resistors form a voltage divider circuit. The voltage at the
gate terminal can be calculated by voltage division rule. In this way, the applied
drain voltage is utilized to get the gate terminal voltage. A resistance is inserted
into source terminal in series. The device current flows through the resistance
and causes a voltage drop. If this source voltage drop is greater than voltage
appears at the gate terminal, the gate to source voltage has a negative value
which is desired for JFET operation.

4. • Let us consider the following circuit.

5. GRAPHICAL ANALYSIS OF JFET WITH
VOLTAGE-DIVIDER BIAS
•The technique which we used for self bias can be used for voltage divider bias to find the Q point of
circuitry on the transfer characteristic curve in the graphical form.
•In junction field-effect transistor voltage divider biasing when current ID is zero then value of VGS is
nonzero which was zero in case of self bias, since voltage divider generates a voltage at the gate terminal
being independent on a current of a drain.
•The load line for voltage divider can be found as.
•If the drain current is zero then.
VS = IDRS = (0)RS = 0V
VGS = VG – VS = VG – 0 V = VG
•So one point on the line at current ID is zero and VGS=VG.
•If VGS =0
ID=(VG – VGS)/RS – VG/Rs
•The 2nd point on the line will be at ID =VG/RS and VGS =0.
•The load line is shown in the below figure.
•The point where the load line is crosses the transfer characteristic curve is called Q point.

6. JFET Q-POINT STABILITY
 There is problems is that the transfer characteristic curve is different for a different type of JFET.
 For instance, if we substitute the 2N5459 junction field-effect transistor with the other 2N5459
transistor the transfer characteristic curve changes also. It is shown in figure denoted as ‘a’.
 For this condition, the max value of IDSS will be 16 milliamperes and the minimum value of IDSS
will be 4milliampere.
 Similarly, the maximum VGS(off) -8volts is and the minimum VGS(off) is -2 volts.
 It means that you have a series of 2N5459 and randomly chose a device its value will be within this
above-given range.
 If we make a self dc load line constructed in figure denoted as ‘b’ through the similar circuitry with
the use of 2N5459 will have Q point on the line from Q1 to minimum bias point to Q2 which is a
maximum point.
 So the ID will have a value among point ID1 and ID2 as displayed through the shaded region.
 It means that dc voltage at the drain will have values according to current ID.
 With that, the value of gate to a source will be among the VGS1 and VGS2.

7.  The below figure explains the Q point stability for
self-biased junction field effect transistor and
voltage divider bias JFET.
 For voltage divider bias the dependency of current
ID on the value range of Q point decreases since
the slop of load line is less for self-bias.
 Though VGS changes more for both self-bias and
voltage divider bias ID has more stability for
voltage divider bias circuit.

8. YOUR TURN
In this way, the applied drain voltage is utilized to get the gate terminal voltage. If this source voltage drop is greater than
voltage appears at the gate terminal, the gate to source voltage has a negative value which is desired for JFET operation.
The purpose of JFET biasing is to select the proper dc gate-to-source voltage to establish a desired value of drain current
and thus, a proper Q-point.
 Why we use voltage divider bias ?