The document proposes a modified semi-orthogonal space-time block code (SSTBC) encoder for noise-free MIMO communication in OFDM systems. It summarizes previous research on space-time coding techniques and identifies limitations. The proposed SSTBC encoder is evaluated and found to have a lower bit error rate than previous designs, indicating it provides more effective error correction and spectral efficiency for optimal MIMO communication. Key aspects of the proposed encoder include a new quasi-orthogonal fading matrix and use of discrete wavelet transform instead of fast Fourier transform.
Hamming net based Low Complexity Successive Cancellation Polar DecoderRSIS International
This paper aims to implement hybrid based Polar
encoder using the knowledge of mutual information and channel
capacity. Further a Hamming weight successive cancellation
decoder is simulated with QPSK modulation technique in
presence of additive white gaussian noise. The experimentation
performed with the effect of channel polarization has shown that
for 256- bit data stream, 30% channels has zero bit and 49%
channels are with a one bit capacity. The decoding complexity is
reduced to almost half as compared to conventional successive
cancellation decoding algorithm. However, the required SNR of
7 dB is achieved at the targeted BER of 10 -4. The penalty paid is
in terms of training time required at the decoding end.
Parallel-prefix adders offer a highly efficient solution to the binary addition problem and are
well-suited for VLSI implementations. In this paper, a novel framework is introduced, which allows
the design of parallel-prefix Ling adders. The proposed approach saves one-logic level of
implementation compared to the parallel-prefix structures proposed for the traditional definition of
carry look ahead equations and reduces the fan out requirements of the design. Experimental results
reveal that the proposed adders achieve delay reductions of up to 14 percent when compared to the
fastest parallel-prefix architectures presented for the traditional definition of carry equations
Tail-biting convolutional codes (TBCC) have been extensively applied in communication systems. This method is implemented by replacing the fixedtail with tail-biting data. This concept is needed to achieve an effective decoding computation. Unfortunately, it makes the decoding computation becomes more complex. Hence, several algorithms have been developed to overcome this issue in which most of them are implemented iteratively with uncertain number of iteration. In this paper, we propose a VLSI architecture to implement our proposed reversed-trellis TBCC (RT-TBCC) algorithm. This algorithm is designed by modifying direct-terminating maximumlikelihood (ML) decoding process to achieve better correction rate. The purpose is to offer an alternative solution for tail-biting convolutional code decoding process with less number of computation compared to the existing solution. The proposed architecture has been evaluated for LTE standard and it significantly reduces the computational time and resources compared to the existing direct-terminating ML decoder. For evaluations on functionality and Bit Error Rate (BER) analysis, several simulations, System-on-Chip (SoC) implementation and synthesis in FPGA are performed.
Efficient implementation of bit parallel finite field multiplierseSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Hamming net based Low Complexity Successive Cancellation Polar DecoderRSIS International
This paper aims to implement hybrid based Polar
encoder using the knowledge of mutual information and channel
capacity. Further a Hamming weight successive cancellation
decoder is simulated with QPSK modulation technique in
presence of additive white gaussian noise. The experimentation
performed with the effect of channel polarization has shown that
for 256- bit data stream, 30% channels has zero bit and 49%
channels are with a one bit capacity. The decoding complexity is
reduced to almost half as compared to conventional successive
cancellation decoding algorithm. However, the required SNR of
7 dB is achieved at the targeted BER of 10 -4. The penalty paid is
in terms of training time required at the decoding end.
Parallel-prefix adders offer a highly efficient solution to the binary addition problem and are
well-suited for VLSI implementations. In this paper, a novel framework is introduced, which allows
the design of parallel-prefix Ling adders. The proposed approach saves one-logic level of
implementation compared to the parallel-prefix structures proposed for the traditional definition of
carry look ahead equations and reduces the fan out requirements of the design. Experimental results
reveal that the proposed adders achieve delay reductions of up to 14 percent when compared to the
fastest parallel-prefix architectures presented for the traditional definition of carry equations
Tail-biting convolutional codes (TBCC) have been extensively applied in communication systems. This method is implemented by replacing the fixedtail with tail-biting data. This concept is needed to achieve an effective decoding computation. Unfortunately, it makes the decoding computation becomes more complex. Hence, several algorithms have been developed to overcome this issue in which most of them are implemented iteratively with uncertain number of iteration. In this paper, we propose a VLSI architecture to implement our proposed reversed-trellis TBCC (RT-TBCC) algorithm. This algorithm is designed by modifying direct-terminating maximumlikelihood (ML) decoding process to achieve better correction rate. The purpose is to offer an alternative solution for tail-biting convolutional code decoding process with less number of computation compared to the existing solution. The proposed architecture has been evaluated for LTE standard and it significantly reduces the computational time and resources compared to the existing direct-terminating ML decoder. For evaluations on functionality and Bit Error Rate (BER) analysis, several simulations, System-on-Chip (SoC) implementation and synthesis in FPGA are performed.
Efficient implementation of bit parallel finite field multiplierseSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Efficient implementation of bit parallel finite eSAT Journals
Abstract Arithmetic in Finite/Galois field is a major aspect for many applications such as error correcting code and cryptography. Addition and multiplication are the two basic operations in the finite field GF (2m).The finite field multiplication is the most resource and time consuming operation. In this paper the complexity (space) analysis and efficient FPGA implementation of bit parallel Karatsuba Multiplier over GF (2m) is presented. This is especially interesting for high performance systems because of its carry free property. To reduce the complexity of Classical Multiplier, multiplier with less complexity over GF (2m) based on Karatsuba Multiplier is used. The LUT complexity is evaluated on FPGA by using Xilinx ISE 8.1i.Furthermore,the experimental results on FPGAs for bit parallel Karatsuba Multiplier and Classical Multiplier were shown and the comparison table is provided. To the best of our knowledge, the bit parallel karatsuba multiplier consumes least resources among the known FPGA implementation. Keywords: Classical Multiplier, Cryptograph, FPGA, Galois field, Karatsuba Multiplier
Compressive Sensing in Speech from LPC using Gradient Projection for Sparse R...IJERA Editor
This paper presents compressive sensing technique used for speech reconstruction using linear predictive coding because the
speech is more sparse in LPC. DCT of a speech is taken and the DCT points of sparse speech are thrown away arbitrarily.
This is achieved by making some point in DCT domain to be zero by multiplying with mask functions. From the incomplete
points in DCT domain, the original speech is reconstructed using compressive sensing and the tool used is Gradient
Projection for Sparse Reconstruction. The performance of the result is compared with direct IDCT subjectively. The
experiment is done and it is observed that the performance is better for compressive sensing than the DCT.
Reduced Test Pattern Generation of Multiple SIC Vectors with Input and Output...IJERA Editor
In recent years, the design for low power has become one of the greatest challenges in high-performance very
large scale integration (VLSI) design. Most of the methods focus on the power consumption during normal mode
operation, while test mode operation has not normally been a predominant concern. However, it has been found
that the power consumed during test mode operation is often much higher than during normal mode operation
[1]. This is because most of the consumed power results from the switching activity in the nodes of the circuit
under test (CUT), which is much higher during test mode than during normal mode operation [1]–[3]. In the
proposed pattern, each generated vector applied to each scan chain is an SIC vector, which can minimize the
input transition and reduce test power. In VLSI testing, power reduction is achieved by increasing the correlation
between consecutive test patterns.
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
A new efficient way based on special stabilizer multiplier permutations to at...IJECEIAES
BCH codes represent an important class of cyclic error-correcting codes; their minimum distances are known only for some cases and remains an open NP-Hard problem in coding theory especially for large lengths. This paper presents an efficient scheme ZSSMP (Zimmermann Special Stabilizer Multiplier Permutation) to find the true value of the minimum distance for many large BCH codes. The proposed method consists in searching a codeword having the minimum weight by Zimmermann algorithm in the sub codes fixed by special stabilizer multiplier permutations. These few sub codes had very small dimensions compared to the dimension of the considered code itself and therefore the search of a codeword of global minimum weight is simplified in terms of run time complexity. ZSSMP is validated on all BCH codes of length 255 for which it gives the exact value of the minimum distance. For BCH codes of length 511, the proposed technique passes considerably the famous known powerful scheme of Canteaut and Chabaud used to attack the public-key cryptosystems based on codes. ZSSMP is very rapid and allows catching the smallest weight codewords in few seconds. By exploiting the efficiency and the quickness of ZSSMP, the true minimum distances and consequently the error correcting capability of all the set of 165 BCH codes of length up to 1023 are determined except the two cases of the BCH(511,148) and BCH(511,259) codes. The comparison of ZSSMP with other powerful methods proves its quality for attacking the hardness of minimum weight search problem at least for the codes studied in this paper.
Area efficient parallel LFSR for cyclic redundancy check IJECEIAES
Cyclic Redundancy Check (CRC), code for error detection finds many applications in the field of digital communication, data storage, control system and data compression. CRC encoding operation is carried out by using a Linear Feedback Shift Register (LFSR). Serial implementation of CRC requires more clock cycles which is equal to data message length plus generator polynomial degree but in parallel implementation of CRC one clock cycle is required if a whole data message is applied at a time. In previous work related to parallel LFSR, hardware complexity of the architecture reduced using a technique named state space transformation. This paper presents detailed explaination of search algorithm implementation and technique to find number of XOR gates required for different CRC algorithms. This paper presents a searching algorithm and new technique to find the number of XOR gates required for different CRC algorithms. The comparison between proposed and previous architectures shows that the number of XOR gates are reduced for CRC algorithms which improve the hardware efficiency. Searching algorithm and all the matrix computations have been performed using MATLAB simulations.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Implementation and Performance Analysis of Kaiser and Hamming Window Techniqu...IJERA Editor
Considering the importance of real time filtering, a comparison was done between two prominent window
techniques known for digital filtering. A 16 tap digital band pass FIR filter is designed for each design technique
(Kaiser and Hamming) and implemented over FPGA. The Simulink model of the filter confirms the correctness
and other properties of the digital filter. Further a hardware descriptive code (VHDL) is generated for the
designed filter which then will be loaded on to the FPGA. The VHDL code is speed optimized. The VHDL code
is simulated and synthesized in Xilinx ISE. Further the performance analysis is done on FPGA to determine the
applicability of the filter.
Efficient Design of Reversible Multiplexers with Low Quantum CostIJERA Editor
Multiplexing is the generic term used to designate the operation of sending one or more analogue or digital
signals over a common transmission line at dissimilar times or speeds and as such, the scheme we use to do just
that is called a Multiplexer. In digital electronics, multiplexers are similarly known as data selectors as they can
“select” each input line, are made from individual Analogue Switches encased in a single IC package as
conflicting to the “mechanical” type selectors such as standard conservative switches and relays. In today era,
reversibility has become essential part of digital world to make digital circuits more efficient. In this paper, we
have proposed a new method to reduce quantum cost and power for various multiplexers. The results are
simulated in Xilinx by using VHDL language.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Efficient implementation of bit parallel finite eSAT Journals
Abstract Arithmetic in Finite/Galois field is a major aspect for many applications such as error correcting code and cryptography. Addition and multiplication are the two basic operations in the finite field GF (2m).The finite field multiplication is the most resource and time consuming operation. In this paper the complexity (space) analysis and efficient FPGA implementation of bit parallel Karatsuba Multiplier over GF (2m) is presented. This is especially interesting for high performance systems because of its carry free property. To reduce the complexity of Classical Multiplier, multiplier with less complexity over GF (2m) based on Karatsuba Multiplier is used. The LUT complexity is evaluated on FPGA by using Xilinx ISE 8.1i.Furthermore,the experimental results on FPGAs for bit parallel Karatsuba Multiplier and Classical Multiplier were shown and the comparison table is provided. To the best of our knowledge, the bit parallel karatsuba multiplier consumes least resources among the known FPGA implementation. Keywords: Classical Multiplier, Cryptograph, FPGA, Galois field, Karatsuba Multiplier
Compressive Sensing in Speech from LPC using Gradient Projection for Sparse R...IJERA Editor
This paper presents compressive sensing technique used for speech reconstruction using linear predictive coding because the
speech is more sparse in LPC. DCT of a speech is taken and the DCT points of sparse speech are thrown away arbitrarily.
This is achieved by making some point in DCT domain to be zero by multiplying with mask functions. From the incomplete
points in DCT domain, the original speech is reconstructed using compressive sensing and the tool used is Gradient
Projection for Sparse Reconstruction. The performance of the result is compared with direct IDCT subjectively. The
experiment is done and it is observed that the performance is better for compressive sensing than the DCT.
Reduced Test Pattern Generation of Multiple SIC Vectors with Input and Output...IJERA Editor
In recent years, the design for low power has become one of the greatest challenges in high-performance very
large scale integration (VLSI) design. Most of the methods focus on the power consumption during normal mode
operation, while test mode operation has not normally been a predominant concern. However, it has been found
that the power consumed during test mode operation is often much higher than during normal mode operation
[1]. This is because most of the consumed power results from the switching activity in the nodes of the circuit
under test (CUT), which is much higher during test mode than during normal mode operation [1]–[3]. In the
proposed pattern, each generated vector applied to each scan chain is an SIC vector, which can minimize the
input transition and reduce test power. In VLSI testing, power reduction is achieved by increasing the correlation
between consecutive test patterns.
The International Journal of Engineering & Science is aimed at providing a platform for researchers, engineers, scientists, or educators to publish their original research results, to exchange new ideas, to disseminate information in innovative designs, engineering experiences and technological skills. It is also the Journal's objective to promote engineering and technology education. All papers submitted to the Journal will be blind peer-reviewed. Only original articles will be published.
A new efficient way based on special stabilizer multiplier permutations to at...IJECEIAES
BCH codes represent an important class of cyclic error-correcting codes; their minimum distances are known only for some cases and remains an open NP-Hard problem in coding theory especially for large lengths. This paper presents an efficient scheme ZSSMP (Zimmermann Special Stabilizer Multiplier Permutation) to find the true value of the minimum distance for many large BCH codes. The proposed method consists in searching a codeword having the minimum weight by Zimmermann algorithm in the sub codes fixed by special stabilizer multiplier permutations. These few sub codes had very small dimensions compared to the dimension of the considered code itself and therefore the search of a codeword of global minimum weight is simplified in terms of run time complexity. ZSSMP is validated on all BCH codes of length 255 for which it gives the exact value of the minimum distance. For BCH codes of length 511, the proposed technique passes considerably the famous known powerful scheme of Canteaut and Chabaud used to attack the public-key cryptosystems based on codes. ZSSMP is very rapid and allows catching the smallest weight codewords in few seconds. By exploiting the efficiency and the quickness of ZSSMP, the true minimum distances and consequently the error correcting capability of all the set of 165 BCH codes of length up to 1023 are determined except the two cases of the BCH(511,148) and BCH(511,259) codes. The comparison of ZSSMP with other powerful methods proves its quality for attacking the hardness of minimum weight search problem at least for the codes studied in this paper.
Area efficient parallel LFSR for cyclic redundancy check IJECEIAES
Cyclic Redundancy Check (CRC), code for error detection finds many applications in the field of digital communication, data storage, control system and data compression. CRC encoding operation is carried out by using a Linear Feedback Shift Register (LFSR). Serial implementation of CRC requires more clock cycles which is equal to data message length plus generator polynomial degree but in parallel implementation of CRC one clock cycle is required if a whole data message is applied at a time. In previous work related to parallel LFSR, hardware complexity of the architecture reduced using a technique named state space transformation. This paper presents detailed explaination of search algorithm implementation and technique to find number of XOR gates required for different CRC algorithms. This paper presents a searching algorithm and new technique to find the number of XOR gates required for different CRC algorithms. The comparison between proposed and previous architectures shows that the number of XOR gates are reduced for CRC algorithms which improve the hardware efficiency. Searching algorithm and all the matrix computations have been performed using MATLAB simulations.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Implementation and Performance Analysis of Kaiser and Hamming Window Techniqu...IJERA Editor
Considering the importance of real time filtering, a comparison was done between two prominent window
techniques known for digital filtering. A 16 tap digital band pass FIR filter is designed for each design technique
(Kaiser and Hamming) and implemented over FPGA. The Simulink model of the filter confirms the correctness
and other properties of the digital filter. Further a hardware descriptive code (VHDL) is generated for the
designed filter which then will be loaded on to the FPGA. The VHDL code is speed optimized. The VHDL code
is simulated and synthesized in Xilinx ISE. Further the performance analysis is done on FPGA to determine the
applicability of the filter.
Efficient Design of Reversible Multiplexers with Low Quantum CostIJERA Editor
Multiplexing is the generic term used to designate the operation of sending one or more analogue or digital
signals over a common transmission line at dissimilar times or speeds and as such, the scheme we use to do just
that is called a Multiplexer. In digital electronics, multiplexers are similarly known as data selectors as they can
“select” each input line, are made from individual Analogue Switches encased in a single IC package as
conflicting to the “mechanical” type selectors such as standard conservative switches and relays. In today era,
reversibility has become essential part of digital world to make digital circuits more efficient. In this paper, we
have proposed a new method to reduce quantum cost and power for various multiplexers. The results are
simulated in Xilinx by using VHDL language.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Investigating the performance of various channel estimation techniques for mi...ijmnct
This paper simulates and investigates the performance of four widely-used channel estimation techniques for MIMO-OFDM wireless communication systems; namely, super imposed pilot (SIP), comb-type, spacetime block coding (STBC), and space-frequency block coding (SFBC) techniques. The performance is
evaluated through a number of MATLab simulations, where the bit-error rate (BER) and the mean square
error (MSE) are estimated and compared for different levels of signal-to-noise ratio (SNR). The simulation results demonstrate that the comb-type channel estimation and the SIP techniques overwhelmed the performance of the STFC and STBC techniques in terms of both bit-error rate (BER) and mean square error (MSE).
INVESTIGATING THE PERFORMANCE OF VARIOUS CHANNEL ESTIMATION TECHNIQUES FOR MI...ijmnct
This paper simulates and investigates the performance of four widely-used channel estimation techniques for MIMO-OFDM wireless communication systems; namely, super imposed pilot (SIP), comb-type, spacetime block coding (STBC), and space-frequency block coding (SFBC) techniques. The performance is evaluated through a number of MATLab simulations, where the bit-error rate (BER) and the mean square error (MSE) are estimated and compared for different levels of signal-to-noise ratio (SNR). The simulation results demonstrate that the comb-type channel estimation and the SIP techniques overwhelmed the performance of the STFC and STBC techniques in terms of both bit-error rate (BER) and mean square error (MSE).
A Novel Technique for Multi User Multiple Access Spatial Modulation Using Ada...ijtsrd
The need for high peak data rates with the corresponding need for signi cantly increased spectral e ciencies, and the support for service speci c quality of service QoS requirements are the key elements that drive the research in the area of wireless communication access technologies Since space constellations and signal constellations are orthogonal, the well known digital signal modulation schemes can be used on top. The spatial multiplexing gain comes from the simultaneous transmission of spatially encoded bits. Analytical and numerical performance of SM in di erent channel conditions, including practical channel considerations, are studied and compared to existing MIMO techniques in this thesis. Results show that SM achieve low BER bit error ratio with a tremendous reduction in receiver complexity without sacri cing spectral e ciency. Anshul Sengar | Gaurav Morghare "A Novel Technique for Multi User Multiple Access Spatial Modulation Using Adaptive Coding and Modulation" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-6 | Issue-1 , December 2021, URL: https://www.ijtsrd.com/papers/ijtsrd47856.pdf Paper URL: https://www.ijtsrd.com/engineering/electronics-and-communication-engineering/47856/a-novel-technique-for-multi-user-multiple-access-spatial-modulation-using-adaptive-coding-and-modulation/anshul-sengar
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
TECHNIQUES IN PERFORMANCE IMPROVEMENT OF MOBILE WIRELESS COMMUNICATION SYSTEM...Onyebuchi nosiri
Mobile wireless communication providers are expected by their numerous subscribers to provide network that can allow higher data rates, and good voice quality. However, this may be restricted due to some technical problems such as limited availability of radio frequency spectrum, bandwidth, channel capacity, geographical areas and transmission problems caused by various factors like fading and multipath distortion. All these lead to overall system performance degradation. This has led to various studies on how improvement on the performance of wireless communication can be realized using different techniques. This paper is a review of some scholarly works on this subject. To achieve this some recent scholarly articles were accessed online and their findings were highlighted. It was observed that all the articles reviewed had results drawn only from theoretical analysis. Based on this, one of the recommendations is that theoretical analysis should be supported with data obtained from carrying out RF measurements in the field where possible.
An Integrated Approach of ACM and CDMA in a Novel Multi User Spatial Modulati...ijtsrd
The research focus in wireless communication access technologies is driven by the demand for high peak data rates and significantly improved spectral efficiencies, as well as the support for specific quality of service QoS requirements. By leveraging the orthogonality of space constellations and signal constellations, well established digital signal modulation schemes can be employed. The spatial multiplexing gain is achieved through the concurrent transmission of spatially encoded bits. This thesis investigates and compares the analytical and numerical performance of Spatial Modulation SM under various channel conditions, taking into account practical channel considerations, in comparison to existing MIMO techniques. The results demonstrate that SM achieves a low bit error ratio BER while substantially reducing receiver complexity, all while maintaining spectral efficiency. Kumari Kanchana | Dr. Prabhat Sharma "An Integrated Approach of ACM and CDMA in a Novel Multi-User Spatial Modulation Scheme" Published in International Journal of Trend in Scientific Research and Development (ijtsrd), ISSN: 2456-6470, Volume-7 | Issue-4, August 2023, URL: https://www.ijtsrd.com/papers/ijtsrd59660.pdf Paper Url:https://www.ijtsrd.com/engineering/electronics-and-communication-engineering/59660/an-integrated-approach-of-acm-and-cdma-in-a-novel-multiuser-spatial-modulation-scheme/kumari-kanchana
Performance Analysis of Convolution Coded WLAN Physical Layer under Different...CSCJournals
WLAN plays an important role as a complement to the existing or planned cellular networks which can offer high speed voice, video and data service up to the customer end. The aim of this paper is to analysis the performance of coded WLAN system for different digital modulation schemes (BPSK, 16-PSK, QPSK, 4-QAM and 16-QAM) under AWGN channel. The performance of convolution encoder WLAN system is in terms of graph between BER and SNR. We also verify the system performance with different code rates (1/2, 1/3, 2/3 1nd 3/4) and different constraint length.
Performance Analysis of OSTBC MIMO Using Precoder with ZF & MMSE EqualizerIJERA Editor
In this paper, a bit error rate analysis is presented for multiple-input–multiple-output (MIMO) system with finite-bit feedback is considered in PSK modulation technique, where a transmit signal consists of a rotational precoder followed by an orthogonal space–time block code (OSTBC) which achieve full diversity when a linear receiver, such as, zeroforcing (ZF) or minimum mean square (MMSE), is used. By choosing different parameters, codes with different symbol rates and orthogonally can be obtained .In this paper, we compare the performance of a family of space-time codes. Simulations show how the precoders obtained by our proposed criterion and method perform better bit error rate reduction compared to the existing ones.
In recent years, cooperative communication is a hot topic of research and it is a powerful physical layer
technique to combat fading in wireless relaying scenario. Concerning with the physical layer issues, in this
paper it is focussed on with providing a better space time block coding (STBC) scheme and incorporating it
in the cooperative relaying nodes to upgrade the system performance. Recently, the golden codes have
proven to exhibit a superior performance in a wireless MIMO (Multiple Input Multiple Output) scenario
than any other code. However, a serious limitation associated with it is its increased decoding complexity.
This paper attempts to resolve this challenge through suitable modification of golden code such that a less
complex sphere decoder could be used without much compromising the error rates. The decoder complexity
is analyzed through simulation and it proves to exhibit less complexity compared to the conventional
(Maximum likelihood) ML decoder. The single relay cooperative STBC consisting of source, relay and
destination are considered. The cooperative protocol strategy considered in the relay node is Decode and
forward (DF) protocol. The proposed modified golden code with less complex sphere decoder is
implemented in the nodes of the cooperative relaying system to achieve better performance in the system.
The simulation results have validated the effectiveness of the proposed scheme by offering better BER
performance, minimum outage probability and increased spectral efficiency compared to the non
cooperative transmission method.
Capsulization of Existing Space Time TechniquesIJEEE
In this paper, we explore the fundamental
concepts behind the emerging field of space-time coding for
wireless communication system. A space–time code (STC)
is a method which employed to increase the reliability of
data transmission in the wireless communication
systems using multiple transmit antennas.
CL-SA-OFDM: cross-layer and smart antenna based OFDM system performance enha...IJECEIAES
The growing usage of wireless services is lacking in providing high-speed data communication in recent times. Hence, many of the modulation techniques are evolved to attain these communication needs. The recent researches have widely considered OFDM technology as the prominent modulation mechanism to fulfill the futuristic needs of wireless communication. The OFDM can bring effective usage of resources, bandwidth, and system performance enhancement in collaboration with the smart antenna and resource allocation mechanism (adaptive). However, the usage of adaptive beamforming with the OFDM leads to complication in the design of medium access layer and which causes a problem in adaptive resource allocation mechanism (ARAM). Hence, the proposed manuscript intends to design an OFDM system by considering different switched beam smart antenna (SBSA) along with the cross-layer adaptive resource allocation (CLARA) and hybrid adaptive array (HAA). In this, various smart antenna mechanism are considered to analyze the quality of service (QoS) and complexity reduction in the OFDM system. In this paper, various SA schemes are used as per the quality of service (QoS) requirement of the different users. The performance analysis is conducted by considering data traffic reduction, bit-rate reduction, and average delay.
PSO-CCO_MIMO-SA: A particle swarm optimization based channel capacity optimza...IJECEIAES
With the radio channels physical limits, achieving higher data rate in the multi-channel systems is been a biggest concern. Hence, various spatial domain techniques have been introduced by incorporating array of antenna elements (i.e., smart antenna) in recent past for the channel limit expansion in mobile communication antennas. These smart antennas help to yield the improved array gain or bearm forming gain and hence by power efficiency enhanmaent in the channel and antenna range expansion. The use of smart antenna leads to spatial diversity and minimizes the fading effect and improves link reliability. However, in the process of antenna design, the proper channel modelling is is biggest concern which affect the wireless system performance. The recent works of MIMO design systems have discussed the issues in number of antenna selection which suggests that optimization of MIMO channel capacity is required. Hence, a Particle Swarm Optimization based channel capacity optimzation for MIMO system incorporated with smart antenna is introduced in this paper. From the outcomes it is been found that the proposed PSO based MIMO system achieves better convergenece speed which results in better channel capacity.
Hardware Architecture of Complex K-best MIMO DecoderCSCJournals
This paper presents a hardware architecture of complex K-best Multiple Input Multiple Output (MIMO) decoder reducing the complexity of Maximum Likelihood (ML) detector. We develop a novel low-power VLSI design of complex K-best decoder for MIMO and 64 QAM modulation scheme. Use of Schnorr-Euchner (SE) enumeration and a new parameter, Rlimit in the design reduce the complexity of calculating K-best nodes to a certain level with increased performance. The total word length of only 16 bits has been adopted for the hardware design limiting the bit error rate (BER) degradation to 0.3 dB with list size, K and Rlimit equal to 4. The proposed VLSI architecture is modeled in Verilog HDL using Xilinx and synthesized using Synopsys Design Vision in 45 nm CMOS technology. According to the synthesize result, it achieves 1090.8 Mbps throughput with power consumption of 782 mW and latency of 0.33 us. The maximum frequency the design proposed is 181.8 MHz.
A New Bit Split and Interleaved Channel Coding for MIMO DecoderIJARBEST JOURNAL
Authors:-C. Amar Singh Feroz1, S. Karthikeyan2, K. Mala3
Abstract– In wireless communications, the use of multiple antennas at both the
transmitter and receiver is a key technology to enable high data transmission without
additional bandwidth or transmit power. MIMO schemes are widely used in many
wireless standards, allowing higher throughput using spatial multiplexing techniques.
Bit split mapping based on JDD is designed. Here ETI coding is used for encoding and
Viterbi is used for decoding. Experimental results for 16-QAM and 64 QAM with the
code rate of ½ and 1/3 codes are shown to verify the proposed approach and to elucidate
the design tradeoffs in terms the BER performance. This bit split mapping based JDD
algorithm can greatly improve BER performance with different system settings.
Similar to IRJET-A Design Of Modified SSTBC Encoder to Noise Free Mimo Communication in OFDM (20)
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Hybrid optimization of pumped hydro system and solar- Engr. Abdul-Azeez.pdffxintegritypublishin
Advancements in technology unveil a myriad of electrical and electronic breakthroughs geared towards efficiently harnessing limited resources to meet human energy demands. The optimization of hybrid solar PV panels and pumped hydro energy supply systems plays a pivotal role in utilizing natural resources effectively. This initiative not only benefits humanity but also fosters environmental sustainability. The study investigated the design optimization of these hybrid systems, focusing on understanding solar radiation patterns, identifying geographical influences on solar radiation, formulating a mathematical model for system optimization, and determining the optimal configuration of PV panels and pumped hydro storage. Through a comparative analysis approach and eight weeks of data collection, the study addressed key research questions related to solar radiation patterns and optimal system design. The findings highlighted regions with heightened solar radiation levels, showcasing substantial potential for power generation and emphasizing the system's efficiency. Optimizing system design significantly boosted power generation, promoted renewable energy utilization, and enhanced energy storage capacity. The study underscored the benefits of optimizing hybrid solar PV panels and pumped hydro energy supply systems for sustainable energy usage. Optimizing the design of solar PV panels and pumped hydro energy supply systems as examined across diverse climatic conditions in a developing country, not only enhances power generation but also improves the integration of renewable energy sources and boosts energy storage capacities, particularly beneficial for less economically prosperous regions. Additionally, the study provides valuable insights for advancing energy research in economically viable areas. Recommendations included conducting site-specific assessments, utilizing advanced modeling tools, implementing regular maintenance protocols, and enhancing communication among system components.
CFD Simulation of By-pass Flow in a HRSG module by R&R Consult.pptxR&R Consult
CFD analysis is incredibly effective at solving mysteries and improving the performance of complex systems!
Here's a great example: At a large natural gas-fired power plant, where they use waste heat to generate steam and energy, they were puzzled that their boiler wasn't producing as much steam as expected.
R&R and Tetra Engineering Group Inc. were asked to solve the issue with reduced steam production.
An inspection had shown that a significant amount of hot flue gas was bypassing the boiler tubes, where the heat was supposed to be transferred.
R&R Consult conducted a CFD analysis, which revealed that 6.3% of the flue gas was bypassing the boiler tubes without transferring heat. The analysis also showed that the flue gas was instead being directed along the sides of the boiler and between the modules that were supposed to capture the heat. This was the cause of the reduced performance.
Based on our results, Tetra Engineering installed covering plates to reduce the bypass flow. This improved the boiler's performance and increased electricity production.
It is always satisfying when we can help solve complex challenges like this. Do your systems also need a check-up or optimization? Give us a call!
Work done in cooperation with James Malloy and David Moelling from Tetra Engineering.
More examples of our work https://www.r-r-consult.dk/en/cases-en/
Hierarchical Digital Twin of a Naval Power SystemKerry Sado
A hierarchical digital twin of a Naval DC power system has been developed and experimentally verified. Similar to other state-of-the-art digital twins, this technology creates a digital replica of the physical system executed in real-time or faster, which can modify hardware controls. However, its advantage stems from distributing computational efforts by utilizing a hierarchical structure composed of lower-level digital twin blocks and a higher-level system digital twin. Each digital twin block is associated with a physical subsystem of the hardware and communicates with a singular system digital twin, which creates a system-level response. By extracting information from each level of the hierarchy, power system controls of the hardware were reconfigured autonomously. This hierarchical digital twin development offers several advantages over other digital twins, particularly in the field of naval power systems. The hierarchical structure allows for greater computational efficiency and scalability while the ability to autonomously reconfigure hardware controls offers increased flexibility and responsiveness. The hierarchical decomposition and models utilized were well aligned with the physical twin, as indicated by the maximum deviations between the developed digital twin hierarchy and the hardware.
Welcome to WIPAC Monthly the magazine brought to you by the LinkedIn Group Water Industry Process Automation & Control.
In this month's edition, along with this month's industry news to celebrate the 13 years since the group was created we have articles including
A case study of the used of Advanced Process Control at the Wastewater Treatment works at Lleida in Spain
A look back on an article on smart wastewater networks in order to see how the industry has measured up in the interim around the adoption of Digital Transformation in the Water Industry.
Cosmetic shop management system project report.pdfKamal Acharya
Buying new cosmetic products is difficult. It can even be scary for those who have sensitive skin and are prone to skin trouble. The information needed to alleviate this problem is on the back of each product, but it's thought to interpret those ingredient lists unless you have a background in chemistry.
Instead of buying and hoping for the best, we can use data science to help us predict which products may be good fits for us. It includes various function programs to do the above mentioned tasks.
Data file handling has been effectively used in the program.
The automated cosmetic shop management system should deal with the automation of general workflow and administration process of the shop. The main processes of the system focus on customer's request where the system is able to search the most appropriate products and deliver it to the customers. It should help the employees to quickly identify the list of cosmetic product that have reached the minimum quantity and also keep a track of expired date for each cosmetic product. It should help the employees to find the rack number in which the product is placed.It is also Faster and more efficient way.