This document summarizes an article that presents an efficient implementation of a bit parallel Karatsuba finite field multiplier on FPGA. It begins by introducing finite field arithmetic and multiplication, which is the most resource intensive operation. It then discusses different multiplier designs, including the classical multiplier and Karatsuba multiplier. The Karatsuba multiplier has lower complexity than the classical multiplier by reducing the number of gates required. Experimental results on FPGAs show that the bit parallel Karatsuba multiplier consumes the fewest resources among known FPGA implementations. In summary, the document presents an efficient Karatsuba finite field multiplier design with lower complexity than alternative designs.
In the VLSI physical design, Floorplanning is the very crucial step as it optimizes the chip. The goal of
floorplanning is to find a floorplan such that no module overlaps with other, optimize the interconnection between
the modules, optimize the area of the floorplan and minimize the dead space. In this Paper, Simulated Annealing (SA)
algorithm has been employed to shrink dead space to optimize area and interconnect of VLSI floorplanning problem.
Sequence pair representation is employed to perturb the solution. The outcomes received after the application of SA
on different benchmark files are compared with the outcomes of different algorithms on same benchmark files and
the comparison suggests that the SA gives the better result. SA is effective and promising in VLSI floorplan design.
Matlab simulation results show that our approach can give better results and satisfy the fixed-outline and nonoverlapping
constraints while optimizing circuit performance.
POWER GATING STRUCTURE FOR REVERSIBLE PROGRAMMABLE LOGIC ARRAYecij
Throughout the world, the numbers of researchers or hardware designer struggle for the reducing of
power dissipation in low power VLSI systems. This paper presented an idea of using the power gating
structure for reducing the sub threshold leakage in the reversible system. This concept presented in the
paper is entirely new and presented in the literature of reversible logics. By using the reversible logics for
the digital systems, the energy can be saved up to the gate level implementation. But at the physical level
designing of the reversible logics by the modern CMOS technology the heat or energy is dissipated due the
sub-threshold leakage at the time of inactivity or standby mode. The Reversible Programming logic array
(RPLA) is one of the important parts of the low power industrial applications and in this paper the physical
design of the RPLA is presented by using the sleep transistor and the results is shown with the help of
TINA- PRO software. The results for the proposed design is also compare with the CMOS design and
shown that of 40.8% of energy saving. The Transient response is also produces in the paper for the
switching activity and showing that the proposed design is much better that the modern CMOS design of
the RPLA.
Fpga based efficient multiplier for image processing applications using recur...VLSICS Design
The Digital Image processing applications like medical imaging, satellite imaging, Biometric trait images
etc., rely on multipliers to improve the quality of image. However, existing multiplication techniques
introduce errors in the output with consumption of more time, hence error free high speed multipliers has
to be designed. In this paper we propose FPGA based Recursive Error Free Mitchell Log Multiplier
(REFMLM) for image Filters. The 2x2 error free Mitchell log multiplier is designed with zero error by
introducing error correction term is used in higher order Karastuba-Ofman Multiplier (KOM)
Architectures. The higher order KOM multipliers is decomposed into number of lower order multipliers
using radix 2 till basic multiplier block of order 2x2 which is designed by error free Mitchell log multiplier.
The 8x8 REFMLM is tested for Gaussian filter to remove noise in fingerprint image. The Multiplier is
synthesized using Spartan 3 FPGA family device XC3S1500-5fg320. It is observed that the performance
parameters such as area utilization, speed, error and PSNR are better in the case of proposed architecture
compared to existing architectures.
In the VLSI physical design, Floorplanning is the very crucial step as it optimizes the chip. The goal of
floorplanning is to find a floorplan such that no module overlaps with other, optimize the interconnection between
the modules, optimize the area of the floorplan and minimize the dead space. In this Paper, Simulated Annealing (SA)
algorithm has been employed to shrink dead space to optimize area and interconnect of VLSI floorplanning problem.
Sequence pair representation is employed to perturb the solution. The outcomes received after the application of SA
on different benchmark files are compared with the outcomes of different algorithms on same benchmark files and
the comparison suggests that the SA gives the better result. SA is effective and promising in VLSI floorplan design.
Matlab simulation results show that our approach can give better results and satisfy the fixed-outline and nonoverlapping
constraints while optimizing circuit performance.
POWER GATING STRUCTURE FOR REVERSIBLE PROGRAMMABLE LOGIC ARRAYecij
Throughout the world, the numbers of researchers or hardware designer struggle for the reducing of
power dissipation in low power VLSI systems. This paper presented an idea of using the power gating
structure for reducing the sub threshold leakage in the reversible system. This concept presented in the
paper is entirely new and presented in the literature of reversible logics. By using the reversible logics for
the digital systems, the energy can be saved up to the gate level implementation. But at the physical level
designing of the reversible logics by the modern CMOS technology the heat or energy is dissipated due the
sub-threshold leakage at the time of inactivity or standby mode. The Reversible Programming logic array
(RPLA) is one of the important parts of the low power industrial applications and in this paper the physical
design of the RPLA is presented by using the sleep transistor and the results is shown with the help of
TINA- PRO software. The results for the proposed design is also compare with the CMOS design and
shown that of 40.8% of energy saving. The Transient response is also produces in the paper for the
switching activity and showing that the proposed design is much better that the modern CMOS design of
the RPLA.
Fpga based efficient multiplier for image processing applications using recur...VLSICS Design
The Digital Image processing applications like medical imaging, satellite imaging, Biometric trait images
etc., rely on multipliers to improve the quality of image. However, existing multiplication techniques
introduce errors in the output with consumption of more time, hence error free high speed multipliers has
to be designed. In this paper we propose FPGA based Recursive Error Free Mitchell Log Multiplier
(REFMLM) for image Filters. The 2x2 error free Mitchell log multiplier is designed with zero error by
introducing error correction term is used in higher order Karastuba-Ofman Multiplier (KOM)
Architectures. The higher order KOM multipliers is decomposed into number of lower order multipliers
using radix 2 till basic multiplier block of order 2x2 which is designed by error free Mitchell log multiplier.
The 8x8 REFMLM is tested for Gaussian filter to remove noise in fingerprint image. The Multiplier is
synthesized using Spartan 3 FPGA family device XC3S1500-5fg320. It is observed that the performance
parameters such as area utilization, speed, error and PSNR are better in the case of proposed architecture
compared to existing architectures.
Analysis of various mcm algorithms for reconfigurable rrc fir filtereSAT Journals
Abstract
Low complexity and power consumption are the key concerns while designing reconfigurable pulse shaping FIR filter for multistandard wireless communication system. In FIR filter, the single input to be multiplied by a set of coefficients known as multiple constant multiplications. This multiple constant multiplication becomes an obstruction in many applications. To overcome that, Digit Based Recoding, Canonic Sign Digit, Common Subexpression Elimination and Binary Common Subexpression Elimination algorithms are used to optimize the number of addition and subtraction operations. While designing these MCM algorithms in the architecture of RRC FIR filter, Binary Common Subexpression Elimination (BCSE) algorithm provides the better performance in terms of area and power.
Keywords: Multiple Constant Multiplication (MCM), Root Raised Cosine Filter (RRC), Canonic Sign Digit (CSD), Multiple Sign Digit (MSD), Common Subexpression Elimination (CSE)
Arithmetic Operations in Multi-Valued LogicVLSICS Design
This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL). Quaternary to binary and binary to quaternary converters are designed using down literal circuits. Negation in modular arithmetic is designed with only one gate. Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams, keeping minimum number of gates and depth of net in to onsideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulation result of each operation is shown separately using Hspice.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Low Power and Area Efficient Multiplier Layout using Transmission GateIJEEE
This paper proposes the design and implementation of a 2-bit multiplier using fully automatic design and semi- custom design. Any digital signal processor has adder and multiplier in its core unit. Low power and high speed mac units are in high demand and therefore make a significant place in today’s vlsi environment. Power consumption of cmos circuits is a major concern in vlsi design. The proposed design is made using transmission gate logicwhich helped in using less number of cmos. The multiplier circuit is first simulated using avlsi cad tool and thus the layout was generated. The proposed circuit is simulated by using 90nm cmos technology with supply voltage of 1.2v. It is found that semi-custom based design produced better results in terms of power dissipation and area.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Reducing the Number Of Transistors In Carry Select Adderpaperpublications3
Abstract: In existing method CMOS logic involved in carry select adder (CSLA), the data dependencies and redundant logic operations are analyzed and then reduced. The carry select (CS) operation is arranged before the calculation of-final-sum, which varies from the earlier methods. But the method is not much more efficient due to power consumption is high. This paper shows the comparison of CMOS logic design and modified Gate Diffusion Input logic (Mod-GDI) and proved Mod-GDI logic is more power-efficient than Gate Diffusion Input logic (GDI), Pass Transistor Logic (PTL) and CMOS logic design in CSLA. Basic GDI logic suffers from some limitations like swing degradation, fabrication difficulty in standard CMOS process and bulk connections. These limitations can be overcome by Mod- GDI. In the proposed scheme, Mod-GDI is better than GDI and CMOS in the maximum cases with respect to area, speed, and power dissipation, and power-delay products. From the simulation results, 45% reduction in power-delay product in Mod-GDI logic in CSLA is obtained. Mod-GDI technique performs varies logic functions by using two transistors. Mod-GDI logic is suitable for designing high speed and less power consumption with reduced number of transistors. Finally, we compare the power consumption and time delay of the existing method with our proposed scheme to show our achievement on accuracy.
37 9144 new technique based peasant multiplication (edit lafi)IAESIJEECS
The Direct Form FIR channel is utilized for DSP application where the channel request is settled. For the most part this channel devours more range and power. To defeat this issue Multiplier Control Signal Decision window (MCSD) plans is joined into Direct Form FIR channel to powerfully change the channel arrange. MCSD structures comprise of Control flag Generator (CG) and Amplitude Detection (AD) rationale circuits. Advertisement rationale is utilized to disavow the correct duplication process and screen the amplitudes of information tests. CG is utilized to control the channel operation through inside counter. Traditional reconfigurable FIR channel is planned utilizing Vedic Multiplier that devours more territory and deferral. In this paper, changed reconfigurable FIR filer is intended to additionally decrease the APT (Area, Power and Timing) item. The proposed Reconfigurable FIR filer, Vedic Multiplier is supplanted by Russian Peasant Multiplication procedure. Subsequently adjusted Reconfigurable FIR channel with Russian Peasant Multiplier expends less region, postponement and power than all analyzed techniques.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Analysis of wireless sensor networks security, attacks and challengeseSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Status of noise in yeshwanthpur circle (bangalore north) based on on site dat...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Comparative study of various supervisedclassification methodsforanalysing def...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Analysis of various mcm algorithms for reconfigurable rrc fir filtereSAT Journals
Abstract
Low complexity and power consumption are the key concerns while designing reconfigurable pulse shaping FIR filter for multistandard wireless communication system. In FIR filter, the single input to be multiplied by a set of coefficients known as multiple constant multiplications. This multiple constant multiplication becomes an obstruction in many applications. To overcome that, Digit Based Recoding, Canonic Sign Digit, Common Subexpression Elimination and Binary Common Subexpression Elimination algorithms are used to optimize the number of addition and subtraction operations. While designing these MCM algorithms in the architecture of RRC FIR filter, Binary Common Subexpression Elimination (BCSE) algorithm provides the better performance in terms of area and power.
Keywords: Multiple Constant Multiplication (MCM), Root Raised Cosine Filter (RRC), Canonic Sign Digit (CSD), Multiple Sign Digit (MSD), Common Subexpression Elimination (CSE)
Arithmetic Operations in Multi-Valued LogicVLSICS Design
This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL). Quaternary to binary and binary to quaternary converters are designed using down literal circuits. Negation in modular arithmetic is designed with only one gate. Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams, keeping minimum number of gates and depth of net in to onsideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulation result of each operation is shown separately using Hspice.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Low Power and Area Efficient Multiplier Layout using Transmission GateIJEEE
This paper proposes the design and implementation of a 2-bit multiplier using fully automatic design and semi- custom design. Any digital signal processor has adder and multiplier in its core unit. Low power and high speed mac units are in high demand and therefore make a significant place in today’s vlsi environment. Power consumption of cmos circuits is a major concern in vlsi design. The proposed design is made using transmission gate logicwhich helped in using less number of cmos. The multiplier circuit is first simulated using avlsi cad tool and thus the layout was generated. The proposed circuit is simulated by using 90nm cmos technology with supply voltage of 1.2v. It is found that semi-custom based design produced better results in terms of power dissipation and area.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Reducing the Number Of Transistors In Carry Select Adderpaperpublications3
Abstract: In existing method CMOS logic involved in carry select adder (CSLA), the data dependencies and redundant logic operations are analyzed and then reduced. The carry select (CS) operation is arranged before the calculation of-final-sum, which varies from the earlier methods. But the method is not much more efficient due to power consumption is high. This paper shows the comparison of CMOS logic design and modified Gate Diffusion Input logic (Mod-GDI) and proved Mod-GDI logic is more power-efficient than Gate Diffusion Input logic (GDI), Pass Transistor Logic (PTL) and CMOS logic design in CSLA. Basic GDI logic suffers from some limitations like swing degradation, fabrication difficulty in standard CMOS process and bulk connections. These limitations can be overcome by Mod- GDI. In the proposed scheme, Mod-GDI is better than GDI and CMOS in the maximum cases with respect to area, speed, and power dissipation, and power-delay products. From the simulation results, 45% reduction in power-delay product in Mod-GDI logic in CSLA is obtained. Mod-GDI technique performs varies logic functions by using two transistors. Mod-GDI logic is suitable for designing high speed and less power consumption with reduced number of transistors. Finally, we compare the power consumption and time delay of the existing method with our proposed scheme to show our achievement on accuracy.
37 9144 new technique based peasant multiplication (edit lafi)IAESIJEECS
The Direct Form FIR channel is utilized for DSP application where the channel request is settled. For the most part this channel devours more range and power. To defeat this issue Multiplier Control Signal Decision window (MCSD) plans is joined into Direct Form FIR channel to powerfully change the channel arrange. MCSD structures comprise of Control flag Generator (CG) and Amplitude Detection (AD) rationale circuits. Advertisement rationale is utilized to disavow the correct duplication process and screen the amplitudes of information tests. CG is utilized to control the channel operation through inside counter. Traditional reconfigurable FIR channel is planned utilizing Vedic Multiplier that devours more territory and deferral. In this paper, changed reconfigurable FIR filer is intended to additionally decrease the APT (Area, Power and Timing) item. The proposed Reconfigurable FIR filer, Vedic Multiplier is supplanted by Russian Peasant Multiplication procedure. Subsequently adjusted Reconfigurable FIR channel with Russian Peasant Multiplier expends less region, postponement and power than all analyzed techniques.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Analysis of wireless sensor networks security, attacks and challengeseSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Status of noise in yeshwanthpur circle (bangalore north) based on on site dat...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
Comparative study of various supervisedclassification methodsforanalysing def...eSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Study of shape of intermediate sill on the design of stilling basin modeleSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Finite element optimization of stator by casted and welded structureseSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
Detection andprevention of fake access point using sensor nodeseSAT Publishing House
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology.
International Journal of Engineering Research and DevelopmentIJERD Editor
Electrical, Electronics and Computer Engineering,
Information Engineering and Technology,
Mechanical, Industrial and Manufacturing Engineering,
Automation and Mechatronics Engineering,
Material and Chemical Engineering,
Civil and Architecture Engineering,
Biotechnology and Bio Engineering,
Environmental Engineering,
Petroleum and Mining Engineering,
Marine and Agriculture engineering,
Aerospace Engineering.
International Journal of Engineering and Science Invention (IJESI)inventionjournals
International Journal of Engineering and Science Invention (IJESI) is an international journal intended for professionals and researchers in all fields of computer science and electronics. IJESI publishes research articles and reviews within the whole field Engineering Science and Technology, new teaching methods, assessment, validation and the impact of new technologies and it will continue to provide information on the latest trends and developments in this ever-expanding subject. The publications of papers are selected through double peer reviewed to ensure originality, relevance, and readability. The articles published in our journal can be accessed online
Arithmetic Operations in Multi-Valued Logic VLSICS Design
This paper presents arithmetic operations like addition, subtraction and multiplications in Modulo-4 arithmetic, and also addition, multiplication in Galois field, using multi-valued logic (MVL). Quaternary to binary and binary to quaternary converters are designed using down literal circuits. Negation in modular arithmetic is designed with only one gate. Logic design of each operation is achieved by reducing the terms using Karnaugh diagrams, keeping minimum number of gates and depth of net in to consideration. Quaternary multiplier circuit is proposed to achieve required optimization. Simulation result of each operation is shown separately using Hspice.
Efficient Design of Ripple Carry Adder and Carry Skip Adder with Low Quantum ...IJERA Editor
The addition of two binary numbers is the important and most frequently used arithmetic process on
microprocessors, digital signal processors (DSP), and data-processing application-specific integrated circuits
(ASIC). Therefore, binary adders are critical structure blocks in very large-scale integrated (VLSI) circuits.
Their effective application is not trivial because a costly carry spread operation involving all operand bits has to
be achieved. Many different circuit constructions for binary addition have been planned over the last decades,
covering a wide range of presentation characteristics. In today era, reversibility has become essential part of
digital world to make digital circuits more efficient. In this paper, we have proposed a new method to reduce
quantum cost for ripple carry adder and carry skip adder. The results are simulated in Xilinx by using VHDL
language.
High Performance Binary to Gray Code Converter using Transmission GATE IJEEE
This paper gives an idea to improve power efficiency and effective area of binary to gray code converter using very popular transmission gate technology. Some sensors send information in gray code. So this must be important to convert a given binary stream into its equivalent gray code. In this paper the binary to gray code converter has been developed using gate, circuit level. The conversion has been done using conventional and transmission gate level and comparing these two in terms of power, number of transistors used and last but not the least area. The simulation result shows that binary to gray code converter using transmission gate has improved power efficiency and area by 76.22% and 72.3% respectively .This paper gives the true comparison between transmission gate and conventional gate implemented binary to gray code converter in many aspects like power, area, and number of transistors used for fully automatic and semicustom layout design.
Multiple Valued Logic for Synthesis and Simulation of Digital CircuitsIJERA Editor
The Multiple valued logic(MVL) has increased attention in the last decades because of the possibility to represent the information with more than two discrete levels.Advancing from two-valued to four-valued logic provides a progressive approach. In new technologies, the most delay and power occurs in the connections between gates. When designing a function using MVL, we need fewer gates,which implies less number of connections, then less delay. In the existing system, the 4:1 multiplexer is designed using the MVL logic and various paramaters are analysed. In the proposed system, the idea of designing a Barrel shifter using the multiple valued logic and the parameters are all analyzed. All these designs are verified using Modelsim simulator.
A METHODOLOGY FOR IMPROVEMENT OF ROBA MULTIPLIER FOR ELECTRONIC APPLICATIONSVLSICS Design
In this paper, propose an approximate multiplier that is high speed yet energy efficient. The approach is to
around the operands to the closest exponent of 2. This way the machine intensive a part of the
multiplication is omitted up speed and energy consumption. The potency of the planned multiplier factor is
evaluated by comparing its performance with those of some approximate and correct multipliers using
different design parameters. In this proposed approach combined the conventional RoBA multiplier with
Kogge-stone parallel prefix adder. The results revealed that, in most (all) cases, the newly designed RoBA
multiplier architectures outperformed the corresponding approximate (exact) multipliers. Thus improved
the parameters of RoBA multiplier which can be used in the voice or image smoothing applications in the
DSP.
A METHODOLOGY FOR IMPROVEMENT OF ROBA MULTIPLIER FOR ELECTRONIC APPLICATIONSVLSICS Design
In this paper, propose an approximate multiplier that is high speed yet energy efficient. The approach is to around the operands to the closest exponent of 2. This way the machine intensive a part of the multiplication is omitted up speed and energy consumption. The potency of the planned multiplier factor is evaluated by comparing its performance with those of some approximate and correct multipliers using different design parameters. In this proposed approach combined the conventional RoBA multiplier with Kogge-stone parallel prefix adder. The results revealed that, in most (all) cases, the newly designed RoBA multiplier architectures outperformed the corresponding approximate (exact) multipliers. Thus improved the parameters of RoBA multiplier which can be used in the voice or image smoothing applications in the DSP.
A METHODOLOGY FOR IMPROVEMENT OF ROBA MULTIPLIER FOR ELECTRONIC APPLICATIONSVLSICS Design
In this paper, propose an approximate multiplier that is high speed yet energy efficient. The approach is to around the operands to the closest exponent of 2. This way the machine intensive a part of the multiplication is omitted up speed and energy consumption. The potency of the planned multiplier factor is evaluated by comparing its performance with those of some approximate and correct multipliers using different design parameters. In this proposed approach combined the conventional RoBA multiplier with Kogge-stone parallel prefix adder. The results revealed that, in most (all) cases, the newly designed RoBA multiplier architectures outperformed the corresponding approximate (exact) multipliers. Thus improved the parameters of RoBA multiplier which can be used in the voice or image smoothing applications in the DSP.
A METHODOLOGY FOR IMPROVEMENT OF ROBA MULTIPLIER FOR ELECTRONIC APPLICATIONSVLSICS Design
In this paper, propose an approximate multiplier that is high speed yet energy efficient. The approach is to
around the operands to the closest exponent of 2. This way the machine intensive a part of the
multiplication is omitted up speed and energy consumption. The potency of the planned multiplier factor is
evaluated by comparing its performance with those of some approximate and correct multipliers using
different design parameters. In this proposed approach combined the conventional RoBA multiplier with
Kogge-stone parallel prefix adder. The results revealed that, in most (all) cases, the newly designed RoBA
multiplier architectures outperformed the corresponding approximate (exact) multipliers. Thus improved
the parameters of RoBA multiplier which can be used in the voice or image smoothing applications in the
DSP
Efficient Design of Reversible Multiplexers with Low Quantum CostIJERA Editor
Multiplexing is the generic term used to designate the operation of sending one or more analogue or digital
signals over a common transmission line at dissimilar times or speeds and as such, the scheme we use to do just
that is called a Multiplexer. In digital electronics, multiplexers are similarly known as data selectors as they can
“select” each input line, are made from individual Analogue Switches encased in a single IC package as
conflicting to the “mechanical” type selectors such as standard conservative switches and relays. In today era,
reversibility has become essential part of digital world to make digital circuits more efficient. In this paper, we
have proposed a new method to reduce quantum cost and power for various multiplexers. The results are
simulated in Xilinx by using VHDL language.
Abstract: Latest technological development in VLSI design permits more functions integrated in a single chip. Multipliers are crucially important building structures for advanced computing and as a part of digital processing system. These logic and arithmetic structures should have to be speedy as well as precise enough so that number of such circuits can be integrated along a single chip. Considering this there is advancement in IC fabrication and design is still going on. In VLSI circuit area, power and delay are the parameters which are considered as design parameters. However, there exists a trade-off amongst them for an optimal design. Multipliers have very crucial and important part in designing of microprocessors, multimedia system and digital signal processors etc. Almost 15% of total IC power is consumed by multiplication unit alone. So it becomes very important to have a well organized design in terms of performance, area and its processing speed of multipliers and same as for Booth multiplication algorithm which gives a fundamental platform for such improvements in the designing of high speed multipliers with great performance.
Booth algorithm gives such an efficient encoding scheme of the bits through first steps of the multiplication process. This work is based on configurable logic for 16-bit Booth multiplier using Radix-2 and Radix-4 Method. Booth multiplier can be configured to perform multiplication on 16-bit operands. The multiplier will identify the range of the operands during configuration register. The configuration register can be configured through input ports. The multiplier has been synthesized using Xilinx 14.5 and in this simulation we have achieve minimum combinational delay. Modelsim is used for the simulation part in this work.
Keywords: Radix, XPS, VHDL, Modelsim, IC fabrication, CBM, MAC, RTL, CIAF, CLA.
Title: Implementation of Radix-4 Booth Multiplier by VHDL
Author: Prof. Sneha Singh, Prachi Singh
International Journal of Recent Research in Electrical and Electronics Engineering (IJRREEE)
ISSN 2349-7815
Paper Publications
This paper presents a compact design of Montgomery modular multiplier
(MMM). MMM serves as a building block commonly required in security
protocols relying on public key encryption. The proposed design is intended
for hardware applications of lightweight cryptographic modules that is utilized
for the system on chip (SoC) and internet of things (IoT) devices. The proposed
design is an enhancement of the original MMM without any multiplication or
subtraction processes. The main target of the new modification is enhancing
the performance and reducing the area of the MMM hardware module. The
operands and internal variables of the proposed hardware circuit is optimized
to be bounded to the smallest efficient size to minimize the area and the critical
path delay. The proposed design was coded in VHDL, implemented on the
Virtex-6 FPGA, and its performance was analyzed utilizing XILINX ISE
tools. Our design occupies the smallest area comparing with other
implementations on the same FPGA type. The proposed design saves in a
range between 60.0% and 99.0% of the resources compared with other relevant
designs.
A Review of Different Methods for Booth MultiplierIJERA Editor
In this review paper, different type of implementation of Booth multiplier has been studied. Multipliers has great importance in digital signal processor, so designing a high-speed multiplier is the need of the hour. Advantages of using modified booth multiplier algorithm is that the number of partial product is reduced. Different types of addition algorithms are also discussed which are used for addition operation of multiplier.
International Journal of Computational Engineering Research(IJCER)ijceronline
International Journal of Computational Engineering Research (IJCER) is dedicated to protecting personal information and will make every reasonable effort to handle collected information appropriately. All information collected, as well as related requests, will be handled as carefully and efficiently as possible in accordance with IJCER standards for integrity and objectivity.
Parallel Processing Technique for Time Efficient Matrix MultiplicationIJERA Editor
In this paper, we have proposed one designs for parallel-parallel input and single output (PPI-SO) matrix-matrix multiplication. In this design differs by high speed area efficient, throughput rate and user defined input format to match application needs. We have compared the proposed designs with the existing similar design and found that, the proposed designs offer higher throughput rate, reduce area at relatively lower hardware cost. We have synthesized the proposed design and the existing design using Xilinx software. Synthesis results shows that proposed design on average consumes nearly 30% less energy than the existing design and involves nearly 70% less area-delay-product than other. Interestingly, the proposed parallel-parallel input and single output (PPI-SO) structure consumes 40% less energy than the existing structure.
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Efficient implementation of bit parallel finite field multipliers
1. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
__________________________________________________________________________________________
Volume: 03 Issue: 03 | Mar-2014, Available @ http://www.ijret.org 661
EFFICIENT IMPLEMENTATION OF BIT PARALLEL FINITE
FIELD MULTIPLIERS
Ajitha.S.S1
, Retheesh.D2
1
ME, Department of ECE, St.Xavier’s Catholic College of Engineering, Tamilnadu, India
2
Assistant Professor, Department of CSE, Saveetha Engineering College, Tamilnadu, India
Abstract
Arithmetic in Finite/Galois field is a major aspect for many applications such as error correcting code and cryptography. Addition
and multiplication are the two basic operations in the finite field GF (2m
).The finite field multiplication is the most resource and time
consuming operation. In this paper the complexity (space) analysis and efficient FPGA implementation of bit parallel Karatsuba
Multiplier over GF (2m
) is presented. This is especially interesting for high performance systems because of its carry free property. To
reduce the complexity of Classical Multiplier, multiplier with less complexity over GF (2m
) based on Karatsuba Multiplier is used. The
LUT complexity is evaluated on FPGA by using Xilinx ISE 8.1i.Furthermore,the experimental results on FPGAs for bit parallel
Karatsuba Multiplier and Classical Multiplier were shown and the comparison table is provided. To the best of our knowledge, the
bit parallel karatsuba multiplier consumes least resources among the known FPGA implementation.
Keywords: Classical Multiplier, Cryptograph, FPGA, Galois field, Karatsuba Multiplier
----------------------------------------------------------------------***------------------------------------------------------------------------
1. INTRODUCTION
A finite field or Galois field is a field that contains only
finitely many elements. The finite fields are classified by size.
This classification specifies the order of the field. Notations
for the finite fields are GF (pm
) or Fp
m
, where the letters ―GF‖
stand for ―Galois field‖. The order or cardinal or number of
elements, of a finite field is of the form pm,
where p is a prime
number called the characteristic of the field and m is a positive
integer called the dimension of the field. Finite field arithmetic
operations in GF (2m
) were frequently desired in coding
theory, cryptography, digital signal processing. Coding theory
is an approach to various science disciplines such as
information theory, electrical engineering, data transmission,
mathematics and science, which helps design efficient and
reliable data transmission methods so that redundancy can be
removed and errors corrected.
Applications of cryptography include ATM cards, computer
passwords and e-commerce. Cryptography is the practice and
study of hiding information. Modern cryptography intersects
the disciplines of mathematics, computer science and
engineering. In these applications, multiplication is the most
common arithmetic. Thus it is desirable to design hardware-
efficient multiplier for GF (2m
) to meet the real time
requirement with minimum hardware complexity.
There are three popular types of bases over finite fields:
polynomial basis (PB), normal basis (NB) and dual basis
(DB). Basis is a set of vectors that, in a linear combination,
can represent every vector in a given vector space. Polynomial
basis is a mathematical function that is the sum of a number of
terms. Normal basis in field theory is a special kind of basis
for Galois extensions of finite degree, characterized as a
forming a single orbit for the Galois group. Dual basis is a set
of vectors that forms a basis for the dual space of a vector
space. One advantage of the normal basis is that the squaring
of an element is computed by a cyclic shift of the binary
representation. The dual basis multipliers require less chip
area than other two types.
The polynomial basis multipliers are widely used and lead to
efficient implementations of multipliers. As compared to other
two bases multipliers, the polynomial basis multipliers have
low design complexity and their sizes are easier to extend to
meet various applications due to their simplicity, regularity,
and modularity in architecture. It appears that polynomial
multipliers for classes of trinomials still achieve the lowest
circuit complexity
Arithmetic operations such as addition and multiplication are
the two basic operations in the finite field GF (2m
). Addition in
GF (2m
) is easily realized using m two-input XOR gates while
multiplication is costly in terms of gate count and time delay.
The other operations of finite fields, such as exponentiation,
division and inversion can be performed by repeated
multiplications. As a result there is a need to have fast
multiplication architecture with low complexity.
The hardware/software implementation efficiency of finite
field arithmetic is measured in terms of the associated space
and time complexities. The space complexity is defined as the
number of XOR and AND gates needed for the
2. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
__________________________________________________________________________________________
Volume: 03 Issue: 03 | Mar-2014, Available @ http://www.ijret.org 662
implementation of the circuit. The space and time
complexities of a multiplier heavily depend on how the field
elements are represented. Finite field multipliers with different
bases of representation have been realized to be used for
various applications. The polynomial basis multipliers are
more efficient and more widely used compared with
multipliers in the other bases of representations.
1.1 Related Work
C.Grabbe,M.Bednara,J.Teich, [1] presented four high
performance GF(2233) multipliers for an FPGA realization
and analyzed the time and area complexities. The finite field
elements are represented as polynomial basis and normal
basis. In polynomial basis, classical multiplier and Karatsuba
multipliers were designed.The advantage of classical
multiplier is regular structure and pipelined operation.The
disadvantage is high space complexity. In Karatsuba
multiplier the advantage is less number of gates are
required.The normal basis multipliers are Massey-Omura and
Sunar-Koc multiplier. The advantage of Massey-Omura is
high flexibility and Sunar-Koc is total number of gates are
reduced.
P.L.Montgomery,[2] presented Karatsuba Ofman algorithm
for multiplying two polynomials. Here multiplication of 5-
term, 6-term and 7-term polynomials are provided with scalar
multiplication of 13,17 and 22.Using 6-term polynomial only
leads to better asymptotic performance than standard
karatsuba.
C.Paar, [3] presented a new bit parallel structure for a
multiplier with low space complexity in Galois field is
introduced. Finite field of GF(2n
) is considered and field
extension of GF((2n
)m
). The field elements are represented in
the canonical base or in standard basis. Field of the form
GF((2n
)m
) are referred as composite field. Karatsuba Ofman
algorithm is used to multiply two polynomials effectively.
Advantages are complexity is reduced by introducing the
composite field. The main disadvantage is security is less and
does not have a regular structure.
C.Rebeirno and D.Mukhopadhyay, [4] presented a hybrid
technique which has a better area delay product. Masking
strategies are introduced to prevent power based side channel
attacks on the multiplier. SCAs are the biggest threat to
modern cryptography systems. In basic recursive KM, the
number LUTs required to combine the partial products is
much lower but it cannot applied directly to ECC. The hybrid
KM requires least resources as compared to other KMs used
for elliptic curve arithmetic; also it has a unique architecture.
Demerits are it is not efficient for FPGA platform as the
number of utilized LUTs is 65%.
A.Reyhani-Masoleh and A.Hasan, [5] presented a new bit
parallel structure for the polynomial basis multiplication
which is applicable to all type of irreducible binary
polynomial. The main advantage of this new formulation is
that it can be used with any field defining irreducible
polynomial. Then a bit parallel hardware architecture
generalization is provided. The architecture consist of two
parts IP network and Q network. The space and time
complexities are analysed as a function of reduction matrix Q.
the main advantage is only fewer number of lines are required
on the bus.
F.Rodriguez and C.K.Koc,[6] presented the Karatsuba-
Ofman Algorithm in which the degree of defining the
irreducible polynomial can be arbitrarily selected by the
designer allowing the usage of prime degrees. Here finite field
and composite field are considered. Composite multiplication
is performed by n-bit Karatsuba multiplier. The main
advantage is number of multiplication is reduced. The
composite field multiplication is performed by binary
Karatsuba multipliers. The advantage is improved gate
complexity .The disadvantage is wastage of several arithmetic
operation.
B.Sunar,[7] presented the subquadratic complexity multipliers
for even characteristic field extension. A short convolution
algorithm named Winograd short convolution algorithm were
designed to improve the space and time complexity. A certain
Winograd short convolutional algorithm is essentially
identical to the Karatsuba algorithm. The merits of Winograd
techniques are it can be easily built for any desired length; it is
simple and uniform construction. The main disadvantages are
appears to have less structure and cause additional wire delay
in VLSI implementation.
A.Weimerskirch and C.Paar, [8] presented the classical
Karatsuba algorithm for polynomial multiplication. Three
methods considered are digital method, Fast Fourier transform
method and Karatsuba method. The Karatsuba algorithm is
derived in two ways namely Chinese Remainder Theorem and
Simple Algebraic Transform KA is applied recursively if the
degree of polynomial is 2i
, where i>1 is a positive integer.
Advantage- squaring the polynomial is easily performed;
adding a dummy coefficients the complexity is reduced.
Disadvantage is a number of intermediate results have been
stored due to the recursive nature of KA.
J.VonzurGathen and J.Shokrollahi, [9] presented different
possibilities for implementing the Karatsuba multiplier for
polynomials over F2 on FPGA. Classical multiplier, Karatsuba
multiplier and a hybrid design were provided. The Karatsuba
multiplier has the lowest crossover point with the classical
algorithm. In hardware, the algorithmic and platform
dependent optimizations yield efficient designs. The resources
usage of polynomial multipliers is decreased by using both the
algorithmic and platform dependent method. The hybrid
design is used to minimize the total arithmetic cost and results
in significant area savings.
3. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
__________________________________________________________________________________________
Volume: 03 Issue: 03 | Mar-2014, Available @ http://www.ijret.org 663
G.Zhou, H.Michalik and L.Hinsenkamp, [10] addresses the
efficient and high throughput implementations of AES-GSM
optimized for FPGAs. The two main components in GCM are
an AES engine and a finite field multiplier over GF (2128
).The
complexity analysis presented is based on FPGA primitives
(LUTs). Modular multiplication consists of two steps: first a
classical multiplication and then a modular reduction. The
straight forward multiplier is used to get speed efficient design
while a Karatsuba multiplier is used to get an area efficient
design. Merits are reduced hardware complexity and high
throughput.
2. FINITE FIELD ARITHMETIC
Arithmetic in a finite field is different from standard integer
arithmetic. There are limited numbers of elements in the finite
field; all operations performed in the finite fields result in an
element within that field. While each finite field itself is not
infinite, there are infinitely many different finite fields; their
number of elements is necessarily of the form pn
. and the two
finite fields of the same size are isomorphic. An element α in
GF (2m
) can be represented as a polynomial, where αi € GF
(2m
).
Addition of two elements in GF (2m
) is performed as
polynomial addition in
GF (2m
)
Where + is XOR operation.
2.1 Addition and Multiplication In Finite Field
Addition and subtraction are performed by adding or
subtracting two of these polynomials together, and reducing
the result modulo the characteristic. In a finite field with
characteristic 2, addition and subtraction are identical, and are
accomplished using the XOR operator. When two polynomials
are added, each term is added independently; there is no
concept of a carry from one term to another.
Thus, Polynomial:
(x6
+ x4
+ x + 1) + (x7
+ x6
+ x3
+ x) = x7
+ x4
+ x3
+ 1
Binary: {01010011} + {11001010} = {10011001}
Hexadecimal: {53} + {CA} = {99}
Notice that under regular addition of polynomials, the sum
would contain a term 2x6
, but that this term becomes 0x6
and is
dropped when the answer is reduced modulo 2.
In binary representation, the coefficients can be only 1 or
0.When adding the coefficients, the following rule applies:
o 0+0=0
o 0+1=1
o 1+0=1
o 1+1=0(there is no carry)
Table-1: Polynomial Addition
Table-1 shows both the normal algebraic sum and the
characteristic 2 finite field sum of a few polynomials:
In computer science applications, the operations are simplified
for finite fields of characteristic 2, also called GF(2n
) Galois
fields, making these fields especially popular choices for
applications. The same logic that made addition become XOR
also applies to subtraction. The exclusive OR operation is
easier for digital logic than binary additions.
Multiplication in a finite field is multiplication modulo an
irreducible reducing polynomial used to define the finite field.
(i.e., it is multiplication followed by division using the
reducing polynomial as the divisor—the remainder is the
product.) The symbol "•" may be used to denote multiplication
in a finite field. Example: Rijndael's finite field
Rijndael uses a characteristic 2 finite field with 8 terms, which
can also be called the Galois field GF (28
). It employs the
following reducing polynomial for multiplication:
x8
+ x4
+ x3
+ x + 1.
For example, {53} • {CA} = {01} in Rijndael's field because
(x6
+ x4
+ x + 1)(x7
+ x6
+ x3
+ x) =
x13
+ x12
+ x9
+ x7
+ x11
+ x10
+ x7
+ x5
+ x8
+ x7
+ x4
+ x2
+ x7
+
x6
+ x3
+ x =
p1 p2
p1 + p2 (normal
algebra)
p1 + p2 in GF(2n
)
x3
+ x + 1 x3
+ x2
2x3
+ x2
+ x + 1 x2
+ x + 1
x4
+ x2
x6
+ x2
x6
+ x4
+ 2x2
x6
+ x4
x + 1 x2
+ 1 x2
+ x + 2 x2
+ x
x3
+ x x2
+ 1 x3
+ x2
+ x + 1 x3
+ x2
+ x + 1
x2
+ x x2
+ x 2x2
+ 2x 0
4. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
__________________________________________________________________________________________
Volume: 03 Issue: 03 | Mar-2014, Available @ http://www.ijret.org 664
x13
+ x12
+ x9
+ x11
+ x10
+ x5
+ x8
+ x4
+ x2
+ x6
+ x3
+ x =
x13
+ x12
+ x11
+ x10
+ x9
+ x8
+ x6
+ x5
+ x4
+ x3
+ x2
+ x
And
x13
+ x12
+ x11
+ x10
+ x9
+ x8
+ x6
+ x5
+ x4
+ x3
+ x2
+ x
modulo x8
+ x4
+ x3
+ x + 1 = (11111101111110 mod
100011011) = 1, which can be performed through long
division method
2.2 Classical Multiplier
The Classical multiplier is the simplest multiplier to perform
finite field multiplication. It is also called as paper and pencil
method or traditional method. To perform the classical
multiplication it requires only AND gates and XOR gates. The
number of AND gates required is n2
and (n-1)2
XOR gates,
where n is bit depth. The total gate complexity is 2n2
-1 and the
time complexity is TAND+(log2n)TXOR. Figure 1 shows the
calculation of the product of two 4-bit integer numbers given
by A3A2A1A0 (multiplicand) and B3B2B1B0 (multiplier).
A3 A2 A1 A0
B3 B2 B1 B0
A3.B0 A2.B0 A1.B0 A0.B0
A3.B1 A2.B1 A1.B1 A0.B1
A3.B2 A2.B2 A1.B2 A0.B2
A3.B3 A2.B3 A1.B3 A0.B3
S6 S5 S4 S3 S2 S1 S0
Fig-1: 4-bit multiplication
Each of the ANDed terms is referred to as a partial product.
The final product is obtained by summing each column of
partial products and is implemented using half adders.. If carry
comes, it must be propagated from the right to the left across
the columns. Adder that accepts a carry from the right must be
a full adder. 4-bit classical multiplier is shown in figure 2.
Fig -2 4-bit Classical Multiplier
The classical multiplier consists of AND gates, Full Adders
and Half adders. The 16 AND gates forms the sixteen partial
products. It is formed by ANDing all combinations of the four
multiplier bits with the four multiplicand bits. The column
sums are obtained using a combination of half and full adders.
The half adder blocks accept two bits to be added from the
top, carry out exits from the left of each block. The output
from the bottom of a block is the sum. The full adder accepts
two bits to be added from the top, any carry in from the right
and carryout exist from left of each block. The bottom of each
block gives the output. The least significant output bit, S0 is
computed as the product of two input bits A0 and B0.This
operation cannot generate a carry out. The next output bit, S1,
involves the sum of two partial products. A half adder is used
to form the sum since there can be no carry in from the first
column.
The third output bit, S2, is formed from the sum of three (1-
bit) partial products plus a possible carry in from the previous
bit. This operation requires two cascaded adders to sum the
four possible input bits (three partial products and one possible
carry in from the right). The remaining output bits are formed
similarly.
2.3 Karatsuba Multiplier
The Karatsuba algorithm is an efficient multiplication
algorithm. It reduces the multiplication of two n-digit numbers
to at most single digit multiplications. It is the fast
multiplication algorithm and at the same time it is the fast
computational algorithm. It uses the technique divide and
conquer technique. That is Karatsuba algorithm is applied to
large degree polynomials by splitting it into a lower and an
upper half. The algorithm becomes recursive if its applied
again to multiply these polynomial half’s.
The next iteration step splits these polynomial again in half.
The algorithm eventually terminates after t-steps. In the final
step the polynomial degenerates into single coefficients. This
recursive splitting of polynomials and the special reassembling
of the partial products ,drastically reduces the number of AND
gates to nlog
2
3
or n1.59
but the n umber of XOR gates increased
to 6nlog
2
3
-8n+2 which is very efficient when the polynomials
become large. But in GF(2n
), multiplication is a quite
expensive operation and an addition can be performed at
nearly no costs(since an XOR is very small on an FPGA and
no carry bits exist) .
For the modular multiplier, the straight forward multiplication
is used to get a speed efficient design, while the karatsuba
algorithm is used to get an area efficient design. But by
combining classical and Karatsuba, we get a high performance
and highly efficient multipliers. Squaring can be easily
performed by applying Karatsuba algorithm.
5. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
__________________________________________________________________________________________
Volume: 03 Issue: 03 | Mar-2014, Available @ http://www.ijret.org 665
In general consider two polynomials of degree m-1
m-1 m-1 m/2-1
A = ∑ αixi
= ∑ αixi
+ ∑ αixi
i=0 i=m/2 i=0
m/2-1 m/2-1
= xm/2
∑ αi+m/2xi
+ ∑ αixi
= xm/2
AH
+AL
i=0 i=0
and
m-1 m-1 m/2-1
B = ∑ bixi
= ∑ bixi
+ ∑ bixi
i=0 i=m/2 i=0
m/2-1 m/2-1
=xm/2
∑ bi+m/2xi
+ ∑ bixi
= xm/2
BH
+BL
i=0 i=0
The polynomial product is
C=xm
AH
BH
+(AH
BL
+AL
BH
) x(m/2)
+ AL
BL
.
To perform an n-bit multiplication we need an algorithm that
divides the n-bit multiplication into several one bit
multiplications, which are the only multiplications that can be
computed directly (i.e., by an AND-gate). With Karatsuba’s
divide and conquer multiplication algorithm, a multiplication
of two n-bit polynomials can be computed with three n=2-bit
multiplications and some additions (which are XOR’s in our
case) to determine interim results and accumulate the final
result. If n is four or more, the three multiplications in
Karatsuba's basic step involve operands with less than n digits.
Therefore, those products can be computed by recursive calls
of the Karatsuba algorithm. Figure 3 denotes 1-bit polynomial
karatsuba multiplier. ―.‖denotes multiplication in finite field.
Fig-3: one bit polynomial Karatsuba multiplier
Fig-4: 2- bit polynomial Karatsuba multiplier
Figure 4 shows the two bit polynomial Karatsuba multiplier
KM2.Here the dot represents the finite field multiplication
(AND gate ) and the plus represents the addition(XOR
gate).The two bit polynomial is derived from three one bit
polynomial Karatsuba multiplier KM1 in addition some
XOR gates are also used. Here a0,a1,b0,b1 are the coefficients
of the one degree polynomial and it is given as input to KM2 ;
c0,c1,c2 are the output of KM2.In normal classical multipliers
requires 4 AND gates and 3 XOR gates. But in Karatsuba
multiplier requires only 3 AND gates and 4 XOR gates. Thus
the space complexity of the multiplier is reduced.
Fig-5: 4- bit polynomial Karatsuba multiplier
6. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
__________________________________________________________________________________________
Volume: 03 Issue: 03 | Mar-2014, Available @ http://www.ijret.org 666
Figure 5 shows the 4- bit polynomial Karatsuba multiplier
KM4. Here the dot represents the finite field multiplication
(AND gate) and the plus represents the addition (XOR gate).
The 4-bit polynomial is derived from three 2-bit polynomial
Karatsuba multiplier KM2 in addition some XOR gates are
also used.
3. RESULTS
In this paper, finite field multipliers are developed and is
simulated using Xilinx ISE 8.1i in Verilog. It is synthesized
using Xiinx Virtex 4, device Xe3VS500E (package FT250,
speed grade -4) and the comparison results are extracted from
the synthesis report.
The simulated waveform for the classical multiplier is shown
in figure 6. Here the inputs are a= 0101 and b= 1000. The
output is c=101000.
Fig-6: simulated waveform for classical multiplier
The simulated Waveform for Karatsuba Multiplier is shown in
figure 7. The inputs given area=1111 and b=0100. The output
is c=111100
Fig-7: simulated waveform for Karatsuba multiplier
Table-2: Comparison of 4-bit Multipliers
Multiplier
No.of 4-input
LUTs
Total Memory Usage
(kb)
No.of Slices
Delay
(ns)
No. of bonded
IOBs
Classical Multiplier 29 118448 17 13.812 16
Karatsuba Multiplier 11 117424 6 7.563 15
7. IJRET: International Journal of Research in Engineering and Technology eISSN: 2319-1163 | pISSN: 2321-7308
__________________________________________________________________________________________
Volume: 03 Issue: 03 | Mar-2014, Available @ http://www.ijret.org 667
Table 2 shows the comparative results of both classical and
Karatsuba multipliers. From the table, karatsuba multiplier
consumes less space than the classical multiplier.
4. CONCLUSIONS
Finite field multipliers play a very important role in the areas
of digital communication especially in the areas of
cryptography, error control coding and digital signal
processing. In this paper, two multipliers namely classical and
Karatsuba multipliers were simulated. The comparison results
show that Karatsuba multiplier is more efficient than the other
multiplier. Using Karatsuba multiplier we can improve the
performance of the process. The Karatsuba algorithm is an
optimization technique used for decomposing larger
multiplications into multiple smaller multiplications. This
feature allows the multiplier to be scaled easily.
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