![3 address instruction
Needs very long words to hold everything
Not common
1. ADD F,A,B F A+B
2. MPY T,D,E T DxE
3. SUB T,T,C T T-C
4. DIV F,F,T F F/T
25
Op-code Result Operand 1 Operand 2
F = (A + B) / [(C - (D x E)]](https://image.slidesharecdn.com/instructionsetprasenjitdey-210209170748/75/Instruction-set-prasenjit-dey-25-2048.jpg)
![2 address instruction
Reduces length of instruction
Requires extra work: temporary storage
1. MOVE F,A F A
2. ADD F,B F F+B
3. MOVE T,D T D
4. MPY T,E T TxE
5. SUB T,C T T-C
6. DIV F,T F F:T
26
Op-code Result Operand 1
F = (A + B) / [(C - (D x E)]](https://image.slidesharecdn.com/instructionsetprasenjitdey-210209170748/75/Instruction-set-prasenjit-dey-26-2048.jpg)
![1 address instruction
Implicit second address, usually a register (accumulator, AC)
1. LOAD D AC D
2. MPY E AC ACxE
3. SUB C AC AC-C
4. STOR F F AC
5. LOAD A AC A
6. ADD B AC AC+B
7. DIV F AC AC:F
8. STOR F F AC
27
Op-code Operand 1
F = (A + B) : [(C - (D x E)]](https://image.slidesharecdn.com/instructionsetprasenjitdey-210209170748/75/Instruction-set-prasenjit-dey-27-2048.jpg)
Uploaded byPrasenjit Dey
Instruction set (prasenjit dey)
The document discusses instruction sets and their components. It defines an instruction set as the list of instructions available for the CPU, which are encoded in binary machine language or assembly language mnemonics. Each instruction contains an operation code and may include source and destination operand references. Instruction formats can vary in the number of operands from zero to three addresses. Instruction length, encoding techniques, and types of instructions like data transfer, arithmetic, and control instructions are also covered.
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Instruction set (prasenjit dey)
- 1.
- 2. Contents 2 • What isinstruction set? • Elements of an Instruction • Op-code Encoding • Instruction Types • Data Transfer, data Processing, and Control • Types of Operand • Instruction Formats • Instruction Length • Number of Addresses
- 3. What is anInstruction Set? • It is the list of instructions available for the CPU • RISC, CISC, VLIW, etc. • These instructions are written in machine language(binary representation) • But for human understanding, we represent the instructions in assembly level language • Assembly language consists of mnemonics • e.g., MOV A, B (A B) • Here, Op-code is MOV and Operands are A, B 3
- 4. Elements of anInstruction Operation code (Op-code) e.g., LOAD, STOR, ADD, SUB, MPY, DIV Source operand reference address of source operand of operation, e.g. register, memory location, I/O Destination operand reference address of destination /result operand of operation, e.g. register, memory location, I/O 4
- 5. Simple Instruction Format5 Op-code Source operand reference Destination operand reference 32 bits 8 bits 12 bits 12 bits 4 byte instruction
- 6. Byte ordering howthe bytes of an instruction are organized in a word 1. Big-endian: bytes in word are ordered from left-to-right, e.g., Motorola 2. Little-endian: bytes in word are ordered right-to-left, e.g., Intel 6 Big endian 0 0 1 2 3 4 4 5 6 7 8 8 9 10 11 12 12 13 14 15 Address 32 bits Little endian 3 2 1 0 0 7 6 5 4 4 11 10 9 8 8 12 13 14 15 12 Address 32 bits Word 0 Word 1 Word 2 Word 3 Word 0 Word 1 Word 2 Word 3
- 7. Instruction Cycle StateDiagram7 Instruction fetch Instruction decode Operand address computation Operand fetch Operation Operand address computation Operand store Instruction address computation Multiple operands Multiple results Return vector data Fetch next instruction
- 8. Op-code Encoding Op-codefield must have at least N bits to encode 2N instructions Need Op-code encoding technique There are 2 types of op-code encoding 1. Block-code technique 2. Expanding op-code technique Block-code technique An N-to-2N decoder is used to decode all the instructions. 8 N-to-2N decoder N-bit op-code instruction 0 instruction 1 instruction 2 Instruction 2N - 1 . . . . . .
- 9. Op-code Encoding Op-code Address1 Address 2 Address 3 1 1 1 1 Op-code Address 1 Address 2 9 Expanding op-code technique If there are only 15 such three-address instructions then one of the unused op-code can be used to expand the instruction set it to two-address, one-address or zero address instructions A compromise between large instruction set and short op- codes, thus short instructions When the op-code is short, a lot of bits are left to hold the operands Let an (4+12) bit instruction with a 4-bit op-code and three 4- bit addresses can at most encode (24=16) three-address instructions
- 10. Expanding op-code technique 11 1 1 1 1 1 1 Op-code Address 1 1 1 1 1 1 1 1 1 1 1 1 1 Op-code 10 Similarly, this expanded op-code field can encode at most 16 two-address instructions. if there are less than 16 such instructions, we can expand the op-code further Here, the three-address instruction can hold 3 operands of 4-bit address fields or it can hold 1 operand of12-bit address field Some part of the op-code can be used to specify the instruction format and/or length
- 11. 11 Let encodethe following instructions 15 instructions with 3 addresses 14 instructions with 2 addresses 31 instructions with 1 address 16 instructions with 0 address 0000 O1 O2 O3 1110 O1 O2 O3 1111 0000 O1 O2 1111 1101 O1 O2 1111 1110 0000-1111 O1 1111 1111 0000-1110 O1 1111 1111 1111 0000 1111 1111 1111 1111 Expanding op-code technique
- 12. Instruction length Vs.speed • Shorter instructions have faster fetch and decode time • Advantages of shorter instructions are: 1. less space in memory 2. Faster transfer to the CPU • Each instructions in instruction set can be encoded with minimum number of bit – Huffman encoding • But instructions need to be decoded bit by bit, can be slow 12
- 13. Design Goals Operation How many ops? What can they do? How complex are they? Data types (length of words, number representation) Instruction formats Length of op-code field Length and number of addresses Registers Number of CPU registers available Which operations can be performed on which registers? General purpose and specific registers Addressing modes (next class) 13
- 14. Types of theinstructions There are 3 types of instructions 1. Data transfer: registers, main memory, stack or I/O 2. Data processing: 1. Arithmetic, e.g., ADD, SUB 2. logical, e.g., AND, OR 3. Control: 1. system control, e.g., Test-And-Set 2. Program Control 1. Unconditional branch, e.g., J B 2. Conditional branch, e.g., BEQ A, B, target 3. Subroutine call, e.g., RET 4. Interrupt-handling, e.g., TRAP 14
- 15. Data Transfer 15 I/O Operations . In case of I/O mapped I/O, dedicated I/O instructions are used , e.g. INPUT, OUTPUT But, in case of memory mapped I/O, data transfer instructions are used Or it may be done by a separate controller (DMA), e.g., Start I/O, Test I/O Load, Store, move, clear, set, push, pop, etc. Contains source and destination operand Register, memory, stack
- 16. Arithmetic ADD, SUB,MUL, DIV, INC, DEC, etc. May include data transfer instructions 16 Logical AND, OR, NOT, XOR, SET, CMP May include shift instructions to perform complex tasks Arithmetic left shift multiply the operand by 2 (without overflow) Arithmetic right shift divide the operand by 2 (truncate for odd number) logical right shift is used to transfer the lower order byte from from 16-bit word
- 17. Control Instruction System control privileged instructions used to accessing control registers or process table, e.g., STOP, HALT, RTE, etc. Used by operating systems in kernel mode 17 Program Control/ Control Transfer Unconditional branch: jump into any location without condition, e.g., J conditional branch: Jump into any location based upon some condition, e.g., BEQ Subroutine call: used to call a subroutine, e.g., CALL, RET Interrupt-handling: used to invoke an interrupt, e.g., TRAP
- 18. Branch Instruction 18 Memory Address 500 501 502 . . . 700 701 . . . ADDA, B BRZ 701 BR 501 unconditional branch conditional branch Instructions
- 19. Nested Subroutine Calls19 Memory …… Call Subroutine 1 …… Return Subroutine 1 Subroutine 2 Main Program …… Call Subroutine 2 …… Call Subroutine 2 …… Return …… …… …… Return Control flow diagram Address 500 600 601 1000 1100 1101 2000 1200 1201
- 20. Use of Stackand stack pointer 20 601 1201 601 601 1101 601 601 Next address after call subroutine 1 SP = 601 Next address after call subroutine 2 SP = 1101 Return from subroutine 2 Pop 1101 Next address after call subroutine 2 SP = 1201 Return from subroutine 2 Pop 1201 Return from subroutine 1 Pop 601 500 : Main Program 600 : call Subroutine 1 1100 : call Subroutine 2 1200 : call Subroutine 2
- 21. Types of Operand Addressing mode: direct, indirect, etc. Number representation: integer, fixed point (2scomplement) floating point (sign, significant, exponent) (packed) decimal Character coding: ASCII Flag bits (Boolean 0 or Boolean 1) 21
- 22. Instruction Formats Itis the bit encoding in an instruction It consists of 2 fields 1. Op-code field 2. Operand field Operand(s) can be implicit or explicit There exists different instruction formats in an instruction set 22
- 23. Instruction Length Thelength of an instruction depends on the followings: 1. Memory size 2. Addressing mode 3. Bus structure, e.g., width 4. CPU complexity 5. CPU speed Trade off between powerful instruction set and saving space Expanding op-code technique 23
- 24. Number of Addressesin an instruction More addresses Registers and inter-register operations are quicker Less instructions per program More complex instructions Fewer addresses Faster fetch/execution of instructions More instructions per program, e.g. data movement Less complex instructions 24 Based on number of addresses instructions can be of 4 types 1. 3 address instruction 2. 2 address instruction 3. 1 address instruction 4. 0(zero) address instruction
- 25. 3 address instruction Needs very long words to hold everything Not common 1. ADD F,A,B F A+B 2. MPY T,D,E T DxE 3. SUB T,T,C T T-C 4. DIV F,F,T F F/T 25 Op-code Result Operand 1 Operand 2 F = (A + B) / [(C - (D x E)]
- 26. 2 address instruction Reduces length of instruction Requires extra work: temporary storage 1. MOVE F,A F A 2. ADD F,B F F+B 3. MOVE T,D T D 4. MPY T,E T TxE 5. SUB T,C T T-C 6. DIV F,T F F:T 26 Op-code Result Operand 1 F = (A + B) / [(C - (D x E)]
- 27. 1 address instruction Implicit second address, usually a register (accumulator, AC) 1. LOAD D AC D 2. MPY E AC ACxE 3. SUB C AC AC-C 4. STOR F F AC 5. LOAD A AC A 6. ADD B AC AC+B 7. DIV F AC AC:F 8. STOR F F AC 27 Op-code Operand 1 F = (A + B) : [(C - (D x E)]
- 28. 0 (zero) addressinstruction All addresses are implicit, e.g. ADD Uses a stack 1. pop A 2. pop B 3. ADD 4. Push 28 Op-code C = (A + B)