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Numerical on General
Pipelines
Dr. Prasenjit Dey
Dynamic Pipeline
Paths = s1s2s3s2s3s1s3s1
Reservation table for the function X
1 2 3 4 5 6 7 8
S1 X X x
S2 X x
S3 X x X
Latency
Latencies causing collision = {(6-1),(8-1),(8-6),(4-2),(5-3),(7-5),(7-3)}
Forbidden latency = {5, 7, 2, 4} = {2,4,5,7}
Maximum forbidden latency = max(Forbidden latency) = 7
Permissible latency = latency sequence = {1,3,6,8+}
1 2 3 4 5 6 7 8
S1 X1 X1 x1
S2 X1 x1
S3 X1 X1 X1
Collision free scheduling
 To avoid collisions, all tasks should be scheduled properly
 The objective is to achieve shortest average latency
between initiations without causing collisions
 Steps to achieve shortest average latency are
 Computation of collision vector
 Formation of State diagram
 Computation of greedy cycles
 Computation of Minimum Average Latency (MAL)
Collision Vectors
 A vector of m-bits, where m is Max(forbidden latency)
 Length of collision vector = maximum forbidden latency = 7
 The bit position (Bi)= 1 if latency i causes collision
 The bit position (Bi)= 0 if latency i do not cause collision
 Collision vector is = (cm,cm-1, …, c2, c1) = 1011010
 This is the Initial Collision Vector (ICV)
1 2 3 4 5 6 7 8
S1 X1 X1 x1
S2 X1 x1
S3 X1 X1 X1
State Diagrams
 A state diagram is formed from the collision vector
 It shows are permissible state transitions among successive
initiations
 Right shift ICV, then OR it with ICV
1011010
1011011 1111111
8+
3 6 8+ 1* 8+
3* 6
1011010 >>1
0101101
0101101
OR
1011010
1111111
Greedy Cycles
 Simple cycles: a latency cycle in which each state appears only
once
 Greedy cycles: Is a simple cycle whose edges are all made with
minimum latencies from their respective starting states
 Their average latencies must be lower than those of other simple
cycles
 Simple cycles were (1,8),(3,6),(6,8)(8)(3),(6)
 Greedy cycles = (3),(1,8)
 Average Latency(3)=3
 Average Latency(1,8)=4.5
 MAL (Minimum Average Latency)= 3
Schedule Optimization
 As greedy cycle not sufficient for optimality of MAL, lower
bound on MAL is required
 Optimize the reservation table to obtain the lower bound
Thank you

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Numerical on general pipelines

  • 2. Dynamic Pipeline Paths = s1s2s3s2s3s1s3s1 Reservation table for the function X 1 2 3 4 5 6 7 8 S1 X X x S2 X x S3 X x X
  • 3. Latency Latencies causing collision = {(6-1),(8-1),(8-6),(4-2),(5-3),(7-5),(7-3)} Forbidden latency = {5, 7, 2, 4} = {2,4,5,7} Maximum forbidden latency = max(Forbidden latency) = 7 Permissible latency = latency sequence = {1,3,6,8+} 1 2 3 4 5 6 7 8 S1 X1 X1 x1 S2 X1 x1 S3 X1 X1 X1
  • 4. Collision free scheduling  To avoid collisions, all tasks should be scheduled properly  The objective is to achieve shortest average latency between initiations without causing collisions  Steps to achieve shortest average latency are  Computation of collision vector  Formation of State diagram  Computation of greedy cycles  Computation of Minimum Average Latency (MAL)
  • 5. Collision Vectors  A vector of m-bits, where m is Max(forbidden latency)  Length of collision vector = maximum forbidden latency = 7  The bit position (Bi)= 1 if latency i causes collision  The bit position (Bi)= 0 if latency i do not cause collision  Collision vector is = (cm,cm-1, …, c2, c1) = 1011010  This is the Initial Collision Vector (ICV) 1 2 3 4 5 6 7 8 S1 X1 X1 x1 S2 X1 x1 S3 X1 X1 X1
  • 6. State Diagrams  A state diagram is formed from the collision vector  It shows are permissible state transitions among successive initiations  Right shift ICV, then OR it with ICV 1011010 1011011 1111111 8+ 3 6 8+ 1* 8+ 3* 6 1011010 >>1 0101101 0101101 OR 1011010 1111111
  • 7. Greedy Cycles  Simple cycles: a latency cycle in which each state appears only once  Greedy cycles: Is a simple cycle whose edges are all made with minimum latencies from their respective starting states  Their average latencies must be lower than those of other simple cycles  Simple cycles were (1,8),(3,6),(6,8)(8)(3),(6)  Greedy cycles = (3),(1,8)  Average Latency(3)=3  Average Latency(1,8)=4.5  MAL (Minimum Average Latency)= 3
  • 8. Schedule Optimization  As greedy cycle not sufficient for optimality of MAL, lower bound on MAL is required  Optimize the reservation table to obtain the lower bound