ppt

1. Instruction Code format, Instruction
Cycle and Instruction Format

2. Instruction code
• A computer instruction is a binary code that
determines the micro-operations in a
sequence for a computer.
• They are saved in the memory along with the
information. Each computer has its specific
group of instructions.

3. Instruction code
• They can be categorized into two elements as
Operation codes (Opcodes) and Address.
Opcodes specify the operation for specific
instructions.
• An address determines the registers or the
areas that can be used for that operation.
Operands are definite elements of computer
instruction that show what information is to
be operated on.

4. Instruction code
• It consists of 12 bits of memory that are required to
define the address as the memory includes 4096
words.
• The 15th bit of the instruction determines the
addressing mode (where direct addressing corresponds
to 0, indirect addressing corresponds to 1).
• Therefore, the instruction format includes 12 bits of
address and 1 bit for the addressing mode, 3 bits are
left for Opcodes.

5. Instruction code format

6. Addressing Modes
• Instructions that define the address of a
definite memory location are known as
memory reference instructions.
• The method in which a target address or
effective address is recognized within the
instruction is known as addressing mode.

7. Addressing Mode
• The address field for instruction can be represented
in two different ways are as follows −
Direct Addressing − It uses the address of the
operand.
Indirect Addressing − It facilitates the address
as a pointer to the operand.
• The address of the operand or the target address is
called the effective address.
• Effective Address (EA) − It defines the address that
can be executed as a target address for a branch type
instruction or the address that can be used directly
to create an operand for a computation type
instruction, without creating any changes.

8. Opcodes
• An opcode is a collection of bits that represents
the basic operations including add, subtract,
multiply, complement, and shift. The total
number of operations provided through the
computer determines the number of bits needed
for the opcode.
• The minimum bits accessible to the opcode
should be n for 2n operations. These operations
are implemented on information that is saved in
processor registers or memory.

9. Address
• The address is represented as the location where a
specific instruction is constructed in the memory. The
address bits of an instruction code is used as an
operand and not as an address.
• In such methods, the instruction has an immediate
operand. If the second part has an address, the
instruction is referred to have a direct address.
• There is another possibility in the second part including
the address of the operand. This is referred to as an
indirect address. In the instruction code, one bit can
signify if the direct or indirect address is executed.

10. The figure shows a diagram showing
direct and indirect addresses

11. Computer Instructions
• Computer instructions are a set of machine
language instructions that a particular processor
understands and executes. A computer performs
tasks on the basis of the instruction provided.
• An instruction comprises of groups called fields.
These fields include:
• The Operation code (Opcode) field which specifies
the operation to be performed.
• The Address field which contains the location of
the operand, i.e., register or memory location.
• The Mode field which specifies how the operand
will be located.

12. • A basic computer has three instruction code
formats which are:
• Memory - reference instruction
• Register - reference instruction
• Input-Output instruction

13. Memory - reference instruction
• In Memory-reference instruction, 12 bits of
memory is used to specify an address and one
bit to specify the addressing mode 'I'.

14. Register Reference Instruction
• The Register-reference instructions are
represented by the Opcode 111 with a 0 in the
leftmost bit (bit 15) of the instruction.
• A Register-reference instruction specifies an
operation on or a test of the AC (Accumulator)
register.

15. Input-Output instruction
• Just like the Register-reference instruction, an Input-
Output instruction does not need a reference to
memory and is recognized by the operation code 111
with a 1 in the leftmost bit of the instruction. The
remaining 12 bits are used to specify the type of the
input-output operation or test performed.

16. Basic Computer Instructions

17. Instruction Cycle
• A program residing in the memory unit of a computer
consists of a sequence of instructions. These instructions
are executed by the processor by going through a cycle for
each instruction.
• In a basic computer, each instruction cycle consists of the
following phases:
• Fetch instruction from memory.
• Decode the instruction.
• Read the effective address from memory.
• Execute the instruction.

18. Instruction Cycle

19. Instruction Cycle
• Fetch and Decode:- Initially, the program counter
PC is loaded with the address of the first
instruction in the program.
• The sequence counter SC is cleared to 0,
providing a decoded timing signal T0.
• After each clock pulse, SC is incremented by one,
so that the timing signals go through a sequence
T0, T1, T2, and so on.
• The microoperations for the fetch and decode
phases can be specified by the following register
transfer statements.

20. Instruction Cycle
• Since only AR is connected to the address inputs of memory, it
is necessary to transfer the address from PC to AR during the
clock transition associated with timing signal T0
• The instruction read from memory is then placed in the
instruction register IR with the clock transition associated with
timing signal T1
• At the same time, PC is incremented by one to prepare it for
the address of the next instruction in the program. At time T2,
the operation code in IR is decoded, the indirect bit is
transferred to flip-flop I, and the address part of the instruction
is transferred to AR .
• Note that SC is incremented after each clock pulse to produce
the sequence To, T1, and T2

21. Instruction cycle flowchart

22. flowchart
• Determine the Type of Instruction:-The timing signal that is active after
the decoding is T3
• During time T3 the control unit determines the type of instruction that
was just read from memory.
• Decoder output D7 is equal to 1 if the operation code is equal to binary
111.
• If D7 = 1 and I = 1, then execute the input output instruction .
• If D7 = 1 and I = 0, then execute the register reference instruction .
• If D7= 0, the operation code must be one of the other seven values 000
through 110, specifying a memory-reference
• instruction.
• If D7 = 0 and I = 1, we have a memory reference instruction with an
indirect address access .
• If D7 = 0 and I = 0, we have a memory reference instruction with an direct
address access.

23. Instruction Formats
• Operations specified by computer instructions are
executed on some data stored in memory or processor
registers.
• Operands residing in memory are specified by their
memory address.
• Operands residing in processor registers are specified
with a register address.
• Thus a CPU with 16 processor registers R0 through R15
will have a register address field of four bits.
• The binary number 0101, for example, will designate
register RS.

24. Instruction Format
• Computers may have instructions of several different
lengths containing varying number of addresses.
• The number of address fields in the instruction format
of a computer depends on the internal organization of
its registers.
• Most computers fall into one of three types of CPU
organizations:
• 1. Single accumulator organization.
• 2. General register organization.
• 3. Stack organization.

25. Instruction Format
• An example of an accumulator-type organization instruction.
A D D X where X is the address of the operand.
• The ADD instruction in this case results in the operation AC <--
AC + M [X]. AC is the accumulator register and M [X]
symbolizes the memory word located at address X.
• An example of a general register type of organization was
presented in An example of register organization instruction.
• Thus the instruction for an arithmetic addition may be written
in an assembly language as ADD R 1 , R 2 , R 3 t o denote the
operation R 1 <--- R2 + R 3 .
• The number o f address fields in the instruction can be
reduced from three to two if the destination register is the
same as one of the source registers.

26. Instruction Format
• Thus the instruction A D D R 1 , R 2 would denote the
operation R 1 <--- R 1 + R2.
• Only register addresses for R 1 and R2 need be specified in
this instruction. . The stack-organized instruction .
• Computers with stack organization would have PUSH and
POP instructions which require an address field.
• PUSH X will push the word at address X to the top of the
stack. The stack pointer is updated automatically.
• Operation type instructions do not need an address field in
stack-organized computers. This is because the operation is
performed on the two items that are on top of the stack.
The instruction ADD .

27. Three-Address Instructions
• Computers with three-address instruction formats can use each
address field to specify either a processor register or a memory
operand.
• The program in assembly language that evaluates X = (A + B) *
(C + D) is shown below, together with comments that explain
the register transfer operation of each instruction.
• It is assumed that the computer has two processor registers, R 1
and R2.
• The symbol M [A ] denotes the operand at memory address
symbolized by A .

28. Three-Address Instructions
• The advantage o f the three-address format i s
that i t results i n short programs when
evaluating arithmetic expressions.
• The disadvantage is that the binary-coded
instructions require too many bits to specify
three addresses.

29. Two-Address Instructions
• Two-address instructions are the most
common in commercial computers. Here again
each address field can specify either a
processor register or a memory word. The
program to evaluate X = (A + B) * (C + D) is as
follows

32. RISC Instructions
• A reduced instruction set computer (RISC). The instruction
set of a typical RISC processor is restricted to the use of
load and store instructions when communicating between
memory and CPU.
• All other instructions are executed within the registers of
the CPU without referring to memory.
• A program for a RISC-type CPU consists of LOAD and STORE
instructions that have one memory and one register
address, and computational-type instructions that have
three addresses with all three specifying processor
registers.
• The following is a program to evaluate X = (A + B) • (C + D).