The document describes the instruction set of the 8085 microprocessor. It contains 13 categories of instructions - data transfer, arithmetic, logical, branching, and control instructions. The data transfer instructions include MOV, MVI, LDA, STA, etc. The arithmetic instructions perform operations like addition, subtraction, increment, decrement. Some examples of instructions and their operations are provided.
Intel 8085 is an 8-bit microprocessor. It handles 8-bit data at a time. One byte consists of 8-bits.A memory location for Intel 8085 microprocessor is designed to accumulate 8-bit data. If 16-bit data are to be stored, they are stored in consecutive memory locations. The address of memory location is 0f 16-bit i.e. 2 bytes. In this slide we have discussed about the various instructions set of INTEL 8085 micrpoprocessor.
Data transfer instruction set of 8085 micro processorvishalgohel12195
Data transfer instruction set of 8085 micro processor
WHAT IS INSTRUCTION?
CLASSIFICATION OF INSTRUCTION.
DATA TRANSFER INSTRUCTION.
EXAMPLES
PROGRAMME OF DATA TRANFER INSTRUCTION
Logical instruction of 8085
Instruction Set of 8085
Classification of Instruction Set
Logical Instructions
AND, OR, XOR
Logical Instructions
Summary Logical Group
Shift and Rotate Instructions
Shift and Rotate Applications
Multiplication and Division Instructions
Extended Addition and Subtraction
ASCII and Packed Decimal Arithmetic
Intel 8085 is an 8-bit microprocessor. It handles 8-bit data at a time. One byte consists of 8-bits.A memory location for Intel 8085 microprocessor is designed to accumulate 8-bit data. If 16-bit data are to be stored, they are stored in consecutive memory locations. The address of memory location is 0f 16-bit i.e. 2 bytes. In this slide we have discussed about the various instructions set of INTEL 8085 micrpoprocessor.
Data transfer instruction set of 8085 micro processorvishalgohel12195
Data transfer instruction set of 8085 micro processor
WHAT IS INSTRUCTION?
CLASSIFICATION OF INSTRUCTION.
DATA TRANSFER INSTRUCTION.
EXAMPLES
PROGRAMME OF DATA TRANFER INSTRUCTION
Logical instruction of 8085
Instruction Set of 8085
Classification of Instruction Set
Logical Instructions
AND, OR, XOR
Logical Instructions
Summary Logical Group
Shift and Rotate Instructions
Shift and Rotate Applications
Multiplication and Division Instructions
Extended Addition and Subtraction
ASCII and Packed Decimal Arithmetic
Dev Dives: Train smarter, not harder – active learning and UiPath LLMs for do...UiPathCommunity
💥 Speed, accuracy, and scaling – discover the superpowers of GenAI in action with UiPath Document Understanding and Communications Mining™:
See how to accelerate model training and optimize model performance with active learning
Learn about the latest enhancements to out-of-the-box document processing – with little to no training required
Get an exclusive demo of the new family of UiPath LLMs – GenAI models specialized for processing different types of documents and messages
This is a hands-on session specifically designed for automation developers and AI enthusiasts seeking to enhance their knowledge in leveraging the latest intelligent document processing capabilities offered by UiPath.
Speakers:
👨🏫 Andras Palfi, Senior Product Manager, UiPath
👩🏫 Lenka Dulovicova, Product Program Manager, UiPath
State of ICS and IoT Cyber Threat Landscape Report 2024 previewPrayukth K V
The IoT and OT threat landscape report has been prepared by the Threat Research Team at Sectrio using data from Sectrio, cyber threat intelligence farming facilities spread across over 85 cities around the world. In addition, Sectrio also runs AI-based advanced threat and payload engagement facilities that serve as sinks to attract and engage sophisticated threat actors, and newer malware including new variants and latent threats that are at an earlier stage of development.
The latest edition of the OT/ICS and IoT security Threat Landscape Report 2024 also covers:
State of global ICS asset and network exposure
Sectoral targets and attacks as well as the cost of ransom
Global APT activity, AI usage, actor and tactic profiles, and implications
Rise in volumes of AI-powered cyberattacks
Major cyber events in 2024
Malware and malicious payload trends
Cyberattack types and targets
Vulnerability exploit attempts on CVEs
Attacks on counties – USA
Expansion of bot farms – how, where, and why
In-depth analysis of the cyber threat landscape across North America, South America, Europe, APAC, and the Middle East
Why are attacks on smart factories rising?
Cyber risk predictions
Axis of attacks – Europe
Systemic attacks in the Middle East
Download the full report from here:
https://sectrio.com/resources/ot-threat-landscape-reports/sectrio-releases-ot-ics-and-iot-security-threat-landscape-report-2024/
DevOps and Testing slides at DASA ConnectKari Kakkonen
My and Rik Marselis slides at 30.5.2024 DASA Connect conference. We discuss about what is testing, then what is agile testing and finally what is Testing in DevOps. Finally we had lovely workshop with the participants trying to find out different ways to think about quality and testing in different parts of the DevOps infinity loop.
Epistemic Interaction - tuning interfaces to provide information for AI supportAlan Dix
Paper presented at SYNERGY workshop at AVI 2024, Genoa, Italy. 3rd June 2024
https://alandix.com/academic/papers/synergy2024-epistemic/
As machine learning integrates deeper into human-computer interactions, the concept of epistemic interaction emerges, aiming to refine these interactions to enhance system adaptability. This approach encourages minor, intentional adjustments in user behaviour to enrich the data available for system learning. This paper introduces epistemic interaction within the context of human-system communication, illustrating how deliberate interaction design can improve system understanding and adaptation. Through concrete examples, we demonstrate the potential of epistemic interaction to significantly advance human-computer interaction by leveraging intuitive human communication strategies to inform system design and functionality, offering a novel pathway for enriching user-system engagements.
GraphRAG is All You need? LLM & Knowledge GraphGuy Korland
Guy Korland, CEO and Co-founder of FalkorDB, will review two articles on the integration of language models with knowledge graphs.
1. Unifying Large Language Models and Knowledge Graphs: A Roadmap.
https://arxiv.org/abs/2306.08302
2. Microsoft Research's GraphRAG paper and a review paper on various uses of knowledge graphs:
https://www.microsoft.com/en-us/research/blog/graphrag-unlocking-llm-discovery-on-narrative-private-data/
Kubernetes & AI - Beauty and the Beast !?! @KCD Istanbul 2024Tobias Schneck
As AI technology is pushing into IT I was wondering myself, as an “infrastructure container kubernetes guy”, how get this fancy AI technology get managed from an infrastructure operational view? Is it possible to apply our lovely cloud native principals as well? What benefit’s both technologies could bring to each other?
Let me take this questions and provide you a short journey through existing deployment models and use cases for AI software. On practical examples, we discuss what cloud/on-premise strategy we may need for applying it to our own infrastructure to get it to work from an enterprise perspective. I want to give an overview about infrastructure requirements and technologies, what could be beneficial or limiting your AI use cases in an enterprise environment. An interactive Demo will give you some insides, what approaches I got already working for real.
Neuro-symbolic is not enough, we need neuro-*semantic*Frank van Harmelen
Neuro-symbolic (NeSy) AI is on the rise. However, simply machine learning on just any symbolic structure is not sufficient to really harvest the gains of NeSy. These will only be gained when the symbolic structures have an actual semantics. I give an operational definition of semantics as “predictable inference”.
All of this illustrated with link prediction over knowledge graphs, but the argument is general.
Securing your Kubernetes cluster_ a step-by-step guide to success !KatiaHIMEUR1
Today, after several years of existence, an extremely active community and an ultra-dynamic ecosystem, Kubernetes has established itself as the de facto standard in container orchestration. Thanks to a wide range of managed services, it has never been so easy to set up a ready-to-use Kubernetes cluster.
However, this ease of use means that the subject of security in Kubernetes is often left for later, or even neglected. This exposes companies to significant risks.
In this talk, I'll show you step-by-step how to secure your Kubernetes cluster for greater peace of mind and reliability.
Smart TV Buyer Insights Survey 2024 by 91mobiles.pdf91mobiles
91mobiles recently conducted a Smart TV Buyer Insights Survey in which we asked over 3,000 respondents about the TV they own, aspects they look at on a new TV, and their TV buying preferences.
UiPath Test Automation using UiPath Test Suite series, part 4DianaGray10
Welcome to UiPath Test Automation using UiPath Test Suite series part 4. In this session, we will cover Test Manager overview along with SAP heatmap.
The UiPath Test Manager overview with SAP heatmap webinar offers a concise yet comprehensive exploration of the role of a Test Manager within SAP environments, coupled with the utilization of heatmaps for effective testing strategies.
Participants will gain insights into the responsibilities, challenges, and best practices associated with test management in SAP projects. Additionally, the webinar delves into the significance of heatmaps as a visual aid for identifying testing priorities, areas of risk, and resource allocation within SAP landscapes. Through this session, attendees can expect to enhance their understanding of test management principles while learning practical approaches to optimize testing processes in SAP environments using heatmap visualization techniques
What will you get from this session?
1. Insights into SAP testing best practices
2. Heatmap utilization for testing
3. Optimization of testing processes
4. Demo
Topics covered:
Execution from the test manager
Orchestrator execution result
Defect reporting
SAP heatmap example with demo
Speaker:
Deepak Rai, Automation Practice Lead, Boundaryless Group and UiPath MVP
Connector Corner: Automate dynamic content and events by pushing a buttonDianaGray10
Here is something new! In our next Connector Corner webinar, we will demonstrate how you can use a single workflow to:
Create a campaign using Mailchimp with merge tags/fields
Send an interactive Slack channel message (using buttons)
Have the message received by managers and peers along with a test email for review
But there’s more:
In a second workflow supporting the same use case, you’ll see:
Your campaign sent to target colleagues for approval
If the “Approve” button is clicked, a Jira/Zendesk ticket is created for the marketing design team
But—if the “Reject” button is pushed, colleagues will be alerted via Slack message
Join us to learn more about this new, human-in-the-loop capability, brought to you by Integration Service connectors.
And...
Speakers:
Akshay Agnihotri, Product Manager
Charlie Greenberg, Host
Transcript: Selling digital books in 2024: Insights from industry leaders - T...BookNet Canada
The publishing industry has been selling digital audiobooks and ebooks for over a decade and has found its groove. What’s changed? What has stayed the same? Where do we go from here? Join a group of leading sales peers from across the industry for a conversation about the lessons learned since the popularization of digital books, best practices, digital book supply chain management, and more.
Link to video recording: https://bnctechforum.ca/sessions/selling-digital-books-in-2024-insights-from-industry-leaders/
Presented by BookNet Canada on May 28, 2024, with support from the Department of Canadian Heritage.
3. What is Instruction ?????
• An instruction is a binary pattern designed
inside a microprocessor to perform a specific
function.
• 8085 has 246 instructions.
• Each instruction is represented by an 8-bit
binary value.
4. Classification Of Instruction Set
• There are 5 Types,
• (1) Data Transfer Instruction,
• (2) Arithmetic Instructions,
• (3) Logical Instructions,
• (4) Branching Instructions,
• (5) Control Instructions,
5. (1) Data Transfer Instructions
• MOV Rd, Rs
• MOV M, Rs
• MOV Rd, M
• This instruction copies the contents of the
source register into the destination register.
• The contents of the source register are not
altered.
• Example: MOV B,A or MOV M,B or MOV C,M
6. BEFORE EXECUTION AFTER EXECUTION
A 20 B MOV B,A A 20 B 20
A F A F
B 30 C B 30 C
D E
MOV M,B D E
H 20 L 50 H 20 L 50 30
A F A F
B C B C 40
D E
MOV C,M
D E
H 20 L 50 40 H 20 L 50 40
7. (2) Data Transfer Instructions
• MVI R, Data(8-bit)
• MVI M, Data(8-bit)
• The 8-bit immediate data is stored in the
destination register (R) or memory (M), R is
general purpose 8 bit register such as
A,B,C,D,E,H and L.
• Example: MVI B, 60H or MVI M, 40H
8. BEFORE EXECUTION AFTER EXECUTION
A F A F
B C B 60 C
D E
MVI B,60H D E
H L H L
BEFORE EXECUTION AFTER EXECUTION
204FH 204FH
40
HL=2050H HL=2050H
MVI M,40H
2051H 2051H
9. (3) Data Transfer Instructions
• LDA 16-bit address
• The contents of a memory location, specified
by a 16-bit address in the operand, are
copied to the accumulator (A).
• The contents of the source are not altered.
• Example: LDA 2000H
10. BEFORE EXECUTION AFTER EXECUTION
A A 30
30 LDA 2000H 30
2000H 2000H
11. (4) Data Transfer Instructions
• LDAX Register Pair
• Load accumulator (A) with the contents of
memory location whose address is specified
by BC or DE or register pair.
• The contents of either the register pair or the
memory location are not altered.
• Example: LDAX D
12. BEFORE EXECUTION AFTER EXECUTION
A F A 80 F
B C 80 B C 80
2030H 2030H
LDAX D
D 20 E 30 D 20 E 30
13. (5) Data Transfer Instructions
• STA 16-bit address
• The contents of accumulator are copied into
the memory location i.e. address specified by
the operand in the instruction.
• Example: STA 2000 H
14. BEFORE EXECUTION AFTER EXECUTION
A 50 A 50
50
2000H STA 2000H 2000H
15. (6) Data Transfer Instructions
• STAX Register Pair
• Store the contents of accumulator (A) into
the memory location whose address is
specified by BC Or DE register pair.
• Example: STAX B
16. BEFORE EXECUTION AFTER EXECUTION
A 50 F A 50 F
B 10 C 20 B 10 C 20 50
1020H 1020H
D E
STAX B D E
17. (7) Data Transfer Instructions
• SHLD 16-bit address
• Store H-L register pair in memory.
• The contents of register L are stored into
memory location specified by the 16-bit
address.
• The contents of register H are stored into the
next memory location.
• Example: SHLD 2500 H
18. BEFORE EXECUTION AFTER EXECUTION
H 30 L 60 H 30 L 60
60
204FH 204FH
30
2500H SHLD 2500H 2500H
2502H 2502H
19. (8) Data Transfer Instructions
• XCHG
• The contents of register H are exchanged
with the contents of register D.
• The contents of register L are exchanged with
the contents of register E.
• Example: XCHG
20. BEFORE EXECUTION AFTER EXECUTION
D 20 E 40 D 70 E 80
H 70 L 80 XCHG H 20 L 40
21. (9) Data Transfer Instructions
• SPHL
• Move data from H-L pair to the Stack Pointer
(SP)
• This instruction loads the contents of H-L pair
into SP.
• Example: SPHL
23. (10) Data Transfer Instructions
• XTHL
• Exchange H–L with top of stack
• The contents of L register are exchanged with
the location pointed out by the contents of
the SP.
• The contents of H register are exchanged
with the next location (SP + 1).
• Example: XTHL
24. L=SP
H=(SP+1)
BEFORE EXECUTION AFTER EXECUTION
SP 2700 50 SP 2700 40
2700H 2700H
H L H L
30 40 60 60 50 30
2701H 2701H
XTHL
2702H 2702H
25. (11) Data Transfer Instructions
• PCHL
• Load program counter with H-L contents
• The contents of registers H and L are copied into
the program counter (PC).
• The contents of H are placed as the high-order
byte and the contents of L as the low-order byte.
• Example: PCHL
26. BEFORE EXECUTION AFTER EXECUTION
PC PC 6000
H
60
L
00
PCHL H
60
L
00
27. (12) Data Transfer Instructions
• IN 8-bit port address
• Copy data to accumulator from a port with 8-
bit address.
• The contents of I/O port are copied into
accumulator.
• Example: IN 80 H
29. (13) Data Transfer Instructions
• OUT 8-bit port address
• Copy data from accumulator to a port with 8-
bit address
• The contents of accumulator are copied into
the I/O port.
• Example: OUT 50 H
32. (1) Arithematic Instructions
• ADD R
• ADD M
• The contents of register or memory are added to
the contents of accumulator.
• The result is stored in accumulator.
• If the operand is memory location, its address is
specified by H-L pair.
• Example: ADD C or ADD M
33. BEFORE EXECUTION AFTER EXECUTION
A 20 A 50
B C 30 B C 30
D E ADD C D E
H L
H L
A=A+R
BEFORE EXECUTION AFTER EXECUTION
A 20 ADD M A 30
B C B C
D E
A=A+M D E
H 20 L 50 10 H 20 L 50 10
2050 2050
34. (2) Arithematic Instructions
• ADC R
• ADC M
• The contents of register or memory and Carry Flag
(CY) are added to the contents of accumulator.
• The result is stored in accumulator.
• If the operand is memory location, its address is
specified by H-L pair. All flags are modified to reflect
the result of the addition.
• Example: ADC C or ADC M
35. BEFORE EXECUTION AFTER EXECUTION
CY 1 CY 0
A 50 A 71
B C 20 B C 20
ADC C
D E D E
A=A+R+CY
H L H L
BEFORE EXECUTION AFTER EXECUTION
CY 1 CY 0
2050H 30 ADC M 2050H 30
A 20 A 51
A=A+M+CY
H 20 L 50 H 20 L 50
36. (3) Arithematic Instructions
• ADI 8-bit data
• The 8-bit data is added to the contents of
accumulator.
• The result is stored in accumulator.
• Example: ADI 10 H
38. (4) Arithematic Instructions
• ACI 8-bit data
• The 8-bit data and the Carry Flag (CY) are
added to the contents of accumulator.
• The result is stored in accumulator.
• Example: ACI 20 H
39. BEFORE EXECUTION AFTER EXECUTION
CY 1 ACI 20H CY 0
A 30
A=A+DATA A 51
(8)+CY
40. (5) Arithematic Instructions
• DAD Register pair
• The 16-bit contents of the register pair are
added to the contents of H-L pair.
• The result is stored in H-L pair.
• If the result is larger than 16 bits, then CY is
set.
• Example: DAD D
41. BEFORE EXECUTION AFTER EXECUTION
CY 0 CY 0
SP SP
B
D 10
C
E 20
DAD D B
D 10
C
E 20
H 20 L 50 HL=HL+R H 30 L 70
42. (6) Arithematic Instructions
• SUB R
• SUB M
• The contents of the register or memory location are
subtracted from the contents of the accumulator.
• The result is stored in accumulator.
• If the operand is memory location, its address is
specified by H-L pair.
• Example: SUB B or SUB M
43. BEFORE EXECUTION AFTER EXECUTION
A 50 A 20
B 30 C B 30 C
D E
SUB B D E
H L A=A-R H L
BEFORE EXECUTION AFTER EXECUTION
10
A 50 1020H A 40 1020H 10
H L
SUB M H L
10 20
A=A-M 10 20
44. (7) Arithematic Instructions
• SBB R
• SBB M
• The contents of the register or memory location and
Borrow Flag (i.e.CY) are subtracted from the contents of the
accumulator.
• The result is stored in accumulator.
• If the operand is memory location, its address is specified
by H-L pair.
• Example: SBB C or SBB M
45. BEFORE EXECUTION AFTER EXECUTION
CY 1 CY 0
A 40 A 19
B C 20
SBB C B C 20
D E A=A-R-CY D E
H L H L
BEFORE EXECUTION AFTER EXECUTION
CY 1 CY 0
10 10
A 50 2050H A 39 2050H
SBB M
H L H L
20 50 A=A-M-CY 20 50
46. (8) Arithematic Instructions
• SUI 8-bit data
• OPERATION: A=A-DATA(8)
• The 8-bit immediate data is subtracted from
the contents of the accumulator.
• The result is stored in accumulator.
• Example: SUI 45 H
47. (9) Arithematic Instructions
• SBI 8-bit data
• The 8-bit data and the Borrow Flag (i.e. CY) is
subtracted from the contents of the
accumulator.
• The result is stored in accumulator.
• Example: SBI 20 H
48. BEFORE EXECUTION AFTER EXECUTION
CY 1 CY 0
A 50
SBI 20H A 29
A=A-DATA(8)-CY
49. (10) Arithematic Instructions
• INR R
• INR M
• The contents of register or memory location are
incremented by 1.
• The result is stored in the same place.
• If the operand is a memory location, its address
is specified by the contents of H-L pair.
• Example: INR B or INR M
50. BEFORE EXECUTION AFTER EXECUTION
A A
B 10 C INR B B 11 C
D
H
E
L
R=R+1 D
H
E
L
BEFORE EXECUTION AFTER EXECUTION
H L 30 H L 31
2050H 2050H
20 50
INR M 20 50
M=M+1
51. (11) Arithematic Instructions
• INX Rp
• The contents of register pair are incremented
by 1.
• The result is stored in the same place.
• Example: INX H
52. BEFORE EXECUTION AFTER EXECUTION
SP SP
B C B C
D E INX H D E
H 10 L 20 H 11 L 21
RP=RP+1
53. (12) Arithematic Instructions
• DCR R
• DCR M
• The contents of register or memory location are
decremented by 1.
• The result is stored in the same place.
• If the operand is a memory location, its address
is specified by the contents of H-L pair.
• Example: DCR E or DCR M
54. BEFORE EXECUTION AFTER EXECUTION
A A
B C B C
D E 20
DCR E D E 19
H L R=R-1 H L
BEFORE EXECUTION AFTER EXECUTION
H L
H L 21 20
20 50 2050H
2050H
20 50 DCR M
M=M-1
55. (13) Arithematic Instructions
• DCX Rp
• The contents of register pair are decremented by
1.
• The result is stored in the same place.
• Example: DCX D
56. BEFORE EXECUTION AFTER EXECUTION
SP SP
B C B C
D 10 E 20 DCX D D 10 E 19
H L H L
RP=RP-1
57. (1) Logical Instructions
• ANA R
• ANA M
• AND specified data in register or memory with
accumulator.
• Store the result in accumulator (A).
• Example: ANA B, ANA M
58. BEFORE EXECUTION 1010 1010=AAH AFTER EXECUTION
0000 1111=0FH
CY AC CY 0 AC 1
0000 1010=0AH
A AA A 0A
B 10
0F C ANA B B 0F C
D E A=A and R D E
H L H L
BEFORE EXECUTION AFTER EXECUTION
0101 0101=55H
CY AC 1011 0011=B3H CY 0 AC 1
B3 0001 0001=11H B3
A 55 2050H A 11 2050H
H 20 L 50 ANA M H 20 L 50
A=A and M
59. (2) Logical Instructions
• ANI 8-bit data
• AND 8-bit data with accumulator (A).
• Store the result in accumulator (A)
• Example: ANI 3FH
60. BEFORE EXECUTION AFTER EXECUTION
1011 0011=B3H
0011 1111=3FH
0011 0011=33H
CY AC CY 0 AC 1
ANI 3FH
A B3 A=A and DATA(8) A 33
61. (3) Logical Instructions
• XRA Register (8-bit)
• XOR specified register with accumulator.
• Store the result in accumulator.
• Example: XRA C
62. 1010 1010=AAH
BEFORE EXECUTION 0010 1101=2DH AFTER EXECUTION
1000 0111=87H
CY AC CY 0 AC 0
A AA A 87
B 10 C 2D B C 2D
D E
XRA C D E
H L A=A xor R H L
63. (4) Logical Instructions
• XRA M
• XOR data in memory (memory location
pointed by H-L pair) with Accumulator.
• Store the result in Accumulator.
• Example: XRA M
64. 0101 0101=55H
BEFORE EXECUTION 1011 0011=B3H AFTER EXECUTION
1110 0110=E6H
CY AC CY 0 AC 0
B3 XRA M B3
2050H A E6 2050H
A 55
A=A xor M
H 20 L 50 H 20 L 50
65. (5) Logical Instructions
• XRI 8-bit data
• XOR 8-bit immediate data with accumulator (A).
• Store the result in accumulator.
• Example: XRI 39H
66. 1011 0011=B3H
0011 1001=39H
BEFORE EXECUTION 1000 1010=8AH AFTER EXECUTION
CY AC CY 0 AC 0
XRI 39H
A B3 A=A xor DATA(8) A 8A
67. (6) Logical Instructions
• ORA Register
• OR specified register with accumulator (A).
• Store the result in accumulator.
• Example: ORA B
68. 1010 1010=AAH
0001 0010=12H
BEFORE EXECUTION AFTER EXECUTION
1011 1010=BAH
CY AC CY 0 AC 0
ORA B
A=A or R
A AA A BA
B 12 C B 12 C
D E D E
H L H L
69. (7) Logical Instructions
• ORA M
• OR specified register with accumulator (A).
• Store the result in accumulator.
• Example: ORA M
70. 0101 0101=55H
1011 0011=B3H
BEFORE EXECUTION AFTER EXECUTION
1111 0111=F7H
CY AC CY 0 AC 0
ORA M
A=A or M
B3 B3
A 55 2050H A F7 2050H
H 20 L 50 H 20 L 50
71. (8) Logical Instructions
• ORI 8-bit data
• OR 8-bit data with accumulator (A).
• Store the result in accumulator.
• Example: ORI 08H
72. 1011 0011=B3H
0000 1000=08H
BEFORE EXECUTION 1011 1011=BBH AFTER EXECUTION
CY AC CY 0 AC 0
ORI 08H
A B3 A=A or DATA(8) A BB
73. (9) Logical Instructions
• CMP Register
• CMP M
• Compare specified data in register or memory
with accumulator (A).
• Store the result in accumulator.
• Example: CMP D or CMP M
74. BEFORE EXECUTION A>R: CY=0,Z=0 AFTER EXECUTION
A=R: CY=0,Z=1
CY Z A<R: CY=1,Z=0 CY 0 Z 0
A B8 A B8
B 10 C CMP D B C
D B9 E A-R D B9 E
H L H L
BEFORE EXECUTION AFTER EXECUTION
A>M: CY=0,Z=0
A=M: CY=0,Z=1
A<M: CY=1,Z=0
CY Z CY 0 Z 1
B8 B8
A B8 2050H A B8 2050H
CMP M
H 20 L 50 A-M H 20 L 50
75. (10) Logical Instructions
• CPI 8-bit data
• Compare 8-bit immediate data with
accumulator (A).
• Store the result in accumulator.
• Example: CPI 30H
76. A>DATA: CY=0,Z=0
A=DATA: CY=0,Z=1
BEFORE EXECUTION A<DATA: CY=1,Z=0 AFTER EXECUTION
CY Z CY 0 AC 0
CPI 30H
A BA
A-DATA A BA
1011 1010=BAH
82. (14) Logical Instructions
• RLC
• Rotate accumulator left
• Each binary bit of the accumulator is rotated left
by one position.
• Bit D7 is placed in the position of D0 as well as
in the Carry flag.
• CY is modified according to bit D7.
• Example: RLC.
84. (15) Logical Instructions
• RRC
• Rotate accumulator right
• Each binary bit of the accumulator is rotated right by
one
• position.
• Bit D0 is placed in the position of D7 as well as in the
Carry flag.
• CY is modified according to bit D0.
• Example: RRC.
86. (16) Logical Instructions
• RAL
• Rotate accumulator left through carry
• Each binary bit of the accumulator is rotated left
by one position through the Carry flag.
• Bit D7 is placed in the Carry flag, and the Carry
flag is placed in the least significant position D0.
• CY is modified according to bit D7.
• Example: RAL.
88. (17) Logical Instructions
• RAR
• Rotate accumulator right through carry
• Each binary bit of the accumulator is rotated left
by one position through the Carry flag.
• Bit D7 is placed in the Carry flag, and the Carry
flag is placed in the least significant position D0.
• CY is modified according to bit D7.
• Example: RAR
90. Concept of Subroutine
• In 8085 microprocessor a subroutine is a
separate program written aside from main
program ,this program is basically the
program which requires to be executed
several times in the main program.
• The microprocessor can call subroutine any
time using CALL instruction. after the
subroutine is executed the subroutine hands
over the program to main program using RET
instruction.
91. Branching Instructions
• The branch group instructions allows the
microprocessor to change the sequence of
program either conditionally or under certain
test conditions. The group includes,
• (1) Jump instructions,
• (2) Call and Return instructions,
• (3) Restart instructions,
92. (1) Branching Instructions
• JUMP ADDRESS
• BEFORE EXECUTION AFTER EXECUTION
PC JMP 2000H PC 2000
• Jump unconditionally to the address.
• The instruction loads the PC with the address
given within the instruction and resumes the
program execution from specified location.
• Example: JMP 200H
93. Conditional Jumps
Instruction Code Decription Condition For Jump
JC Jump on carry CY=1
JNC Jump on not carry CY=0
JP Jump on positive S=0
JM Jump on minus S=1
JPE Jump on parity even P=1
JPO Jump on parity odd P=0
JZ Jump on zero Z=1
JNZ Jump on not zero Z=0
94. (2) Branching Instructions
• CALL address
• Call unconditionally a subroutine whose
starting address given within the
instruction and used to transfer program
control to a subprogram or subroutine.
• Example: CALL 2000H
95. Conditional Calls
Instruction Code Description Condition for CALL
CC Call on carry CY=1
CNC Call on not carry CY=0
CP Call on positive S=0
CM Call on minus S=1
CPE Call on parity even P=1
CPO Call on parity odd P=0
CZ Call on zero Z=1
CNZ Call on not zero Z=0
96. (3) Branching Instructions
• RET
• Return from the subroutine unconditionally.
• This instruction takes return address from the
stack and loads the program counter with
this address.
• Example: RET
97. BEFORE EXECUTION AFTER EXECUTION
SP 27FD 00 SP 27FF 00
27FDH 27FDH
PC PC 6200
27FEH 62 27FEH 62
RET
27FFH 27FFH
98. (4) Branching Instructions
• RST n
• Restart n (0 to 7)
• This instruction transfers the program control
to a specific memory address. The processor
multiplies the RST number by 8 to calculate
the vector address.
• Example: RST 6
99. BEFORE EXECUTION AFTER EXECUTION
SP-1
SP 3000 SP 2999 01
2FFEH 2FFEH
PC 2000 PC 0030
2FFFH 20
RST 6 2FFFH
3000H 3000H
ADDRESS OF THE NEXT INSTRUCTION IS 2001H
101. (1) Control Instructions
• NOP
• No operation
• No operation is performed.
• The instruction is fetched and decoded but no
operation is executed.
• Example: NOP
102. (2) Control Instructions
• HLT
• Halt
• The CPU finishes executing the current
instruction and halts any further execution.
• An interrupt or reset is necessary to exit from
the halt state.
• Example: HLT
103. (3) Control Instructions
• RIM
• Read Interrupt Mask
• This is a multipurpose instruction used to read the
status of interrupts 7.5, 6.5, 5.5 and read serial data
input bit.
• The instruction loads eight bits in the accumulator
with the following interpretations.
• Example: RIM
105. • SIM
• Set Interrupt Mask
• This is a multipurpose instruction and used to
implement the 8085 interrupts 7.5, 6.5, 5.5, and
serial data output.
• The instruction interprets the accumulator
contents as follows.
• Example: SIM