Overview of microprocessor part 3

1. 1. Programming with 8085
2. Instruction set of 8085

2. Assembly Language,
Machine Language
Machine Dependent
Low Level Language
C, C++, JAVA
Machine Independent
High Level Language
Programming with 8085

3. Internal Structure of 8085

4.  A is Accumulator – used to perform
arithmetic and logical operations
 F is Flag register – not directly accessible
 B, C, D, E, H, L are general purpose
registers
 B-C, D-E, H-L can be used as 16-bit
register
 SP is Stack Pointer
 PC is Program Counter used by µP itself. It
stores the 16-bit address of the next
memory register to be executed
A Flag
B C
D E
H L
SP
PC

5. Flag Register
S Z AC P CY
= 1
NEGATIVE
= 0
POSITIVE
S = 1
RESULT IS
ZERO
= 0
RESULT IS
NOT ZERO
Z =1
EVEN NO. OF
1’S
=0
ODD NO. OF
1’S
P
= 1
CARRY
GENERATED BY
D3
= 0
OTHERWISE
AC = 1
CARRY
GENERATED
= 0
CARRY NOT
GENERATED
CY
D0

6. OPCODE: Operation to be performed
OPERAND: On which the operation to be
performed
OPCODE OPERAND
MOV A, B
Each instruction has two parts
Instruction Format

7. Number of registers required to store an instruction in
memory
HLT 76 1 Byte
MVI B, 37H 06 37 2 Byte
STA 3015H 32 15 30 3 Byte
Instruction Byte Size

8. T State: Time period of the system Clock. (1 / frequency)
Clock: A Clock is a square wave generator which is used to
synchronize various devices in the microprocessor and in the
system.
Instruction Cycle: Total time to execute a complete instruction
Machine Cycle: an instruction may be divided into several
parts like Opcode fetch, Memory read, Memory write etc.
Time to execute each part is known as Machine Cycle.
Instruction Timing

9. Memory Code
0000 H XX
---- --
---- --
3010 H 3E H
3011 H 35 H
---- --
---- --
FFFF H XX
MVI A, 35H
Steps:
Opcode Fetch (4 T-state)
Place the address 3010H in the address bus
Activate ALE signal
Activate Read signal
Copy Opcode 3E H in the data bus
Memory Read (3 T-state)
Place the address 3011H in the address bus
Activate ALE signal
Activate Read signal
Copy Data 35 H in the data bus
Timing Diagram

10. Memory Code
3010 H 3E H
3011 H 35 H
MVI A, 35 H
Timing
Diagram

11. Memory Code
0000 H XX
---- --
---- --
3010 H 21 H
3011 H 35 H
3012 H 20 H
---- --
FFFF H XX
LXI H 2035H
Steps:
Opcode Fetch (4 T-state)
 Place the address 3010H in the address bus
 Activate ALE signal
 Activate Read signal
 Copy Opcode 21 H in the data bus
Memory Read (3 T-state)
 Place the address 3011H in the address bus
 Activate ALE signal
 Activate Read signal
 Copy Data 35 H in the data bus
Memory Read (3 T-state)
 Place the address 3012H in the address bus
 Activate ALE signal
 Activate Read signal
 Copy Data 20 H in the data bus
Timing Diagram

13. 8085 Instruction Set

14. The different ways in which a source operand / data is denoted
in an instruction are known as addressing modes.
 Register Addressing
 Data stored in a register and that register is specified in the instruction
 Immediate Addressing
 Data itself is specified in the instruction
 Direct Addressing
 Data stored in memory and that address is specified in the instruction
 Register Indirect Addressing
 Specified register contains the address of the data
 Implicit Addressing
 No data is specified in the instruction
Addressing Mode

15. 1. Data Transfer Operation
2. Arithmetic Operation
3. Logical Operation
4. Branching & machine Control Operation
Types of Instruction

16. • MOV Rd, Rs
Rd Rs
Example:
MOV A,B
MOV C,H
MOV D,C
Addressing Mode: Register
Instruction Size: 1 Byte
Rd: Destination Register
Rs; Source Register

17. • MVI Rd, <8-Bit data>
Rd
Example:
MVI A, 54H
MVI C, 61H
MVI D, 8CH
<8-Bit data>
Addressing Mode: Immediate
Instruction Size: 2 Bytes

18. • LXI Rp, <16-Bit data>
Rp
Example:
LXI H,5004H
LXI B,6021H
LXI D,840CH
<16-Bit data>
Addressing Mode: Immediate
Instruction Size: 3 Bytes
Rp: Register Pair

19. • MVI M, <8 bit data>
• MOV R, M
• MOV M, R
R
MEMORYµP
XX XX
H L
XXXXH
R: Register
M; Memory Register
• Data transfer between microprocessor and a memory register
• Address of the memory register is stored in H-L register pair
Addressing Mode: Immediate / Reg. Indirect
Instruction Size: 2 Bytes / 1 Bytes

20. D
Example:
LXI H,2004H
MOV D, M
MEMORYµP
20 04
42
H L
42H
MEMORY
39H
42H
72H
2003H
2004H
2005H

21. • LDA <16 Bit Address>
• STA <16 Bit Address>
ACC
MemoryµP
ACC
MemoryµP
Addressing Mode: Direct
Instruction Size: 3 Bytes
1600H 2500H
LDA 1600H
STA 2500H

22. Timing Diagram of ‘STA’ instruction
STA 526A H
Memory Code
41FFH 32H
4200H 6AH
4201H 52H

23. • STAX B
• STAX D
• LDAX B
• LDAX D
ACC
Memory
µP
ACC
Memory
µP
B C B C
Addressing Mode: Register Indirect
Instruction Size: 1 Bytes

24. • SHLD <16 Bit Address>
• LHLD <16 Bit Address>
Memory
µP
Memory
µP
1660H 2080H
H L H L
1661H 2081H
Addressing Mode: Direct
Instruction Size: 3 Bytes
SHLD 2080H
LHLD 1660H

25. • XCHG
µP µP
pq rs ab cd
H L H L
Addressing Mode: Register
Instruction Size: 1 Bytes
Exchange the contents of H-L with D-E register pair
ab cd
D E
pq rs
D E

26. • ADD R
• ADD M
• ADI <8-BIT Data>
Acc R Acc
Acc MEMORY
(Address from H-L)
Acc
Acc 8-Bit Data Acc
ADDITION

27. • ADC R
• ADC M
• ACI <8-BIT Data>
Acc R Acc
Acc MEMORY
(Address from H-L)
Acc
Acc 8-Bit Data Acc
CY
CY
CY
ADDITION with CARRY

28. • SUB R
• SUB M
• SUI <8-BIT Data>
Acc R Acc
Acc MEMORY
(Address from H-L)
Acc
Acc 8-Bit Data Acc
SUBTRACTION

29. • SBB R
• SBB M
• SBI <8-BIT Data>
Acc R Acc
Acc MEMORY
(Address from H-L)
Acc
Acc 8-Bit Data Acc
CY
CY
CY
SUBTRACTION with BORROW

30. • DAD Rp
H RpL H L
 LXI H,1800H
 LXI B,1200H
 DAD B
 HLT
H
0018
L B
XXXX
C
H
0018
L B
0012
C
H
002A
L B
0012
C
16 Bit Addition

31. • INR R
• DCR R
• INX Rp
• DCX Rp
R R
R R
Rp Rp
Rp Rp
Increment & Decrement

32. • DAA
Decimal Adjust Accumulator
The DAA instruction is provided to correct the problem associated with BCD
(Binary Coded Decimal) addition
After an Addition instruction
1. If the lower nibble (4 bits) is greater than 9, or if AC=1, add 0110 (6) to the
lower 4 bits
2. If the upper nibble is greater than 9, or if CY=1, add 0110 (6) to the upper
4 bits
Example
MVI A, 29H A = 29 H HEX BCD
29 0010 1001
+ 18 + 0001 1000
41 0100 0001 AC=1
+ 6 + 0110
47 0100 0111
ADI 18H
A = 29H + 18H = 41H
Aux. Carry = 1
DAA A = 41H + 06H = 47H

33. BCD Operation
The binary representation of the digits 0 to 9 is called BCD (Binary Coded Decimal)
Digit BCD
0 0000
1 0001
2 0010
3 0011
4 0100
5 0101
6 0110
7 0111
8 1000
9 1001
Unpacked BCD
In unpacked BCD, the lower 4 bits of the number represent the
BCD number, and the rest of the bits are 0
Ex. 9 = 0000 1001
5 = 0000 0101
Packed BCD
In packed BCD, a single byte has two BCD number in it, one in
the lower 4 bits, and one in the upper 4 bits
Ex. 59 = 0101 1001 (not 0011 1011)

34. Problem Associated with BCD Addition
To correct this problem, the programmer must add 6 (0110) to the low digit:
3FH + 06H = 45H.
BCD addition
17
+ 28
45 (0100 0101)
HEX addition
17
+ 28
3F (0011 1111)
General rule: After addition
1. If the first digit is greater than 9, or if there is a carry generation in first digit
place, add 06H to the result
2. If the second digit is greater than 9, or if there is a carry generation in second
digit place, add 60H to the result

35. • ANA R
• ANA M
• ANI <8-BIT Data>
Acc R/M/DATA Acc
• ORA R
• ORA M
• ORI <8-BIT Data> Acc R/M/DATA Acc
• XRA R
• XRA M
• XRI <8-BIT Data> Acc R/M/DATA Acc
AND Operation
OR Operation
XOR Operation

36. Rotate Operation
• RLC (Rotate Accumulator Left)
• RAL (Rotate Accumulator Left Through Carry)
1 0 1 0 1 1 0 0 0 1 0 1 1 0 0 1
X 1
RLC
CY CY
1 0 1 0 1 1 0 0 0 1 0 1 1 0 0 X
X 1
RAL
CY
CY

37. Rotate Operation
• RRC (Rotate Accumulator Right)
• RAR (Rotate Accumulator Right Through Carry)
1 0 1 0 1 1 0 0 0 1 0 1 0 1 1 0
X 0
RRC
CY CY
0
RAR
CY
1 0 1 0 1 1 0 0
X
CY
X 1 0 1 0 1 1 0

38. Compare
• CMP R
• CMP M
• CPI <8-Bit Number>
Acc R/M/8-Bit No.
1 0
CY Z
0 0
CY Z
0 1
CY Z
When Result
is —ve
When Result
is +ve
When Result
is Zero

39. Complement
• CMA
1’s complement of the content of the Accumulator
• CMC
Complement of the content of the Carry bit

40. Jump Instruction
2000H Instruction 1
2001H Instruction 2
2002H .
2003H .
2004H JMP 200AH
2005H
2006H
2007H .
2008H .
2009H .
200AH .
200BH .
200CH .
200DH .
200EH .

41. Conditional Jump
• JP <16-Bit Address> jump when s = 0
• JM <16-Bit Address> jump when s = 1
• JZ <16-Bit Address> jump when z = 1
• JNZ <16-Bit Address> jump when z = 0
• JPE <16-Bit Address> jump when P = 1
• JPO <16-Bit Address> jump when P = 0
• JC <16-Bit Address> jump when CY = 1
• JNC <16-Bit Address> jump when CY = 0

42. Some Special Instructions
• PCHL
Content of H-L pair are transferred to the program counter
• NOP
No operation. Content of the program counter is
incremented by 1
• HLT
Microprocessor stops program execution until an interrupt