The document discusses the different operating modes of the 80386 microprocessor including real address mode, protected address mode, and virtual address mode. It describes the global descriptor table, local descriptor table, and interrupt descriptor table which define memory segments and interrupts. The 80386 supports virtual addressing, memory management, and protection through descriptor tables, paging enabled by control registers, and segmentation of the virtual address space.

1. 1Submitted by-
Deepak – 101116
Sunil – 101117
Submitted to-
Prof. Rahul Mehta
Prof. Harekrishna Parmar

2. 2
 Three modes of software operation in 80386:
 Real-address mode,
 Protected-address mode and
 Virtual-address mode
 80386 microprocessor comes up in Real Mode
whenever it is RESET.
 PE bit of CR0 is used to switch 80386 into Protected
Mode.
 In this mode 80386 provides an advanced software
architecture supporting memory management, virtual
addressing, paging, protection and multi-tasking.
 Disadvantages:
 More difficult to program
 Much harder to debug, no source-level debugging

3.  GDTR : global descriptor table
 LDTR : local descriptor table
 IDTR : interrupt descriptor table
 TR : task register
 EIP : 32 bits in length
 EFLAGS
 CR0, CR1, CR2, CR3
 DR0-DR7(Debug registers)
 TR6-TR7(Test registers)
3
EIP
CS
DS
SS
ES
FS
GS
AX
BX
CX
DX
SP
BP
SI
DI
EFLAGS
GDTR
IDTR
LDTR
CR0
CR1
CR2
CR3
TR
Limit
LimitBase
Base
0151647
MSW
DR0
DR1
DR2
DR3
DR4
DR5
DR6
DR7
TR6
TR7
31 16 15 0

4.  Global Descriptor Table
 GDT provides a mechanism for defining the
characteristics of the 80386’s global memory address
space. Global memory is a general system resource that
is shared by many or all software tasks.
 Contains system segment descriptors
4
BASE LIMIT
047 16 15
0
8191
1
Global
Descriptor
Table
(GDT)
Global Descriptor Table Register(GDTR) MAX: 64k bytes
8K entries

5.  These descriptors identify the characteristics of the
segments of global memory.
 One descriptor exists for each segment of memory in
virtual address space.
 8 bytes long and contains three kinds of information
 Limit
 Base
 Access Rights
5

6.  Interrupt Descriptor Table (IDT)
 Contains interrupt descriptors, not segment descriptors
 IDT can also be up to 64KB; But 80386 only supports
up to 256 interrupts and exceptions(2KB)
6
BASE LIMIT
047 16 15
0
255
1
Interrupt
Descriptor
Table
(IDT)
Interrupt Descriptor Table Register(IDTR)
MAX: 2k bytes
256 entries

7.  Local Descriptor Table(LDT)
 Each task can have
access to own private
descriptor table(LDT) in
addition to GDT.
 Contains descriptors that
provide access to code
and data in segments of
memory that are
reserved for the current
task.
7
GDT
LDT0
LDTn
LIMIT
BASE
LIMIT
BASE
selector
0
015
15
31
31
LDTR
LDTR
cache
program invisible
LDT0
LDTn
GDTR
15 0

8. 0112331 10
CR0
CR3
CR2
CR1RESERVED
RESERVED
Page Fault Linear Address
Page Directory Base Register
P
G
M
P
T
S
P
E
 MSW (machine status word) : CR0
 the lower 5 bits of CR0 are system-control flags
 PE: protected-mode enable bit
 At reset, PE is cleared.(real mode)
 Set PE to 1 to enter protected mode
 Once in protected mode, 80386 cannot be switched
back to real mode under SW control
8
PE: protection enable
MP: math present
EM: emulate
ET: extension type
(coprocessor)
TS: task switched
RESERVED
E
M
E
T

9.  Paging mechanism
 MSB of CR0, CR2, CR3
 Task Register
 Task switching mechanism
 TSS descriptor
 TSS : task state segment; information needed to
initiate the task, such as initial values for the user-
accessible registers
9
Physical Memory
GDT
TSS
TSS descriptorTR
BASE LIMIT
0151647
015
Cache

10.  Example: The value of selector load to CS: 1007H, GDT
base 00100000H, LDT base 00120000H
 (CS) = 0001 0000 0000 0111 : RPL = 3, TI =1, Index =
0001 0000 0000 0
 Offset=0001 0000 0000 0 *8=512 *8=4096d=1000h
 Address of the segment descriptor
Descriptor address = 00120000H + 1000H =
00121000H
10
RPLINDEX
SEGMENT SELECTOR REGISTER
1-0
2
15-3
Requested
Privilege
Level (RPL)
Indicates selector privilege
level desired
Table
Indicator
(TI)
TI=0 use global descriptor table (GDT)
TI=1 use local descriptor table (LDT)
Index select descriptor entry in table
T
I
Bits Name Function

11.  VM : virtual 8086 Mode - system flag
 set only in Protected Mode by IRET instruction and by
task switches
 unaffected by POPF
 RF : resume flag - system flag
 in conjunction with the debug register breakpoints
 NT: nested task flag - system flag
 indicates that the execution of this task is nested
within another task
 IOPL : input/output privilege flag - system flag
 indicates the numerically maximum CPL(current)
value permitted to execute I/O instructions 11
0 0 0 0 0 0 0 0 0 0 0 0 0 0 V R 0 N IO O D I T S Z 0 A 0 P 1 C
M F T PL F F F F F F F F F
071531

12.  Virtual Address and Virtual Address Space
 virtual address : selector(16-bit): offset(32-bit)
-214(16,384 = 16K) unique segments of memory, each of
which has a maximum size of 4G bytes
 Total virtual address space = 246 , 64 TB
 T1 for global or local descriptor table to define Virtual
Address space 12
47 32 31 0
T
I
selector offset
47 32 31 0
RPLINDEX

13.  Segment Partitioning of the Virtual Address Space
13
Local segment 8191
Local segment 1
Local segment 0
Global segment 8191
Global segment 1
Global segment 0
Local address space
32 Terabytes
Global address space
32 Terabytes
Virtual Address Space
64 Terabytes

14.  Application Program : a collection of tasks
 task: a group of program routines that together
perform a specific function
 A task can activate both global and local segments of
memory
14
Task 1
Local Address
Space
Global
Address
Space
Task 3
Local Address
Space
Task 2
Local Address
Space
Task 1 Virtual Address Space
Task 2 Virtual Address SpaceTask 3 Virtual Address Space

15. 15
SELECTOR OFFSET
SEGMENT
TRANSLATION
PG?
DIR PAGE OFFSET
31 0
PAGE
TRANSLATION
PHYSICAL ADDRESS
PAGING DISABLED
PAGING ENABLED
LOGICAL ADDRESS
LINEAR ADDRESS

16. 16
SELECTOR OFFSET
SEGMENT
TRANSLATION
PG?
DIR PAGE OFFSET
31 0
PAGE
TRANSLATION
PHYSICAL ADDRESS
PAGING DISABLED
PAGING ENABLED
LOGICAL ADDRESS
LINEAR ADDRESS
Data Segment
Descriptor
Cache Register
Selector Offset(EBX)
(DS)
Data
Segment
LDT
Operand
Segment
Descriptor

17. 17
CS
DS
SS
ES
FS
GS
Programmer
accessible
Selectors
Transparently Loaded by MPU
Access Rights Base Address Limit
01920515263
64-bit Segment
Descriptor
Cache Registers

18. Ref. :
Walter A. Triebel and Avtar Singh,
The 8088 and 886 Microprocessor.