The document provides instruction on the 8085 microprocessor instruction set. It discusses the different types of instructions including data transfer, arithmetic, and logical instructions. Data transfer instructions move data between registers and memory. Arithmetic instructions perform operations like addition, subtraction, incrementing, and decrementing. Logical instructions perform bitwise operations like AND and OR. The document provides examples of common instructions and explains their purpose and functionality.
Presentation On: "Micro-controller 8051 & Embedded System"surabhii007
The presentation is dealing with majors about 'An Embedded System' along with 'Micro-controller' with it's base peripherals & parameters.
Hope It'll be helpfull!
Presentation On: "Micro-controller 8051 & Embedded System"surabhii007
The presentation is dealing with majors about 'An Embedded System' along with 'Micro-controller' with it's base peripherals & parameters.
Hope It'll be helpfull!
Memory Organization | Computer Fundamental and OrganizationSmit Luvani
Agenda :
Introduction
Memory Cell
Memory Organization
Read Only Memory
Serial Access Memory
Physical Devices Used to Construct Memories
Magnetic Optical Disk
Virtual Memory
This all topics covered in This PPT.
Memory Organization | Computer Fundamental and OrganizationSmit Luvani
Agenda :
Introduction
Memory Cell
Memory Organization
Read Only Memory
Serial Access Memory
Physical Devices Used to Construct Memories
Magnetic Optical Disk
Virtual Memory
This all topics covered in This PPT.
Intel 8085 is an 8-bit microprocessor. It handles 8-bit data at a time. One byte consists of 8-bits.A memory location for Intel 8085 microprocessor is designed to accumulate 8-bit data. If 16-bit data are to be stored, they are stored in consecutive memory locations. The address of memory location is 0f 16-bit i.e. 2 bytes. In this slide we have discussed about the various instructions set of INTEL 8085 micrpoprocessor.
Accelerate your Kubernetes clusters with Varnish CachingThijs Feryn
A presentation about the usage and availability of Varnish on Kubernetes. This talk explores the capabilities of Varnish caching and shows how to use the Varnish Helm chart to deploy it to Kubernetes.
This presentation was delivered at K8SUG Singapore. See https://feryn.eu/presentations/accelerate-your-kubernetes-clusters-with-varnish-caching-k8sug-singapore-28-2024 for more details.
JMeter webinar - integration with InfluxDB and GrafanaRTTS
Watch this recorded webinar about real-time monitoring of application performance. See how to integrate Apache JMeter, the open-source leader in performance testing, with InfluxDB, the open-source time-series database, and Grafana, the open-source analytics and visualization application.
In this webinar, we will review the benefits of leveraging InfluxDB and Grafana when executing load tests and demonstrate how these tools are used to visualize performance metrics.
Length: 30 minutes
Session Overview
-------------------------------------------
During this webinar, we will cover the following topics while demonstrating the integrations of JMeter, InfluxDB and Grafana:
- What out-of-the-box solutions are available for real-time monitoring JMeter tests?
- What are the benefits of integrating InfluxDB and Grafana into the load testing stack?
- Which features are provided by Grafana?
- Demonstration of InfluxDB and Grafana using a practice web application
To view the webinar recording, go to:
https://www.rttsweb.com/jmeter-integration-webinar
Generating a custom Ruby SDK for your web service or Rails API using Smithyg2nightmarescribd
Have you ever wanted a Ruby client API to communicate with your web service? Smithy is a protocol-agnostic language for defining services and SDKs. Smithy Ruby is an implementation of Smithy that generates a Ruby SDK using a Smithy model. In this talk, we will explore Smithy and Smithy Ruby to learn how to generate custom feature-rich SDKs that can communicate with any web service, such as a Rails JSON API.
Smart TV Buyer Insights Survey 2024 by 91mobiles.pdf91mobiles
91mobiles recently conducted a Smart TV Buyer Insights Survey in which we asked over 3,000 respondents about the TV they own, aspects they look at on a new TV, and their TV buying preferences.
Kubernetes & AI - Beauty and the Beast !?! @KCD Istanbul 2024Tobias Schneck
As AI technology is pushing into IT I was wondering myself, as an “infrastructure container kubernetes guy”, how get this fancy AI technology get managed from an infrastructure operational view? Is it possible to apply our lovely cloud native principals as well? What benefit’s both technologies could bring to each other?
Let me take this questions and provide you a short journey through existing deployment models and use cases for AI software. On practical examples, we discuss what cloud/on-premise strategy we may need for applying it to our own infrastructure to get it to work from an enterprise perspective. I want to give an overview about infrastructure requirements and technologies, what could be beneficial or limiting your AI use cases in an enterprise environment. An interactive Demo will give you some insides, what approaches I got already working for real.
Essentials of Automations: Optimizing FME Workflows with ParametersSafe Software
Are you looking to streamline your workflows and boost your projects’ efficiency? Do you find yourself searching for ways to add flexibility and control over your FME workflows? If so, you’re in the right place.
Join us for an insightful dive into the world of FME parameters, a critical element in optimizing workflow efficiency. This webinar marks the beginning of our three-part “Essentials of Automation” series. This first webinar is designed to equip you with the knowledge and skills to utilize parameters effectively: enhancing the flexibility, maintainability, and user control of your FME projects.
Here’s what you’ll gain:
- Essentials of FME Parameters: Understand the pivotal role of parameters, including Reader/Writer, Transformer, User, and FME Flow categories. Discover how they are the key to unlocking automation and optimization within your workflows.
- Practical Applications in FME Form: Delve into key user parameter types including choice, connections, and file URLs. Allow users to control how a workflow runs, making your workflows more reusable. Learn to import values and deliver the best user experience for your workflows while enhancing accuracy.
- Optimization Strategies in FME Flow: Explore the creation and strategic deployment of parameters in FME Flow, including the use of deployment and geometry parameters, to maximize workflow efficiency.
- Pro Tips for Success: Gain insights on parameterizing connections and leveraging new features like Conditional Visibility for clarity and simplicity.
We’ll wrap up with a glimpse into future webinars, followed by a Q&A session to address your specific questions surrounding this topic.
Don’t miss this opportunity to elevate your FME expertise and drive your projects to new heights of efficiency.
State of ICS and IoT Cyber Threat Landscape Report 2024 previewPrayukth K V
The IoT and OT threat landscape report has been prepared by the Threat Research Team at Sectrio using data from Sectrio, cyber threat intelligence farming facilities spread across over 85 cities around the world. In addition, Sectrio also runs AI-based advanced threat and payload engagement facilities that serve as sinks to attract and engage sophisticated threat actors, and newer malware including new variants and latent threats that are at an earlier stage of development.
The latest edition of the OT/ICS and IoT security Threat Landscape Report 2024 also covers:
State of global ICS asset and network exposure
Sectoral targets and attacks as well as the cost of ransom
Global APT activity, AI usage, actor and tactic profiles, and implications
Rise in volumes of AI-powered cyberattacks
Major cyber events in 2024
Malware and malicious payload trends
Cyberattack types and targets
Vulnerability exploit attempts on CVEs
Attacks on counties – USA
Expansion of bot farms – how, where, and why
In-depth analysis of the cyber threat landscape across North America, South America, Europe, APAC, and the Middle East
Why are attacks on smart factories rising?
Cyber risk predictions
Axis of attacks – Europe
Systemic attacks in the Middle East
Download the full report from here:
https://sectrio.com/resources/ot-threat-landscape-reports/sectrio-releases-ot-ics-and-iot-security-threat-landscape-report-2024/
Securing your Kubernetes cluster_ a step-by-step guide to success !KatiaHIMEUR1
Today, after several years of existence, an extremely active community and an ultra-dynamic ecosystem, Kubernetes has established itself as the de facto standard in container orchestration. Thanks to a wide range of managed services, it has never been so easy to set up a ready-to-use Kubernetes cluster.
However, this ease of use means that the subject of security in Kubernetes is often left for later, or even neglected. This exposes companies to significant risks.
In this talk, I'll show you step-by-step how to secure your Kubernetes cluster for greater peace of mind and reliability.
GDG Cloud Southlake #33: Boule & Rebala: Effective AppSec in SDLC using Deplo...James Anderson
Effective Application Security in Software Delivery lifecycle using Deployment Firewall and DBOM
The modern software delivery process (or the CI/CD process) includes many tools, distributed teams, open-source code, and cloud platforms. Constant focus on speed to release software to market, along with the traditional slow and manual security checks has caused gaps in continuous security as an important piece in the software supply chain. Today organizations feel more susceptible to external and internal cyber threats due to the vast attack surface in their applications supply chain and the lack of end-to-end governance and risk management.
The software team must secure its software delivery process to avoid vulnerability and security breaches. This needs to be achieved with existing tool chains and without extensive rework of the delivery processes. This talk will present strategies and techniques for providing visibility into the true risk of the existing vulnerabilities, preventing the introduction of security issues in the software, resolving vulnerabilities in production environments quickly, and capturing the deployment bill of materials (DBOM).
Speakers:
Bob Boule
Robert Boule is a technology enthusiast with PASSION for technology and making things work along with a knack for helping others understand how things work. He comes with around 20 years of solution engineering experience in application security, software continuous delivery, and SaaS platforms. He is known for his dynamic presentations in CI/CD and application security integrated in software delivery lifecycle.
Gopinath Rebala
Gopinath Rebala is the CTO of OpsMx, where he has overall responsibility for the machine learning and data processing architectures for Secure Software Delivery. Gopi also has a strong connection with our customers, leading design and architecture for strategic implementations. Gopi is a frequent speaker and well-known leader in continuous delivery and integrating security into software delivery.
Encryption in Microsoft 365 - ExpertsLive Netherlands 2024Albert Hoitingh
In this session I delve into the encryption technology used in Microsoft 365 and Microsoft Purview. Including the concepts of Customer Key and Double Key Encryption.
Neuro-symbolic is not enough, we need neuro-*semantic*Frank van Harmelen
Neuro-symbolic (NeSy) AI is on the rise. However, simply machine learning on just any symbolic structure is not sufficient to really harvest the gains of NeSy. These will only be gained when the symbolic structures have an actual semantics. I give an operational definition of semantics as “predictable inference”.
All of this illustrated with link prediction over knowledge graphs, but the argument is general.
Neuro-symbolic is not enough, we need neuro-*semantic*
Instruction set class
1. Instruction Set
• Prof. Rajesh R.K.
• Assistant Professor,
• Department of MCA
• Mohandas College of Engineering &
Technology, Thiruvananthapuram, Kerala
2. Instruction
• An instruction is a binary pattern designed
inside a microprocessor to perform a specific
function.
• 8085 has 246 instructions.
• Each instruction is represented by an 8-bit
binary value.
3. 1. Introduction
• A microprocessor executes instructions given by the
user
• Instructions should be in a language known to the
microprocessor
• Microprocessor understands the language of 0’s and
1’s only
• This language is called Machine Language
4. Assembly language program to add two
numbers
MVI A, 2H ;Copy value 2H in register A
MVI B, 4H ;Copy value 4H in register B
ADD B ;A = A + B
Note:
• Assembly language is specific to a given processor
• For e.g. assembly language of 8085 is different than
that of Motorola 6800 microprocessor
5. Microprocessor understands Machine Language only!
• Microprocessor cannot understand a program
written in Assembly language
• A program known as Assembler is used to convert a
Assembly language program to machine language
Assembly
Language
Program
Assembler
Program
Machine
Language
Code
9. Classification Of Instruction Set
• There are 5 Types,
• (1) Data Transfer Instruction,
• (2) Arithmetic Instructions,
• (3) Logical Instructions,
• (4) Branching Instructions,
• (5) Control Instructions,
10. (1) Data Transfer Instructions
• MOV Rd, Rs
• MOV M, Rs
• MOV Rd, M
• This instruction copies the contents of the
source register into the destination register.
• The contents of the source register are not
altered.
• Example: MOV B,A or MOV M,B or MOV C,M
11. A 20 B 20
A F
B 30 C
D E
H 20 L 50
A 20 B
BEFORE EXECUTION AFTER EXECUTION
MOV B,A
A F
B 30 C
D E
H 20 L 50
A F
B C
D E
H 20 L 50
A F
B C 40
D E
H 20 L 50
MOV M,B
MOV C,M
40 40
30
12. • MVI R, Data(8-bit)
• MVI M, Data(8-bit)
• The 8-bit immediate data is stored in the
destination register (R) or memory (M), R is
general purpose 8 bit register such as
A,B,C,D,E,H and L.
• Example: MVI B, 60H or MVI M, 40H
(2) Data Transfer Instructions
13. A F
B C
D E
H L
A F
B 60 C
D E
H L
AFTER EXECUTIONBEFORE EXECUTION
MVI B,60H
40
HL=2050H
2051H
204FH 204FH
HL=2050H
2051H
MVI M,40H
BEFORE EXECUTION AFTER EXECUTION
14. • LDA 16-bit address
• The contents of a memory location, specified
by a 16-bit address in the operand, are
copied to the accumulator (A).
• The contents of the source are not altered.
• Example: LDA 2000H
(3) Data Transfer Instructions
16. (4) Data Transfer Instructions
• LDAX Register Pair
• Load accumulator (A) with the contents of
memory location whose address is specified
by BC or DE or register pair.
• The contents of either the register pair or the
memory location are not altered.
• Example: LDAX D
17. A F
B C
D 20 E 30
A 80 F
B C
D 20 E 30
80 80
AFTER EXECUTIONBEFORE EXECUTION
LDAX D
2030H 2030H
18. (5) Data Transfer Instructions
• STA 16-bit address
• The contents of accumulator are copied into
the memory location i.e. address specified by
the operand in the instruction.
• Example: STA 2000 H
19. A 50 A 50
50
AFTER EXECUTIONBEFORE EXECUTION
STA 2000H2000H 2000H
20. (6) Data Transfer Instructions
• STAX Register Pair
• Store the contents of accumulator (A) into
the memory location whose address is
specified by BC Or DE register pair.
• Example: STAX B
21. A 50 F
B 10 C 20
D E
A 50 F
B 10 C 20
D E
50
AFTER EXECUTIONBEFORE EXECUTION
STAX B
1020H 1020H
22. • LHLD 2050 Means..copy content of 2050 and 2051 to
HL pair
if
2050 -> 90H
2051->5AH
LHLD 2050 implies..
L -> 90H
H -> 5AH
23. •
LXI means..Load Register Pair with Immediate data.. 16bit data
LXI B ,2050H
Loads BC pair with value 2050H
B-> 20H
C-> 50H
Its similar to 2 MVI instruction
ie
MVI B,20H
MVI C,50H
24. (7) Data Transfer Instructions
• SHLD 16-bit address
• Store H-L register pair in memory.
• The contents of register L are stored into
memory location specified by the 16-bit
address.
• The contents of register H are stored into the
next memory location.
• Example: SHLD 2500 H
25. H 30 L 60
BEFORE EXECUTION AFTER EXECUTION
60
30
H 30 L 60
SHLD 2500H2500H 2500H
204FH
2502H
204FH
2502H
26. (8) Data Transfer Instructions
• XCHG
• The contents of register H are exchanged
with the contents of register D.
• The contents of register L are exchanged with
the contents of register E.
• Example: XCHG
27. D 20 E 40
H 70 L 80
D 70 E 80
H 20 L 40
BEFORE EXECUTION AFTER EXECUTION
XCHG
28. (9) Data Transfer Instructions
• SPHL
• Move data from H-L pair to the Stack Pointer
(SP)
• This instruction loads the contents of H-L pair
into SP.
• Example: SPHL
29. H 25 L 00
SP
BEFORE EXECUTION
AFTER EXECUTION
H 25 L 00
SP 2500
SPHL
30. (10) Data Transfer Instructions
• XTHL
• Exchange H–L with top of stack
• The contents of L register are exchanged with
the location pointed out by the contents of
the SP.
• The contents of H register are exchanged
with the next location (SP + 1).
• Example: XTHL
32. (11) Data Transfer Instructions
• PCHL
• Load program counter with H-L contents
• The contents of registers H and L are copied into
the program counter (PC).
• The contents of H are placed as the high-order
byte and the contents of L as the low-order
byte.
•
34. (12) Data Transfer Instructions
• IN 8-bit port address
• Copy data to accumulator from a port with 8-
bit address.
• The contents of I/O port are copied into
accumulator.
• Example: IN 80 H
35. 10 A
10 A 10
BEFORE EXECUTION
AFTER EXECUTION
IN 80H
PORT 80H
PORT 80H
36. (13) Data Transfer Instructions
• OUT 8-bit port address
• Copy data from accumulator to a port with 8-
bit address
• The contents of accumulator are copied into
the I/O port.
• Example: OUT 50 H
37. 10 A 40
40 A 40
BEFORE EXECUTION
AFTER EXECUTION
OUT 50H
PORT 50H
PORT 50H
39. (1) Arithematic Instructions
• ADD R
• ADD M
• The contents of register or memory are added
to the contents of accumulator.
• The result is stored in accumulator.
• If the operand is memory location, its address is
specified by H-L pair.
• Example: ADD C or ADD M
40. B C 30
D E
H L
B C 30
D E
H L
AFTER EXECUTIONBEFORE EXECUTION
B C
D E
H 20 L 50
B C
D E
H 20 L 50
AFTER EXECUTIONBEFORE EXECUTION
A 20
A 50A 20
A 30
ADD C
A=A+R
ADD M
A=A+M
10 10
2050 2050
41. (2) Arithematic Instructions
• ADC R
• ADC M
• The contents of register or memory and Carry Flag
(CY) are added to the contents of accumulator.
• The result is stored in accumulator.
• If the operand is memory location, its address is
specified by H-L pair. All flags are modified to reflect
the result of the addition.
• Example: ADC C or ADC M
42. B C 20
D E
H L
A 50
B C 20
D E
H L
A 71
AFTER EXECUTIONBEFORE EXECUTION
ADC C
A=A+R+CY
CY 1 CY 0
CY 1 CY 0
A 20 A 51
H 20 L 50 H 20 L 50
ADC M
A=A+M+CY
AFTER EXECUTIONBEFORE EXECUTION
30 302050H 2050H
43. (3) Arithematic Instructions
• ADI 8-bit data
• The 8-bit data is added to the contents of
accumulator.
• The result is stored in accumulator.
• Example: ADI 10 H
44. A 50 A 60
AFTER EXECUTIONBEFORE EXECUTION
ADI 10H
A=A+DATA(8)
45. (4) Arithematic Instructions
• ACI 8-bit data
• The 8-bit data and the Carry Flag (CY) are
added to the contents of accumulator.
• The result is stored in accumulator.
• Example: ACI 20 H
46. CY 1 CY 0
A 30 A 51
AFTER EXECUTIONBEFORE EXECUTION
ACI 20H
A=A+DATA
(8)+CY
47. (5) Arithematic Instructions
• DAD Register pair
• The 16-bit contents of the register pair are
added to the contents of H-L pair.
• The result is stored in H-L pair.
• If the result is larger than 16 bits, then CY is
set.
• Example: DAD D
49. (6) Arithematic Instructions
• SUB R
• SUB M
• The contents of the register or memory location are
subtracted from the contents of the accumulator.
• The result is stored in accumulator.
• If the operand is memory location, its address is
specified by H-L pair.
• Example: SUB B or SUB M
50. B 30 C
D E
H L
A 50
B 30 C
D E
H L
A 20
AFTER EXECUTIONBEFORE EXECUTION
SUB B
A=A-R
AFTER EXECUTIONBEFORE EXECUTION
A 50 A 40
H
10
L
20
H
10
L
20
SUB M
A=A-M
10 10
1020H1020H
51. (7) Arithematic Instructions
• SBB R
• SBB M
• The contents of the register or memory location and
Borrow Flag (i.e.CY) are subtracted from the contents of
the accumulator.
• The result is stored in accumulator.
• If the operand is memory location, its address is specified
by H-L pair.
• Example: SBB C or SBB M
52. B C 20
D E
H L
A 40
CY 1
B C 20
D E
H L
A 19
CY 0
SBB C
A=A-R-CY
AFTER EXECUTIONBEFORE EXECUTION
CY 1
A 50
H
20
L
50
CY 0
A 39
H
20
L
50
AFTER EXECUTIONBEFORE EXECUTION
SBB M
A=A-M-CY
10 10
2050H 2050H
53. (8) Arithematic Instructions
• SUI 8-bit data
• OPERATION: A=A-DATA(8)
• The 8-bit immediate data is subtracted from
the contents of the accumulator.
• The result is stored in accumulator.
• Example: SUI 45 H
54. (9) Arithematic Instructions
• SBI 8-bit data
• The 8-bit data and the Borrow Flag (i.e. CY) is
subtracted from the contents of the
accumulator.
• The result is stored in accumulator.
• Example: SBI 20 H
55. CY 1
A 50
AFTER EXECUTIONBEFORE EXECUTION
CY 0
A 29SBI 20H
A=A-DATA(8)-CY
56. (10) Arithematic Instructions
• INR R
• INR M
• The contents of register or memory location are
incremented by 1.
• The result is stored in the same place.
• If the operand is a memory location, its address
is specified by the contents of H-L pair.
• Example: INR B or INR M
57. B 10 C
D E
H L
A
B 11 C
D E
H L
A
AFTER EXECUTIONBEFORE EXECUTION
H
20
L
50
H
20
L
50
30 31
2050H 2050H
AFTER EXECUTIONBEFORE EXECUTION
INR M
M=M+1
B 10 C
D E
H L
A
BEFORE EXECUTION
INR B
R=R+1
58. (11) Arithematic Instructions
• INX Rp
• The contents of register pair are incremented
by 1.
• The result is stored in the same place.
• Example: INX H
59. B C
D E
H 10 L 20
B C
D E
H 11 L 21
AFTER EXECUTIONBEFORE EXECUTION
SPSP
INX H
RP=RP+1
60. (12) Arithematic Instructions
• DCR R
• DCR M
• The contents of register or memory location are
decremented by 1.
• The result is stored in the same place.
• If the operand is a memory location, its address
is specified by the contents of H-L pair.
• Example: DCR E or DCR M
61. B C
D E 19
H L
A
AFTER EXECUTION
B C
D E 20
H L
A
BEFORE EXECUTION
DCR E
R=R-1
H
20
L
50
H
20
L
5021 20
2050H
AFTER EXECUTIONBEFORE EXECUTION
DCR M
M=M-1
2050H
62. (13) Arithematic Instructions
• DCX Rp
• The contents of register pair are decremented
by 1.
• The result is stored in the same place.
• Example: DCX D
63. B C
D 10 E 20
H L
B C
D 10 E 19
H L
AFTER EXECUTIONBEFORE EXECUTION
SPSP
DCX D
RP=RP-1
64. (1) Logical Instructions
• ANA R
• ANA M
• AND specified data in register or memory with
accumulator.
• Store the result in accumulator (A).
• Example: ANA B, ANA M
65. B 10 C
D E
H L
A
B 0F C
D E
H L
A 0A
AFTER EXECUTION
ANA B
A=A and R
B 0F C
D E
H L
A AA
BEFORE EXECUTION
CY AC CY 0 AC 1
AFTER EXECUTIONBEFORE EXECUTION
CY AC CY 0 AC 1
A 11A 55
H 20 L 50 H 20 L 50
B3 B3
2050H
ANA M
A=A and M
2050H
1010 1010=AAH
0000 1111=0FH
0000 1010=0AH
0101 0101=55H
1011 0011=B3H
0001 0001=11H
66. (2) Logical Instructions
• ANI 8-bit data
• AND 8-bit data with accumulator (A).
• Store the result in accumulator (A)
• Example: ANI 3FH
67. CY AC
A B3
AFTER EXECUTIONBEFORE EXECUTION
CY 0 AC 1
A 33
ANI 3FH
A=A and DATA(8)
1011 0011=B3H
0011 1111=3FH
0011 0011=33H
68. (3) Logical Instructions
• XRA Register (8-bit)
• XOR specified register with accumulator.
• Store the result in accumulator.
• Example: XRA C
69. B 10 C
D E
H L
A
B C 2D
D E
H L
A 87
AFTER EXECUTION
XRA C
A=A xor R
B C 2D
D E
H L
A AA
BEFORE EXECUTION
CY AC CY 0 AC 0
1010 1010=AAH
0010 1101=2DH
1000 0111=87H
70. (4) Logical Instructions
• XRA M
• XOR data in memory (memory location
pointed by H-L pair) with Accumulator.
• Store the result in Accumulator.
• Example: XRA M
71. H 20 L 50
A 55
AFTER EXECUTION
XRA M
A=A xor M
BEFORE EXECUTION
CY AC CY 0 AC 0
0101 0101=55H
1011 0011=B3H
1110 0110=E6H
H 20 L 50
A E6
B3 B3
2050H 2050H
72. (5) Logical Instructions
• XRI 8-bit data
• XOR 8-bit immediate data with accumulator (A).
• Store the result in accumulator.
• Example: XRI 39H
73. CY AC
A B3
AFTER EXECUTIONBEFORE EXECUTION
CY 0 AC 0
A 8A
XRI 39H
A=A xor DATA(8)
1011 0011=B3H
0011 1001=39H
1000 1010=8AH
74. (6) Logical Instructions
• ORA Register
• OR specified register with accumulator (A).
• Store the result in accumulator.
• Example: ORA B
75. AFTER EXECUTIONBEFORE EXECUTION
CY AC
ORA B
A=A or R
1010 1010=AAH
0001 0010=12H
1011 1010=BAH
B 12 C
D E
H L
A AA
B 12 C
D E
H L
A BA
CY 0 AC 0
76. (7) Logical Instructions
• ORA M
• OR specified register with accumulator (A).
• Store the result in accumulator.
• Example: ORA M
77. AFTER EXECUTIONBEFORE EXECUTION
CY AC
ORA M
A=A or M
0101 0101=55H
1011 0011=B3H
1111 0111=F7H
H 20 L 50
A 55 A F7
CY 0 AC 0
H 20 L 50
B3 B3
2050H 2050H
78. (8) Logical Instructions
• ORI 8-bit data
• OR 8-bit data with accumulator (A).
• Store the result in accumulator.
• Example: ORI 08H
79. CY AC
A B3
AFTER EXECUTIONBEFORE EXECUTION
CY 0 AC 0
A BB
ORI 08H
A=A or DATA(8)
1011 0011=B3H
0000 1000=08H
1011 1011=BBH
80. (9) Logical Instructions
• CMP Register
• CMP M
• Compare specified data in register or memory
with accumulator (A).
• Store the result in accumulator.
• Example: CMP D or CMP M
81. B 10 C
D E
H L
A
B C
D B9 E
H L
A B8
AFTER EXECUTION
CMP D
A-R
B C
D B9 E
H L
A B8
BEFORE EXECUTION
CY Z CY 0 Z 0
AFTER EXECUTIONBEFORE EXECUTION
CY Z CY 0 Z 1
A B8A B8
H 20 L 50 H 20 L 50
B8 B8
2050H
CMP M
A-M
2050H
A>R: CY=0,Z=0
A=R: CY=0,Z=1
A<R: CY=1,Z=0
A>M: CY=0,Z=0
A=M: CY=0,Z=1
A<M: CY=1,Z=0
82. (10) Logical Instructions
• CPI 8-bit data
• Compare 8-bit immediate data with
accumulator (A).
• Store the result in accumulator.
• Example: CPI 30H
83. CY Z
A BA
AFTER EXECUTIONBEFORE EXECUTION
CY 0 AC 0
A BA
CPI 30H
A-DATA
A>DATA: CY=0,Z=0
A=DATA: CY=0,Z=1
A<DATA: CY=1,Z=0
1011 1010=BAH
89. (14) Logical Instructions
• RLC
• Rotate accumulator left
• Each binary bit of the accumulator is rotated left
by one position.
• Bit D7 is placed in the position of D0 as well as
in the Carry flag.
• CY is modified according to bit D7.
• Example: RLC.
91. (15) Logical Instructions
• RRC
• Rotate accumulator right
• Each binary bit of the accumulator is rotated right by
one
• position.
• Bit D0 is placed in the position of D7 as well as in the
Carry flag.
• CY is modified according to bit D0.
• Example: RRC.
93. (16) Logical Instructions
• RAL
• Rotate accumulator left through carry
• Each binary bit of the accumulator is rotated left
by one position through the Carry flag.
• Bit D7 is placed in the Carry flag, and the Carry
flag is placed in the least significant position D0.
• CY is modified according to bit D7.
• Example: RAL.
95. (17) Logical Instructions
• RAR
• Rotate accumulator right through carry
• Each binary bit of the accumulator is rotated left
by one position through the Carry flag.
• Bit D7 is placed in the Carry flag, and the Carry
flag is placed in the least significant position D0.
• CY is modified according to bit D7.
• Example: RAR
97. Concept of Subroutine
• In 8085 microprocessor a subroutine is a
separate program written aside from main
program ,this program is basically the
program which requires to be executed
several times in the main program.
• The microprocessor can call subroutine any
time using CALL instruction. after the
subroutine is executed the subroutine hands
over the program to main program using RET
instruction.
98. Branching Instructions
• The branch group instructions allows the
microprocessor to change the sequence of
program either conditionally or under certain
test conditions. The group includes,
• (1) Jump instructions,
• (2) Call and Return instructions,
• (3) Restart instructions,
99. (1) Branching Instructions
• JUMP ADDRESS
• BEFORE EXECUTION AFTER EXECUTION
• Jump unconditionally to the address.
• The instruction loads the PC with the address
given within the instruction and resumes the
program execution from specified location.
• Example: JMP 200H
PC PC 2000JMP 2000H
101. (2) Branching Instructions
• CALL address
• Call unconditionally a subroutine whose
starting address given within the
instruction and used to transfer
program control to a subprogram or
subroutine.
• Example: CALL 2000H
102. Conditional Calls
Instruction Code Description Condition for CALL
CC Call on carry CY=1
CNC Call on not carry CY=0
CP Call on positive S=0
CM Call on minus S=1
CPE Call on parity even P=1
CPO Call on parity odd P=0
CZ Call on zero Z=1
CNZ Call on not zero Z=0
103. (3) Branching Instructions
• RET
• Return from the subroutine unconditionally.
• This instruction takes return address from
the stack and loads the program counter
with this address.
• Example: RET
104. SP 27FD
PC
00
62
SP 27FF
PC 6200
00
62
AFTER EXECUTIONBEFORE EXECUTION
RET
27FFH
27FEH
27FDH
27FFH
27FEH
27FDH
105. (4) Branching Instructions
• RST n
• Restart n (0 to 7)
• This instruction transfers the program
control to a specific memory address. The
processor multiplies the RST number by 8 to
calculate the vector address.
• Example: RST 6
106. SP 3000
PC 2000
SP 2999
PC 0030
01
20
AFTER EXECUTIONBEFORE EXECUTION
RST 6
3000H
2FFFH
2FFEH
SP-1
ADDRESS OF THE NEXT INSTRUCTION IS 2001H
3000H
2FFFH
2FFEH
108. (1) Control Instructions
• NOP
• No operation
• No operation is performed.
• The instruction is fetched and decoded but no
operation is executed.
• Example: NOP
109. (2) Control Instructions
• HLT
• Halt
• The CPU finishes executing the current
instruction and halts any further execution.
• An interrupt or reset is necessary to exit from
the halt state.
• Example: HLT
110. (3) Control Instructions
• RIM
• Read Interrupt Mask
• This is a multipurpose instruction used to read the
status of interrupts 7.5, 6.5, 5.5 and read serial data
input bit.
• The instruction loads eight bits in the accumulator
with the following interpretations.
• Example: RIM
112. • SIM
• Set Interrupt Mask
• This is a multipurpose instruction and used to
implement the 8085 interrupts 7.5, 6.5, 5.5, and
serial data output.
• The instruction interprets the accumulator
contents as follows.
• Example: SIM