The document describes the specifications of various logic integrated circuits (ICs), including their fan-in, fan-out, input, and output characteristics. It defines common digital IC terminology related to voltage levels, current parameters, propagation delays, and noise immunity. It then examines the characteristics of different logic families, specifically TTL and CMOS. TTL families include standard TTL, low power TTL, high speed TTL, and others. CMOS families include 4000 series and 74C/HC/HCT series. Key specifications like voltage levels, noise margins, and power dissipation are compared between TTL and CMOS logic families.

1. Objective
Describe the specification of the various logic ICs with
emphasis on fan-in, fan-out, input and output
characteristic.
Verify the common technical specification of TTL and
CMOS logic families.

2. Basic
Characteristics
Digital ICs are a collection of resistors, diodes, and transistors
fabricated on apiece of semiconductor material (usually silicon).
Digital ICs are categorized according to their circuit complexity as
measured by the number of equivalent logic gates packaged
within.
Complexity Numbers of gates
Small-scale integration (SSI) Fewer than 12
Medium-scale integration (MSI) 12 to 99
Large-scale integration (LSI) 100 to 9999
Very large-scale integration (VLSI) 10,000 or more
Ultra large-scale integration (ULSI) 100,000 or more

3. Integrated Circuit Logic Families: EC30110
3
WEST (AMK) Unit 5 YUNOS
In the beginning…
Diode Logic (DL)
• simplest; does not scale
• NOT not possible (need
an active element)
=
=
Resistor-Transistor
Logic (RTL)
• replace diode switch
with a transistor switch
• can be cascaded
• large power draw
3

4. Integrated Circuit Logic Families: EC30110
4
WEST (AMK) Unit 5 YUNOS
was…
=
Diode-Transistor Logic (DTL)
• essentially diode logic with transistor amplification
• reduced power consumption
• faster than RTL
DL AND gate Saturating inverter
4

5. Types of IC families:
TTL Family
TTL Prefix Example IC
a) Standard TTL 74 7404(hex inverter)
b) High speed TTL 74H 74H04
c) Low power TTL 74L 74L04
d) Low power Schottky TTL 74LS 74LS04
e) Advanced Schottky 74AS 74AS04
f) Advanced low power Schottky TTL 74ALS 74ALS04

6. CMOS Family
CMOS Prefix Example IC
a) Metal oxide 40 or 140 4001 or 14001
CMOS (quad NOR gates)
b) Metal oxide, pin compatible 74C 74C02
with TTL (quad NOR gates)
c) Silicon gate, pin compatible 74HC 74HC02
with TTL, high speed (quad NOR gates)
d) Silicon gate, high speed, 74HCT 74HCT02
electrically compatible with TTL (quad NOR gates)

7. Power and Ground
Digital ICs are DC powered with ground.
Power supply pin for TTL circuit is labeled Vcc and for
CMOS circuit is labeled Vdd.

8. Logic-level Voltage Ranges
Logic 0
Logic 0
Indeterminate
Indeterminate
Logic 1
Logic 1
TTL CMOS
0V 0V
0.8V
1.5V
2V
3.5V
5V 5V

9. Unconnected (Floating)
Inputs
A floating TTL input acts as logic 1
Inputs not used should be connected to logic HIGH as a floating
TTL input is extremely susceptible to picking up noise signals
that can adversely affect the device’s operation.
A floating TTL input will measure a DC level between 1.4V to
1.8V.
+5V
1k
A
B X = AB X = AB
X = AB
A
B
A
B
(a) (b) (c)
Three ways to handle unused logic inputs
Unconnected
(floating)

10. If a CMOS input is left floating, it may become
overheated and eventually destroyed itself.
Thus, all inputs to a CMOS IC must be connected to a
LOW or a HIGH level or to the output of another IC.
A floating CMOS input will not measure as a specific
DC voltage but fluctuate randomly as it picks up noise.
Thus, it does not act as a logic 1 or logic 0 and its effect
on the output is unpredictable.

11. Digital IC terminology
Voltage parameters
a) VIH (min) – High-Level Input Voltage
The voltage level required for logic 1 at an input.
Any voltage below this level will not be accepted as a HIGH by the logic circuit.
b) VIL (max) – Low-Level Input Voltage
The voltage level required for logic 0 at an input.
Any voltage above this level will not be accepted as a LOW by the logic circuit.
c) VOH (min) – High-Level Output Voltage
The voltage level at a logic circuit output in the logic 1 state.
The maximum value of VOH is usually specified.
d) VOL (max) – Low-Level Output Voltage
The voltage level at a logic circuit output in the logic 0 state
The maximum value of VOL is usually specified.

12. Integrated Circuit Logic Families: EC30110
12
WEST (AMK) Unit 5 YUNOS
VOH(min) – The minimum voltage level at an output in the logical
“1” state under defined load conditions
VOL(max) – The maximum voltage level at an output in the logical
“0” state under defined load conditions
VIH(min) – The minimum voltage required at an input to be
recognized as “1” logical state
VIL(max) – The maximum voltage required at an input that still will
be recognized as “0” logical state
Logic families: V levels
VOH VIH VOL VIL
12

13. Current parameters
a) IIH – High-Level Input Current
The current the flows into an input when a specified HIGH-level
voltage is applied to that input.
b) IIL – Low-Level Input Current
The current that flows into an input when a specified LOW-level
voltage is applied to that input.
c) IOH – High-Level Output Current
The current that flows from an output in the logical 1 state under
specified load conditions.
d) IOL – Low-Level Output Current
The current that flows from an output in the logical 0 state under
specified load conditions.

14. Integrated Circuit Logic Families: EC30110
14
WEST (AMK) Unit 5 YUNOS
IOH – Current flowing into an output in the logical “1” state under
specified load conditions
IOL – Current flowing into an output in the logical “0” state under
specified load conditions
IIH – Current flowing into an input when a specified HI level is
applied to that input
IIL – Current flowing into an input when a specified LO level is
applied to that input
Logic families: I requirements
VOH VIH VOL VIL
IOH IIH IOL IIL
14

15. +5V
HIGH LOW
Current and Voltages in the 2 logic inputs
IOH
VOH
+
_
IIH
VIH
+
_
IOL
VOL
+
_
IIL
VIL
+
_

16. Fan-Out
A logic circuit output is specified to drive a certain fixed
number of logic inputs.
The fan-out (also called loading factor) is defined as the
maximum number of standard logic inputs that an
output can drive reliably.
For example, a logic gate specified to have a fan-out of
10 can drive 10 standard logic inputs. If this number is
exceeded, the output logic level voltages cannot be
guaranteed.

17. Propagation Delays
A logic signal always experiences a delay in going through a
circuit.
Two propagation delay times are defined as:
tPLH – delay time in going from logical 0 to logical 1 state.
tPHL – delay time in going from logical 1 to logical 0 state.
In general, tPHL and tPLH are not the same value, and both will
vary depending on loading conditions. The values of propagation
times are used as a measure of the relative speed of logic
circuits. For example, a logic circuit with values of 10ns is a
faster logic circuit than one with values of 20ns.

18. Noise Immunity
The noise immunity of a logic circuit refers to the
circuit’s ability to tolerate noise voltages on its inputs.
A quantitative measure of noise immunity is called
noise margin.

19. Disallowed
range
Logic
1
Logic
0
Output voltage
ranges
Indeterminate
range
Logic
1
Logic
0
Input voltage
requirements
(a) (b)
(a) Diagram showing range of voltages that can occur at a logic circuit output
(b) Input voltage requirements at a logic circuit input
Voltage
VOH (min)
VOL (max)
VIL (max)
VIH (min)
{
VNH
{
VNL

20. DC Noise Margins
a) The high-state noise margin VNH is defined as
VNH = VOH (min) – VIH (min)
b) The low-state noise margin VNL is defined as
VNL = VIL (max) – VOL (max)

21. Current-Sourcing and Current-Sinking
Logic
Current-sourcing action
Driving gate supplies (sources) current to load gate in HIGH
state.
+VCC
VOH
Driving gate
Load gate
Current Sourcing Action
1
2
Current sourcing
Driving gate supplies
(sources) current to load
gate in HIGH state.
LOW
LOW
IIH

22. Current-sinking action
Driving gate receives (sink) current from load gate in LOW state.
1
2 Current sinking
Driving gate receives
(sinks) current from
load gate in LOW state.
IIL
HIGH
HIGH
Current Sinking Action
+VCC
Load gate
Driving gate
VOL

23. Standard TTL series
characteristics
Standard 74 series voltage levels
Minimum Typical Maximum
VOL - 0.1 0.4
VOH 2.4 3.4 -
VIL - - 0.8
VIH 2.0 - -
Noise Margins (worst case) VNL = VNH = 400mV
Average power dissipation Pd = 10mW
Average propagation delay td = 9nsec
Typical fan-out = 10

24. Other TTL series
a) Low-Power TTL, 74L series
Same basic circuit as standard 74 series except that all resistor
values are increased, thus reducing the power requirements.
Increased resistor values results in longer propagation delays.
Suitable for low frequency operation.
Has become obsolete.
b) High-Speed TTL, 74H series
Smaller resistor values used and have much faster switching
speed with an average propagation delay of 6ns.
The power dissipation, however, is higher.

25. c) Schottky TTL, 74S series
A Schottky Barrier Diode (SBD) is included to increase switching
speed.
Schottky diode
74S have twice the speed of 74H at about the same power
requirement.

26. d) Low-Power Schottky TTL, 74LS series (LS-TTL)
Lower-powered, slower speed version of the 74S series.
Most common series in TTL family.
e) Advanced Schottky TTL, 74AS series (AS TTL)
Improved in speed over the 74S series at a much lower power
requirement.
Fastest TTL series and speed power product is lower than 74S
series.
Requires lower input current (IIL, IIH) that results in a greater fan-
out.
f) Advanced Low-Power Schottky TTL, 74ALS series
Lowest speed-power product of all the TTL series.
Lowest gate power dissipation.
Higher fan-out.

27. TTL loading and fan-out
Fig 5.3 (a) shows a standard TTL output in the LOW state
connected to drive several standard TTL inputs.
With gate 1 output in the LOW state, it will sink an amount of
current IOL which is the sum of the IIL currents from each input.
IOL
IIL
IIL
+5V
+5V
1
1
VOL
Fig 5.3 (a)

28. Determining the Fan-out
To determine how many different inputs an IC output
can drive, one needs to know the current drive
capability of the output [i.e. IOL(max) and IOH(max)] and
the current requirements of each input (i.e. IIL and IIH).

29. Unit Loads
The device input and output currents is specified in terms of
UNIT LOAD (UL).
1 unit load (UL) =
40uA in the HIGH state
1.6mA in the LOW state
Example: If an IC has a fan-out of 10 UL, it means
IOH(max) = 10 x 40uA = 100uA
IOL(max) = 10 x 1.6mA = 16mA

30. MOS Digital Integrated Circuits
The transistors of MOS technology are field-effect transistors
called MOSFETs.
The advantages of MOSFET are that it is:
Relatively simple and inexpensive to fabricate (since no other components needed)
Small
Consuming lesser power
MOS ICs can accommodate a much larger number of circuit
elements on a single chip than a bipolar ICs.
This higher packing density of MOS ICs result in greater system
operating speed due to the reduction of external connections.
However, MOS ICs are relatively slow in operating speed as
compared to bipolar ICs.

31. Digital MOSFET circuits
Three categories of MOSFETs:
1. P-MOS :- P-channel enhancement MOSFETs
2. N-MOS :- N-channel enhancement MOSFETs
3. C-MOS :- Complementary MOS
P-MOS and NMOS digital ICs have a greater packing density
and more economical as compared to CMOS ICs.
N-MOS is twice as fast as P-MOS.
CMOS has greater complexity and lowest packing density of the
MOS families.
CMOS has higher speed and much lower power dissipation
among the MOS families.

32. Characteristics of MOS logic
MOS logic families compared to bipolar logic families:
a) Slower speed
b) Requires much less power (large resistance)
c) Better noise margin
d) Greater supply voltage range
e) Higher fan-out
f) Simplest to fabricate (only N-MOS or P-MOS
elements are used)

33. CMOS series characteristics
a) 4000 series
2 versions, namely 4000A and 4000B with the “B” series having
higher output current capabilities.
b) 74C series
pin-for-pin and function-for-function compatible with TTL
devices having the same number.
c) 74HC series (high speed CMOS)
higher switching speed and higher output current capability.
d) 74HCT series
voltage-compatible with TTL devices.
can be driven directly by a TTL output.

34. Voltage levels
When CMOS outputs drive only CMOS inputs, the output
voltage levels will be very close to 0V for the LOW state, and
+Vdd for the HIGH state.
This is due to very high CMOS input resistance drawing very
little current from the CMOS output that is driving it.
The input voltage requirements for both logic states are expressed
as a percentage of the supply voltage as such:
VIL(max) = 30% of Vdd
VIH(min) = 70% of Vdd
For example, when a CMOS is operating from Vdd = +5V, it will
accept any input voltage less than VIL(max) = 1.5V as a LOW,
and any input voltage greater than VIH(min) = 3.5V as a HIGH.

35. Noise Margins
CMOS noise margins are determined as follows:
VNH = VOH(min) – VIH(min)
= Vdd – 70% Vdd
= 30% Vdd
VNL = VIL(max) – VOL(max)
= 30% Vdd – 0
= 30% Vdd
The noise margins are the same in both states and depend on Vdd.
For example, at Vdd = +5V, the noise margins are both 1.5V
which is better than TTL.
This makes CMOS attractive for applications that are exposed to
a high-noise environment.

36. Power dissipation
When CMOS logic circuit is in static state (not changing), its power
dissipation, Pd, is extremely Low.
However, the power dissipation will increase in proportion to frequency
at which the circuits are switching states.
Each time a CMOS output switches from ‘0’ to ‘1’, a transient charging
current has to be supplied to the load capacitance which consists of the
combined input capacitances of any loads being driven and the device’s
own output capacitance.
These narrow spikes of current are supplied by Vdd, which can be of
5mA. As the switching frequency increases, there will be more of these
current spikes and the average current drawn from Vdd will increase.
Thus, at higher frequencies, CMOS begins to lose some of its
advantage over other logic families.

37. +
Current spikes drawn from Vdd each time the output
switches from ‘0’ to ‘1’
+5V
ON
OFF
CLOAD
VIN
+
_
ID
P
N
VIN
5V
0V
VOUT
5V
0V
ID
0V
VOUT

38. Fan-out
CMOS inputs have extremely large resistance (10M ohms) that draws
essentially no current from the signal source.
Each CMOS inputs has a capacitance (5pF) that limit the number of
CMOS inputs that one CMOS output can drive.
The CMOS output has to change and discharge the parallel
combination of each input number of loads being driven.
Typically, each CMOS load increases the driving circuit’s propagation
delay by 3nsec.
CMOS outputs are limited to a fan-out of 50 for low frequency
operation.
For higher frequency, the fan-out would have to be less.

39. Each CMOS input adds to the total load capacitance
seen by the the driving gate’s output
+
5pF
+
5pF
Gate 1 output
drives a total
CLOAD of N x 5pF
To other loads

40. Unused inputs
CMOS input should never be left disconnected.
All CMOS inputs have to be tied either to a fixed
voltage level (0V or Vdd) or to another input.
An unconnected CMOS input is susceptible to noise and
static charges that could easily bias the P and N-channel
MOSFETs in the conductive state, resulting increased
power dissipation and possible overheating.