The document discusses the rise of the nanowire transistor for use in smartphones. Nanowires are microscopic wires with widths measured in nanometers that can improve transistor performance by allowing for superior gate control, high drive current, reduced sensitivity to process variations, and improved transport properties. This helps push the limits of transistor downscaling for faster speeds and lower power consumption. The document also notes specific benefits of nanowires such as reduced lattice thermal conductance and faster switching speeds compared to conventional transistors.

1. RISE OF THE NANOWIRE TRANSISTOR
Compound-semiconductor nanowire to keep smartphones charged longer
Chalamaneni Jeevan Prasad (154M1A0419)
Department of E.C.E, VEMU Institute of Technology, Chittoor 517124
ABSTRACT
1. Superior gate control (minimize channel effects).
2. High drive current.
3. Less sensitive to process variations.
4. Improved transport property.
5. Ultimate limit on the current trend of down
Scaling transistors and integrated circuits to
achieve faster speeds and lower power consumption
INTRODUCTION
NANO WIRE
Nanowires are microscopic wires that have a
width measured in Nano meters. Typically their
width ranges from forty to fifty Nano meters, but
their length is not so limited. Since they can be
lengthened by simply attaching more wires end
to end or just by growing them longer, they can
be as long as desired.
FEATURES
SIZE IMPRESSION ON NANO WIRE
REFERENCES
CONCLUSION
RESULT
Reduction in lattice thermal conductance as high as
30% obtained by 20% atom removal. Weak material
depend Si & Ge nanowire show similar reduction.
Node reduction in lattice thermal conductance.
RTDs is much faster than any other conventional trans.
Very good rectifier low leakage current. Much research
needs to be done to improve the output power and also
to integrate them with conventional transistors.
Volume inversion dominant until dnw=4nm. Surface phonon
and back scattering dominant below dnw=4nm.
We cherish our smartphones for delivering
entertainment and information on the go but their
need for daily charging is a problem. So when new
smartphone models come on the market with
Microprocessors based on the latest foundry
process, the increase in the number of transistors
in the chips should be balanced by a reduction in
the power.
https://ieeexplore.ieee.org/abstract/document/4419093
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GSDSAT VI 
Sung Dae Suk, et al., “Investigation of nanowire size dependency on
TSNWFET,” IEDM 2007, pp. 891-894.
Kyoung Hwan Yeo, et al., “Gate-All-Around (GAA) Twin Silicon
Nanowire MOSFET (TSNWFET),” IEDM 2006.
▪ At around 10 nanometres from the interface, the quality
of the material is very good, so we can grow the. Channel
layers.
▪ The total thickness for the layers bridging the difference in
lattice spacing is just 150 nm, compared with roughly 1μm.
▪ Traditional buffer layers, meaning less material, lower
costs, and faster production.
▪ It avoids many complications of crystal growth.
▪ The nanowire devices also yielded a trans conductance of
1,057 μS/μm, which is a record for electron-transporting
germanium nanowire FETs.