International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
High Performance and Low power VLSI CMOS Circuit Designs using ONOFIC Approach IJERA Editor
Leakage power dissipation a major concern for scaling down portable devices. Improving high performance with reduced power consumption and chip area are the main constraint for designing VLSI CMOS circuits. In this paper, high performance and low power ONOFIC approach for VLSI CMOS circuits have been implemented. Mostly the concentrated part in deep sub micron regime is the power dissipation. Many techniques have been proposed for reducing leakage current in deep sub micron but with some limitations they are not suitable for actual requirements. Here we discussed two techniques named LECTOR & ONOFIC. The proposed On/Off Logic (ONOFIC) serves the needs for deep sub micron with its reduced power dissipation and increased performance in VLSI circuits. Thus the proposed ONOFIC approach results have been compared with the LECTOR technique and observed that the proposed technique improves the performance and reduce the power dissipation.
Extremely Low Power FIR Filter for a Smart Dust Sensor ModuleCSCJournals
Digital filters are common components in many applications today, also in for sensor systems, such as large-scale distributed smart dust sensors. For these applications the power consumption is very critical, it has to be extremely low. With the transistor technology scaling becoming more and more sensitive to e.g. gate leakage, it has become a necessity to find ways to minimize the flow of leakage in current CMOS logic. This paper studies sub-threshold source coupled logic (STSCL) in a 45-nm process. The STSCL can be used instead of traditional CMOS to meet the low power and energy consumption requirements. The STSCL style is in this paper used to design a digital filter, applicable for the audio interface of a smart dust sensor where the sample frequency will be 44.1 kHz. A finite-length impulse response (FIR) filter is used with transposed direct form structure and for the coefficient multiplication five-bit canonic signed digit [7] based serial/parallel multipliers were used. The power consumption is calculated along with the delay in order to present the power delay product (PDP) such that the performance of the sub-threshold logic can be compared with corresponding CMOS implementation. The simulated results shows a significant reduction in energy consumption (in terms of PDP) with the system running at a supply voltage as low as 0.2 V using STSCL.
Design and Implementation of Re-configurable AntennaIJARIIT
This paper introduces a design of advanced and efficient technique used for antenna reconfiguration. Conventional
antennas are designed for specific application as it operates at a particular frequency range. On the other hand reconfigurable
antenna provides performance enhancement and gives single antenna structure to operate at various frequency range. In
order to obtain this, we use the technique of frequency reconfiguration i.e. PIN diode switching through which it can switch
among different frequency band. Antenna design is simulated and analyzed using HFSS software.
Comparative analysis of technology advancement from single gate to multi gate...eSAT Journals
Abstract
Among the entire contender in modern microelectronics,DG-MOSFET is a front line runner in planar technology. Itsunique
structure allows scaling the device at sub-nanometer region and mimicking the electrical characteristics of a MOSFET.Here
simulation of NMOS, SOI-NMOS, and DG-NMOS is presentedand relative comparison among short channel characteristics
ispresented.It has been seen that among all the above stated device, DG-MOSFET possess better immune to leakage current with
betterDIBL, whereas SOI MOSFET have better driving capacity.
KeyWords:SOI-MOSFET, DG-MOSFET, UTB, DIBL,SCEs
Design and simulation of a tunable frequency microstrip patch antennaeSAT Journals
Abstract This paper presents an evaluation of frequency reconfigurable patch antennas for X-band, using PIN diode as a switch. A pin diode is incorporated in the slot etched on rectangular patch antenna. The frequency band selectivity can be achieved by controlling the state of switch inserted in the antenna. We are using IE3D simulation software for designing and analysis. We have discussed and analyzed the performance of unslotted Rectangular Microstrip patch antenna and slotted rectangular patch antenna with PIN diode in ON and OFF states. Keyword: Microstrip Antenna, Return Loss, Radiation pattern, IE3D.
High Performance and Low power VLSI CMOS Circuit Designs using ONOFIC Approach IJERA Editor
Leakage power dissipation a major concern for scaling down portable devices. Improving high performance with reduced power consumption and chip area are the main constraint for designing VLSI CMOS circuits. In this paper, high performance and low power ONOFIC approach for VLSI CMOS circuits have been implemented. Mostly the concentrated part in deep sub micron regime is the power dissipation. Many techniques have been proposed for reducing leakage current in deep sub micron but with some limitations they are not suitable for actual requirements. Here we discussed two techniques named LECTOR & ONOFIC. The proposed On/Off Logic (ONOFIC) serves the needs for deep sub micron with its reduced power dissipation and increased performance in VLSI circuits. Thus the proposed ONOFIC approach results have been compared with the LECTOR technique and observed that the proposed technique improves the performance and reduce the power dissipation.
Extremely Low Power FIR Filter for a Smart Dust Sensor ModuleCSCJournals
Digital filters are common components in many applications today, also in for sensor systems, such as large-scale distributed smart dust sensors. For these applications the power consumption is very critical, it has to be extremely low. With the transistor technology scaling becoming more and more sensitive to e.g. gate leakage, it has become a necessity to find ways to minimize the flow of leakage in current CMOS logic. This paper studies sub-threshold source coupled logic (STSCL) in a 45-nm process. The STSCL can be used instead of traditional CMOS to meet the low power and energy consumption requirements. The STSCL style is in this paper used to design a digital filter, applicable for the audio interface of a smart dust sensor where the sample frequency will be 44.1 kHz. A finite-length impulse response (FIR) filter is used with transposed direct form structure and for the coefficient multiplication five-bit canonic signed digit [7] based serial/parallel multipliers were used. The power consumption is calculated along with the delay in order to present the power delay product (PDP) such that the performance of the sub-threshold logic can be compared with corresponding CMOS implementation. The simulated results shows a significant reduction in energy consumption (in terms of PDP) with the system running at a supply voltage as low as 0.2 V using STSCL.
Design and Implementation of Re-configurable AntennaIJARIIT
This paper introduces a design of advanced and efficient technique used for antenna reconfiguration. Conventional
antennas are designed for specific application as it operates at a particular frequency range. On the other hand reconfigurable
antenna provides performance enhancement and gives single antenna structure to operate at various frequency range. In
order to obtain this, we use the technique of frequency reconfiguration i.e. PIN diode switching through which it can switch
among different frequency band. Antenna design is simulated and analyzed using HFSS software.
Comparative analysis of technology advancement from single gate to multi gate...eSAT Journals
Abstract
Among the entire contender in modern microelectronics,DG-MOSFET is a front line runner in planar technology. Itsunique
structure allows scaling the device at sub-nanometer region and mimicking the electrical characteristics of a MOSFET.Here
simulation of NMOS, SOI-NMOS, and DG-NMOS is presentedand relative comparison among short channel characteristics
ispresented.It has been seen that among all the above stated device, DG-MOSFET possess better immune to leakage current with
betterDIBL, whereas SOI MOSFET have better driving capacity.
KeyWords:SOI-MOSFET, DG-MOSFET, UTB, DIBL,SCEs
Design and simulation of a tunable frequency microstrip patch antennaeSAT Journals
Abstract This paper presents an evaluation of frequency reconfigurable patch antennas for X-band, using PIN diode as a switch. A pin diode is incorporated in the slot etched on rectangular patch antenna. The frequency band selectivity can be achieved by controlling the state of switch inserted in the antenna. We are using IE3D simulation software for designing and analysis. We have discussed and analyzed the performance of unslotted Rectangular Microstrip patch antenna and slotted rectangular patch antenna with PIN diode in ON and OFF states. Keyword: Microstrip Antenna, Return Loss, Radiation pattern, IE3D.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
NOVEL SLEEP TRANSISTOR TECHNIQUES FOR LOW LEAKAGE POWER PERIPHERAL CIRCUITSVLSICS Design
Static power consumption is a major concern in nanometre technologies. Along with technology scaling down and higher operating speeds of CMOS VLSI circuits, the leakage power is getting enhanced. As process geometries are becoming smaller, device density increases and threshold voltage as well as oxide thickness decrease to keep pace with performance. Two novel circuit techniques for leakage current reduction in inverters with and without state retention property are presented in this work. The power dissipation during inactive (standby) mode of operation can be significantly reduced compared to traditional power gating methods by these circuit techniques. The proposed circuit techniques are applied to inverters and the results are compared with earlier inverter leakage minimization techniques. Inverter
buffer chains are designed using new state retention low leakage technique and found to be dissipating lower power with state retention. All low leakage inverters are designed and simulated in cadence design environment using 90 nm technology files. The leakage power during sleep mode is found to be better by X 63 times for novel method. The total power dissipation has also reduced by a factor of X 3.5, compared to earlier sleepy keeper technique. The state retention feature is also good compared to earlier leakage power reduction methodologies.
Analysis of FinFET based Low Power SRAM Cellijsrd.com
As CMOS electronic devices are continuously shrinking to nanometer regime, leads to increasing the consequences of short channel effects and variability due to the process parameters which lead to cause the reliability of the circuit as well as performance. To solve these issues of CMOS, FINFET is one of the promising and better technologies without sacrificing reliability and performance for its applications and the circuit design. Among the various embedded memory technologies, SRAM provides the highest performance along with low standby power consumption. In CMOS circuits, high leakage current in deep-submicron regimes is becoming a significant contributor to power dissipation due to reduction in threshold voltage, channel length, and gate oxide thickness. FinFET based SRAM design can be used as an alternative solution to the bulk devices. FinFET is suitable for Nano scale memory circuits design due to its reduced Short Channel Effects (SCE) and leakage current. As the impact of process variations become increasingly significant in ultra deep submicron technologies, FinFETs are becoming increasingly popular a contender for replacement of bulk FETs due to favorable device characteristics. The paper focuses on study of various design aspects of FinFET based SRAM.
A Comparative Study Of Low Power Consumption Techniques In A VLSI CircuitIJERA Editor
Power optimization has become an important factor in designing a VLSI circuit. Earlier dynamic power was single largest concern but as transistor size decreases static power dominates the dynamic power. A comparable analysis of different low power, leakage current reduction techniques like sleep, stack, sleepy keeper and reverse body bias with sleep and stack has been done. Based on simulations performed on a XNOR circuit, the reverse body with sleep and stack achieves up to 60% less power consumption as compared to the base case which is better than other conventional techniques. Simulations to estimate power consumption are done on a TANNER EDA tool at 90 nm technology.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Analysis of analog and RF behaviors in junctionless double gate vertical MOSFETjournalBEEI
The prime obstacle in continuing the transistor’s scaling is to maintain ultra-shallow source/drain (S/D) junctions with high doping concentration gradient, which definitely demands an advanced and complicated S/D and channel engineering. Junctionless transistor configuration has been found to be an alternative device structure in which the junction and doping gradients could be totally eliminated, thus simplifying the fabrication process. In this paper, a process simulation has been performed to study the impact of junctionless configuration on the analog and RF behaviors of double-gate vertical MOSFET. The result proves that the performance of n-channel junctionless double-gate vertical MOSFET (n-JLDGVM) is slightly better than the junction double-gate vertical MOSFET (n-JDGVM). Junctionless device exhibits better analog behaviors as the transconductance (gm) is increased by approximately 4%. In term of RF behaviors, the junctionless device exhibits 3.4% and 7% higher cut-off frequency (fT) and gain band-width product (GBW) respectively over the junction device.
ARDUINO MICROCONTROLLER BASED UNDERGROUND CABLE FAULT DISTANCE LOCATORIAEME Publication
The growing concern for safety and infrastructural proliferations in the densely
populated urban and suburban areas as well as the quest to preserve the aesthetic
values in many modern localities have necessitated the need for underground
installations. The underground cabling installations are devoid of faults common to the
overhead transmission lines but are associated with certain kinds of faults such as short
circuit and open circuit faults. Locating the exact position of any of these kinds of faults
is very exhausting, costly and time-consuming because its power distribution system is
invisible. Hence, a microcontroller based underground cable fault distance locator
powered by Arduino is designed to detect and pinpoint location of faults in underground
cable lines. A basic ohm’s law is employed to achieve the variation of current with
respect to resistance that determines the position of the fault. This device has a power
supply unit, cable unit, control unit, tripping unit and display unit. The power supply
unit provides power to the other components. The cable unit consists of a three-phase
cabling system with switches between each phase to activate faults. The control unit
takes in signals from the cable unit to cause control of tripping unit and display unit.
The tripping unit then detects the phase which encounters the fault and the display unit
shows the fault characteristics on the LCD. The distance to the fault is displayed,
alongside the phase which encounters the fault for easy clearance.
IJRET : International Journal of Research in Engineering and Technology is an international peer reviewed, online journal published by eSAT Publishing House for the enhancement of research in various disciplines of Engineering and Technology. The aim and scope of the journal is to provide an academic medium and an important reference for the advancement and dissemination of research results that support high-level learning, teaching and research in the fields of Engineering and Technology. We bring together Scientists, Academician, Field Engineers, Scholars and Students of related fields of Engineering and Technology
NOVEL SLEEP TRANSISTOR TECHNIQUES FOR LOW LEAKAGE POWER PERIPHERAL CIRCUITSVLSICS Design
Static power consumption is a major concern in nanometre technologies. Along with technology scaling down and higher operating speeds of CMOS VLSI circuits, the leakage power is getting enhanced. As process geometries are becoming smaller, device density increases and threshold voltage as well as oxide thickness decrease to keep pace with performance. Two novel circuit techniques for leakage current reduction in inverters with and without state retention property are presented in this work. The power dissipation during inactive (standby) mode of operation can be significantly reduced compared to traditional power gating methods by these circuit techniques. The proposed circuit techniques are applied to inverters and the results are compared with earlier inverter leakage minimization techniques. Inverter
buffer chains are designed using new state retention low leakage technique and found to be dissipating lower power with state retention. All low leakage inverters are designed and simulated in cadence design environment using 90 nm technology files. The leakage power during sleep mode is found to be better by X 63 times for novel method. The total power dissipation has also reduced by a factor of X 3.5, compared to earlier sleepy keeper technique. The state retention feature is also good compared to earlier leakage power reduction methodologies.
Analysis of FinFET based Low Power SRAM Cellijsrd.com
As CMOS electronic devices are continuously shrinking to nanometer regime, leads to increasing the consequences of short channel effects and variability due to the process parameters which lead to cause the reliability of the circuit as well as performance. To solve these issues of CMOS, FINFET is one of the promising and better technologies without sacrificing reliability and performance for its applications and the circuit design. Among the various embedded memory technologies, SRAM provides the highest performance along with low standby power consumption. In CMOS circuits, high leakage current in deep-submicron regimes is becoming a significant contributor to power dissipation due to reduction in threshold voltage, channel length, and gate oxide thickness. FinFET based SRAM design can be used as an alternative solution to the bulk devices. FinFET is suitable for Nano scale memory circuits design due to its reduced Short Channel Effects (SCE) and leakage current. As the impact of process variations become increasingly significant in ultra deep submicron technologies, FinFETs are becoming increasingly popular a contender for replacement of bulk FETs due to favorable device characteristics. The paper focuses on study of various design aspects of FinFET based SRAM.
A Comparative Study Of Low Power Consumption Techniques In A VLSI CircuitIJERA Editor
Power optimization has become an important factor in designing a VLSI circuit. Earlier dynamic power was single largest concern but as transistor size decreases static power dominates the dynamic power. A comparable analysis of different low power, leakage current reduction techniques like sleep, stack, sleepy keeper and reverse body bias with sleep and stack has been done. Based on simulations performed on a XNOR circuit, the reverse body with sleep and stack achieves up to 60% less power consumption as compared to the base case which is better than other conventional techniques. Simulations to estimate power consumption are done on a TANNER EDA tool at 90 nm technology.
IJERA (International journal of Engineering Research and Applications) is International online, ... peer reviewed journal. For more detail or submit your article, please visit www.ijera.com
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Analysis of analog and RF behaviors in junctionless double gate vertical MOSFETjournalBEEI
The prime obstacle in continuing the transistor’s scaling is to maintain ultra-shallow source/drain (S/D) junctions with high doping concentration gradient, which definitely demands an advanced and complicated S/D and channel engineering. Junctionless transistor configuration has been found to be an alternative device structure in which the junction and doping gradients could be totally eliminated, thus simplifying the fabrication process. In this paper, a process simulation has been performed to study the impact of junctionless configuration on the analog and RF behaviors of double-gate vertical MOSFET. The result proves that the performance of n-channel junctionless double-gate vertical MOSFET (n-JLDGVM) is slightly better than the junction double-gate vertical MOSFET (n-JDGVM). Junctionless device exhibits better analog behaviors as the transconductance (gm) is increased by approximately 4%. In term of RF behaviors, the junctionless device exhibits 3.4% and 7% higher cut-off frequency (fT) and gain band-width product (GBW) respectively over the junction device.
ARDUINO MICROCONTROLLER BASED UNDERGROUND CABLE FAULT DISTANCE LOCATORIAEME Publication
The growing concern for safety and infrastructural proliferations in the densely
populated urban and suburban areas as well as the quest to preserve the aesthetic
values in many modern localities have necessitated the need for underground
installations. The underground cabling installations are devoid of faults common to the
overhead transmission lines but are associated with certain kinds of faults such as short
circuit and open circuit faults. Locating the exact position of any of these kinds of faults
is very exhausting, costly and time-consuming because its power distribution system is
invisible. Hence, a microcontroller based underground cable fault distance locator
powered by Arduino is designed to detect and pinpoint location of faults in underground
cable lines. A basic ohm’s law is employed to achieve the variation of current with
respect to resistance that determines the position of the fault. This device has a power
supply unit, cable unit, control unit, tripping unit and display unit. The power supply
unit provides power to the other components. The cable unit consists of a three-phase
cabling system with switches between each phase to activate faults. The control unit
takes in signals from the cable unit to cause control of tripping unit and display unit.
The tripping unit then detects the phase which encounters the fault and the display unit
shows the fault characteristics on the LCD. The distance to the fault is displayed,
alongside the phase which encounters the fault for easy clearance.
Introduction to Selenium world for those who are starting journey to Selenium testing tools. This is review of available instruments. I'll share our experiences of use of Selenium tools, how we moved from IDE to Grid. As a takeaway you'll know everything you need to avoid the same errors like we did and to select your tool wisely.
Artificial intelligence (AI) is everywhere, promising self-driving cars, medical breakthroughs, and new ways of working. But how do you separate hype from reality? How can your company apply AI to solve real business problems?
Here’s what AI learnings your business should keep in mind for 2017.
Study: The Future of VR, AR and Self-Driving CarsLinkedIn
We asked LinkedIn members worldwide about their levels of interest in the latest wave of technology: whether they’re using wearables, and whether they intend to buy self-driving cars and VR headsets as they become available. We asked them too about their attitudes to technology and to the growing role of Artificial Intelligence (AI) in the devices that they use. The answers were fascinating – and in many cases, surprising.
This SlideShare explores the full results of this study, including detailed market-by-market breakdowns of intention levels for each technology – and how attitudes change with age, location and seniority level. If you’re marketing a tech brand – or planning to use VR and wearables to reach a professional audience – then these are insights you won’t want to miss.
Sub-Threshold Leakage Current Reduction Techniques In VLSI Circuits -A SurveyIJERA Editor
There is an increasing demand for portable devices powered up by battery, this led the manufacturers of
semiconductor technology to scale down the feature size which results in reduction in threshold voltage and
enables the complex functionality on a single chip. By scaling down the feature size the dynamic power
dissipation has no effect but the static power dissipation has become equal or more than that of Dynamic power
dissipation. So in recent CMOS technologies static power dissipation i.e. power dissipation due to leakage
current has become a challenging area for VLSI chip designers. In order to prolong the battery life and maintain
reliability of circuit, leakage current reduction is the primary goal. A basic overview of techniques used for
reduction of sub-threshold leakages is discussed in this paper. Based on the surveyed techniques, one would be
able to choose required and apt leakage reduction technique.
Power Gating Based Ground Bounce Noise ReductionIJERA Editor
As low power circuits are most popular the decrease in supply voltage leads to increase in leakage power with respect to the technology scaling. So for removing this kind of leakages and to provide a better power efficiency many power gating techniques are used. But the leakage due to ground connection to the active part of the circuit is very high rather than all other leakages. As it is mainly due to the back EMF of the ground connection it was called it as ground bounce noise. To reduce this noise different methodologies are designed. In this paper the design of such an efficient technique related to ground bounce noise reduction using power gating circuits and comparing the results using DSCH and Microwind low power tools. In this paper the analysis of adders such as full adders using different types of power gated circuits using low power VLSI design techniques and to present the comparison results between different power gating methods.
Low Power Design of Standard Digital Gate Design Using Novel Sleep Transisto...IJMER
In the nanometer range design technologies static power consumption is very important
issue in present peripheral devices. In the CMOS based VLSI circuits technology is scaling towards
down in respect of size and achieving higher operating speeds. We have also considered these
parameters such that we can control the leakage power. As process model design are getting smaller
the density of device increases and threshold voltage as well as oxide thickness decrease to maintain
the device performance. In this article two novel circuit techniques for reduction leakage current in
NAND and NOR inverters using novel sleepy and sleepy property are investigated. We have proposed a
design model that has significant reduction in power dissipation during inactive (standby) mode of
operation compared to classical power gating methods for these circuit techniques. The proposed
circuit techniques are applied to NAND and NOR inverters and the results are compared with earlier
inverter leakage minimization techniques. All low leakage models of inverters are designed and
simulated in Tanner Tool environment using 65 nm CMOS Technology (1volt) technologies. Average
power, Leakage power, sleep transistor
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
Static power optimization using dual sub threshold supply voltages in digital...VLSICS Design
Power dissipation in high performance systems requi
res more expensive packaging. In this situation, lo
w
power VLSI design has assumed great importance as a
n active and rapidly developing field. As the densi
ty
and operating speed of CMOS VLSI chip increases, st
atic power dissipation becomes more significant. Th
is
is due to the leakage current when the transistor i
s off this is threshold voltage dependent. This can
be
observed in the combinational and sequential circui
ts. Static power reduction techniques are achieved
by
means of operating the transistor either in Cut-off
or in Saturation region completely and avoiding th
e
clock in unnecessary circuits. In this work, “Dual
sub-threshold voltage supply” technique is used to
operate the transistor under off state or either in
on state by applying some voltage at the gate of t
he MOS
transistor. This static power reduction technique i
s to digital circuits, so that the power dissipatio
n is
reduced and the performance of the circuit is incre
ased. The designed circuits can be simulated by usi
ng
Mentor Graphics Backend Tool
A novel approach for leakage power reduction techniques in 65nm technologiesVLSICS Design
The rapid progress in semiconductor technology have led the feature sizes of transistor to be shrunk there
by evolution of Deep Sub-Micron (DSM) technology; there by the extremely complex functionality is
enabled to be integrated on a single chip. In the growing market of mobile hand-held devices used all over
the world today, the battery-powered electronic system forms the backbone. To maximize the battery life,
the tremendous computational capacity of portable devices such as notebook computers, personal
communication devices (mobile phones, pocket PCs, PDAs), hearing aids and implantable pacemakers has
to be realized with very low power requirements. Leakage power consumption is one of the major technical
problem in DSM in CMOS circuit design. A comprehensive study and analysis of various leakage power
minimization techniques have been presented in this paper a novel Leakage reduction technique is
developed in Cadence virtuoso in 65nm regim with the combination of stack with sleepy keeper approach
with Low Vth & High Vth which reduces the Average Power with respect Basic Nand Gate 29.43%, 39.88%,
Force Stack 56.98, 63.01%, sleep transistor with Low Vth & High Vth 13.90, 26.61% & 33.03%, 75.24%
with respect to sleepy Keeper 93.70, 56.01% of Average Power is saved.
A NOVEL APPROACH FOR LEAKAGE POWER REDUCTION TECHNIQUES IN 65NM TECHNOLOGIESVLSICS Design
The rapid progress in semiconductor technology have led the feature sizes of transistor to be shrunk there by evolution of Deep Sub-Micron (DSM) technology; there by the extremely complex functionality is enabled to be integrated on a single chip. In the growing market of mobile hand-held devices used all over the world today, the battery-powered electronic system forms the backbone. To maximize the battery life, the tremendous computational capacity of portable devices such as notebook computers, personal communication devices (mobile phones, pocket PCs, PDAs), hearing aids and implantable pacemakers has to be realized with very low power requirements. Leakage power consumption is one of the major technical problem in DSM in CMOS circuit design. A comprehensive study and analysis of various leakage power minimization techniques have been presented in this paper a novel Leakage reduction technique is developed in Cadence virtuoso in 65nm regim with the combination of stack with sleepy keeper approach with Low Vth & High Vth which reduces the Average Power with respect Basic Nand Gate 29.43%, 39.88%, Force Stack 56.98, 63.01%, sleep transistor with Low Vth & High Vth 13.90, 26.61% & 33.03%, 75.24% with respect to sleepy Keeper 93.70, 56.01% of Average Power is saved.
NOVEL SLEEP TRANSISTOR TECHNIQUES FOR LOW LEAKAGE POWER PERIPHERAL CIRCUITSVLSICS Design
Static power consumption is a major concern in nanometre technologies. Along with technology scaling down and higher operating speeds of CMOS VLSI circuits, the leakage power is getting enhanced. As process geometries are becoming smaller, device density increases and threshold voltage as well as oxide thickness decrease to keep pace with performance. Two novel circuit techniques for leakage current reduction in inverters with and without state retention property are presented in this work. The power dissipation during inactive (standby) mode of operation can be significantly reduced compared to traditional power gating methods by these circuit techniques. The proposed circuit techniques are applied to inverters and the results are compared with earlier inverter leakage minimization techniques. Inverter
buffer chains are designed using new state retention low leakage technique and found to be dissipating lower power with state retention. All low leakage inverters are designed and simulated in cadence design environment using 90 nm technology files. The leakage power during sleep mode is found to be better by X 63 times for novel method. The total power dissipation has also reduced by a factor of X 3.5, compared to earlier sleepy keeper technique. The state retention feature is also good compared to earlier leakage power reduction methodologies.
Design of ultra low power 8 channel analog multiplexer using dynamic threshol...VLSICS Design
The design of an ultra low voltage, low power high
speed 8 channel Analog multiplexer in 180nm CMOS
technology is presented. A modified transmission ga
te using a dynamic threshold voltage MOSFET
(DTMOS
)
is employed in the design. The design is optimized
with respect to critical requirements like short
switching time, low power dissipation, good lineari
ty and high dynamic range with an operating voltage
of
0.4V. The ON and OFF resistances achieved are 32 oh
ms and 10Mohms respectively with a switching
speed of 10MHz. The power dissipation obtained is a
round 2.65uW for a dynamic range of 1uV to 0.4V.
International Journal of Engineering Research and Applications (IJERA) is an open access online peer reviewed international journal that publishes research and review articles in the fields of Computer Science, Neural Networks, Electrical Engineering, Software Engineering, Information Technology, Mechanical Engineering, Chemical Engineering, Plastic Engineering, Food Technology, Textile Engineering, Nano Technology & science, Power Electronics, Electronics & Communication Engineering, Computational mathematics, Image processing, Civil Engineering, Structural Engineering, Environmental Engineering, VLSI Testing & Low Power VLSI Design etc.
FORCED STACK SLEEP TRANSISTOR (FORTRAN): A NEW LEAKAGE CURRENT REDUCTION APPR...VIT-AP University
Reduction in leakage current has become a significant concern in nanotechnology-based low-power, low-voltage, and high-performance VLSI applications. This research article discusses a new low-power circuit design the approach of FORTRAN (FORced stack sleep TRANsistor), which decreases the leakage power efficiency in the CMOS-based circuit outline in VLSI domain. FORTRAN approach reduces leakage current in both active as well as standby modes of operation. Furthermore, it is not time intensive when the circuit goes from active mode to standby mode and vice-versa. To validate the proposed design approach, experiments are conducted in the Tanner EDA tool of mentor graphics bundle on projected circuit designs for the full adder, a chain of 4-inverters, and 4-bit multiplier designs utilizing 180nm, 130nm, and 90nm TSMC technology node. The outcomes obtained show the result of a 95-98% vital reduction in leakage power as well as a 15-20% reduction in dynamic power with a minor increase in delay. The result outcomes are compared for accuracy with the notable design approaches that are accessible for both active and standby modes of operation.
Comparative Performance Analysis of XORXNOR Function Based High-Speed CMOS Fu...VLSICS Design
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Owing to the fact that MOSFETs can be effortlessly assimilated into ICs, they have become the heart of the
growing semiconductor industry. The need to procure low power dissipation, high operating speed and
small size requires the scaling down of these devices. This fully serves the Moore’s Law. But scaling down
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of SED based devices prove to be a better solution to device downsizing has been presented. As such the
study of Short Channel effects as well as the issues associated with a nanoMOSFET is provided. The study
of the properties of several Quantum dot materials and how to choose the best material depending on the
observation of clear Coulomb blockade is done. Specifically, a study of a graphene single electron
transistor is reviewed. Also a theoretical explanation to a model designed to tune the movement of
electrons with the help of a quantum wire has been presented.
REVIEW PAPER ON NEW TECHNOLOGY BASED NANOSCALE TRANSISTORmsejjournal
Owing to the fact that MOSFETs can be effortlessly assimilated into ICs, they have become the heart of the
growing semiconductor industry. The need to procure low power dissipation, high operating speed and
small size requires the scaling down of these devices. This fully serves the Moore’s Law. But scaling down
comes with its own drawbacks which can be substantiated as the Short Channel Effect. The working of the
device deteriorates owing to SCE. In this paper, the problems of device downsizing as well as how the use
of SED based devices prove to be a better solution to device downsizing has been presented. As such the
study of Short Channel effects as well as the issues associated with a nanoMOSFET is provided. The study
of the properties of several Quantum dot materials and how to choose the best material depending on the
observation of clear Coulomb blockade is done. Specifically, a study of a graphene single electron
transistor is reviewed. Also a theoretical explanation to a model designed to tune the movement of
electrons with the help of a quantum wire has been presented.
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The low-power consumption with less delay time has become an important issue in the recent
trends of VLSI. In these days, the low power systems with high speed are highly preferable
everywhere. Designers need to understand how low-power techniques affect performance
attributes, and have to choose a set of techniques that are consistent with these attributes .The
main objective of this paper is to describe, how to achieve low power consumption with
approximately same delay time in a single circuit. In this paper, we make circuits with CMOS
and MTCMOS techniques and check out its power and delay characteristics. The circuits
designed using MTCMOS technique gives least power consumption.
All the pre-layout simulations have been performed at 250nm technology on tanner EDA tool.
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1. Sagar Ekade et al Int. Journal of Engineering Research and Applications www.ijera.com
ISSN : 2248-9622, Vol. 4, Issue 4( Version 6), April 2014, pp.104-107
www.ijera.com 104 | P a g e
Analysis of Leakages and Leakage Reduction Methods in UDSM
CMOS VLSI Circuits.
Sagar Ekade*, Mr. Surendra Waghmare**
*(Department of E&TC Engineering, Student, G.H.R.C.E.M. Wagholi, Pune University, Pune)
** (Department of Electronics Engg. Asst. Professor, G.H.R.C.E.M., Wagholi, Pune University, Pune.)
ABSTRACT
This is the era of portable devices which need to be powered by battery. Due to scarcity of space and leakages in
chips, battery life is a serious concern. As technology advances, scaling of transistor feature size and supply
voltage has improved the performance, increased the transistor density and reduced the power required by the
chip. The maximum power consumed by the chip is the function of its technology along with its
implementation. As technology is scaling down and CMOS circuits are supplied with lower supply voltages, the
static power i.e. standby leakage current becomes very crucial. In Ultra Deep-submicron regime scaling has
reduced the threshold voltage and that has led to increase in leakage current in sub-threshold region and hence
rise in static power dissipation. This paper presents a critical analysis of leakages and leakage reduction
techniques.
Keywords – leakage current, scaling, sub-threshold region, threshold voltage, UDSM.
I. INTRODUCTION
During the 90s, VLSI designers were
focused primarily on improvising speed to work out
crucially important real-time modules such as video
alteration, games, graphics etc. This has resulted in
Integrated circuits that have combined various
complex signal processing blocks and graphics
processing units to meet the office and entertainment
requirements. While these efforts have solved the
real-time problem, they leave the problem of
increasing demand for portable operation
unaccounted, where portable devices need to carry all
this with consuming least possible power. The stern
limitation on required power in portable electronics
applications such as smart phones and tablets must be
fulfilled by the VLSI chip designers while still
keeping performance high. While wireless devices
are a new buzz in the consumer electronics market,
an important design constraint for portable operation
is power consumption of the device. The key is - to
improve life time with minimum requirements on
dimensions, battery time and weight of the batteries.
So the most central factor to consider while designing
ICs for portable devices is „low power design‟.
This paper is organised as follows: section 1
deal with introduction and need for low power
design. Section 2 deals with sources of power
dissipation in CMOS gates. Section 3 deals with low
power design. Section 4 deals with various low
power design approaches. Conclusion and future
work is given in section 5.
II. SOURCES OF POWER DISSIPATION
Power consumed by the ICs is divided as
Dynamic, Short Circuit and Static. In submicron and
later stages, static power reduction is the focus of
design. Static power corresponds to various leakages
at transistor level.
There are roughly six major leakage
currents. Reverse bias junction leakage (I1) is from
the source/drain into the substrate through the reverse
biased diodes. Gate oxide tunnelling leakage (I2) is
due to electron tunnelling from gate to substrate and
vice versa due to thin oxide. Hot carrier injection (I3)
is due to crossing of Si-SiO2 interface potential
barrier by electrons or holes. Gate Induced Drain
Leakage (I4) is due to carrier production through
avalanche multiplication and band - band tunnelling.
Channel punch through current (I5) is due to merging
of source-substrate and drain-substrate depletion
regions due to short channel. The most important of
these is Sub-threshold Leakage Current (I6). It is
given by
Isub = Io*e [V
GS
−V
TH
/nV
T
]
[1−e-V
DS
/V
T ] ---- (1)
Where Io=(μoCoxVT2e1.8(W/L)) , VT =
KT/q is the thermal voltage, VTH is the threshold
voltage, VGS is the gate to source voltage, VDS is
the drain to source voltage, W and L are the transistor
width and length respectively. Cox is the gate oxide
capacitance, μo is the carrier mobility and n is the sub
threshold swing coefficient.
RESEARCH ARTICLE OPEN ACCESS
2. Sagar Ekade et al Int. Journal of Engineering Research and Applications www.ijera.com
ISSN : 2248-9622, Vol. 4, Issue 4( Version 6), April 2014, pp.104-107
www.ijera.com 105 | P a g e
III. LOW POWER DESIGN
Low power design can be achieved at
various abstraction levels. The methods at these
abstraction levels are as given below.
At the system level, we have methods such
as Partitioning and Power down. At Algorithmic
level, we have Regularity, Complexity and
Concurrency. At the architecture level, we can imply
parallelism, data encoding, redundancy and
pipelining. At the circuit level, we can reduce power
by applying logic styles, transistor sizing and energy
recovery. And at the technology level, we have multi
threshold devices and threshold reduction for power
reduction.
IV. VARIOUS LOW POWER DESIGN
APPROACHES
There are various leakage reduction
approaches or low power design approaches have
been devised by the engineers. But each approach has
some practical advantages as well as disadvantages.
The basic parameters to be considered for the power
reduction are mainly static leakage power, area and
propagation delay. Some approaches combine two or
more techniques which are compatible with each
other to achieve more efficiency. These approaches
are critically analyzed as follows.
1. Use of stacking
This approach is based on the fact that
natural stacking of MOSFET helps in achieving less
leakage current. The leakage through two series OFF
transistor is much lower than that of single transistor
because of stack effect. One such technique
following this approach is Forced stack. In this
technique, every transistor in the network is
duplicated with both the transistors bearing half the
original transistor width. Duplicated transistors cause
a slight reverse bias between the gate and source
when both transistors are turned off. Because sub-
threshold current is exponentially dependent on gate
bias, it obtains substantial current reduction. It is a
state retention technique but has backdrops as more
dynamic power and area.
2. Use of sleep transistors
This approach uses the sleep transistor
between both VDD and the pull up network and
between GND and pull down network. The sleep
transistor turn off the circuit by cutting off the power
rails in idle mode thus can reduce leakage power
effectively. In this technique we have floating values
and thus will lose state during sleep mode. The
Wakeup time and energy of the sleep technique have
significant impact on the efficiency of the circuit. The
techniques following this approach are Sleepy
Keeper and Leakage feedback. Sleepy Keeper
uses a PMOS transistor in parallel to NMOS sleep
transistor in the pull down path and NMOS transistor
in parallel to PMOS sleep transistor in the pull up
path. The extra retention transistors are connected to
the output so that during sleep mode the logic state is
maintained, with high total power dissipation. But
this technique increases dynamic power during active
mode. This creates virtual power and ground rails in
the circuit, which affects the switching speed when
the circuit is active. The identification of the idle
regions of the circuit and the generation of the sleep
signal need additional hardware capable of predicting
the circuit states accurately, increasing the area
requirement of the circuit.
Leakage feedback technique is based on the
sleep approach. To maintain logic during sleep mode,
the leakage feedback technique uses two additional
transistors and the two transistors are driven by the
output of an inverter which is driven by output of the
circuit implemented utilizing leakage feedback.
Performance degradation and increase in area are the
limitations along with the limitation of sleep
technique.
3. Use of stacking along with sleep transistors
This approach combines the advantages of
both sleep and stacking. The technique employing
this approach is Sleepy stack. In this technique, one
sleep transistor and two half sized transistors replaces
each existing transistor. Although use of W/2 for the
width of the sleep transistor is done, changing the
sleep transistor width may provide additional
tradeoffs between delay, power and area. It also
requires additional control and monitory circuit, for
the sleep transistors.
4. Use of variable body biasing
This approach uses two parallel connected
sleep transistors in Vdd and two parallel connected
sleep transistors in GND. To reduce the leakage
current in sleep mode we ensured that the body to
source voltage of the sleep transistor is increased.
The source of one of PMOS sleep transistor is
connected to the body of other PMOS sleep transistor
for having so called body biasing effect. Similarly the
source of one of the NMOS sleep transistor is
connected to the body of other NMOS sleep
transistor for having the same effect as for PMOS
sleep transistors. So, leakage reduction in this
technique occurs in two ways. Firstly the sleep
transistors effect and secondly, the variable body
biasing effect. It is well known that PMOS transistors
are not efficient at passing GND and NMOS
transistors are not efficient at passing Vdd. But this
variable body biasing technique uses PMOS
transistor in GND and NMOS transistor in Vdd, both
3. Sagar Ekade et al Int. Journal of Engineering Research and Applications www.ijera.com
ISSN : 2248-9622, Vol. 4, Issue 4( Version 6), April 2014, pp.104-107
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are in paralleled to the sleep transistor, for maintain
exact logic state during sleep mode.
5. Use of various threshold levels
This approach is based on the fact that high
Vth transistors are slow but have less leakage and
low Vth transistors are fast but have high leakages.
So, here appropriate combination of these is used as
required. The techniques using this approach are
given here. Dual-Vth assignment is one such
technique. In this method, each cell in the standard
cell library has two types as low Vth and high Vth.
Gates with low Vth are fast but have high leakage,
whereas gates with high Vth are slow but have less
leakage. Conventional deterministic approaches for
dual-threshold assignment utilize the timing slack of
non-critical paths to assign high Vth to some or all
gates on those non-critical paths to minimize the
leakage power.
Another such technique is Multiple Vth
CMOS. An MTCMOS circuit is implemented by
inserting high Vth transistors between the power
supply voltage and the original transistors of the
circuit. The original transistors are assigned low Vth
to enhance the performance while high-Vth
transistors are used as sleep controllers. In active
mode, SL is set low and sleep control high-Vth
transistors are turned on. Their on-resistance is so
small that VSSV and VDDV can be treated as almost
being equal to the real power supply. In the standby
mode, SL is set high and sleep control high-Vth
transistors are turned off and the leakage current is
low. The large leakage current in the low-Vth
transistors is suppressed by the small leakage in the
high-Vth transistors. By utilizing the sleep control
high-Vth transistors, the requirements for high
performance in active mode and low static power
consumption in standby mode can both be satisfied.
SCCMOS technique is very much similar to
the MTCMOS but instead of a high Vth sleep
transistor, a nominal Vth sleep transistor is employed
to reduce the additional delay caused due to the
presence of increased threshold value in sleep
transistor. Variable Threshold CMOS (VTCMOS) is
a circuit design technique that has been developed to
reduce standby leakage currents in low Vdd and low
Vt applications. Rather than employing multiple
threshold voltage process options, a VTCMOS circuit
inherently uses low threshold voltage transistors, and
the substrate bias voltages of the NMOS and PMOS
transistors are generated by the variable substrate bias
control circuit.
6. Use of optimized input vectors
This approach follows the concept that sub-
threshold leakage current depends on the vectors
applied to the gate inputs because different vectors
cause different transistors to be turned off. When a
circuit is in the standby mode, one could carefully
choose an input vector and let the total leakage in the
whole circuit to be minimized model leakage current
by means of linearized pseudo- Boolean functions.
7. Use of zigzag technique
In this approach, sleep transistors are used in
a zigzag or alternate manner with Vdd and GND.
Wake-up cost can be reduced in zigzag technique but
still state destruction is a limitation. Thus, any
specific state which is needed on wakeup must be
regenerated by any means. Thus the technique may
need extra circuitry to generate a specific input
vector.
8. Use of GALEOR and LECTOR
In these two approaches, leakage control
transistors are used to create stacking effect. In the
LECTOR method two extra Leakage Control
Transistors (a P-type and an N-type) are inserted
within the gate, where the gate terminal of each
Leakage Control Transistor is controlled by the
source of the other. GALEOR technique reduces the
leakage current flowing through the CMOS logic gate
using stack effect where two drain controlled gated
transistors are used. These two techniques are very
good at leakage reduction but there is no provision of
sleep mode of operation.
9. Use of LPSR approach
The Low Power State Retention approach
makes use of a pair of NMOS and PMOS transistors
in the pull-up and pull-down paths of the CMOS
circuit. The LPSR logic gate has four modes of
operation as Active Mode, Deep Sleep Mode, State
Retention Mode 1, and State Retention Mode 0. The
LPSR approach has active mode static power less
than other sleepy techniques and the least static
power during deep sleep state and good state
retention at low power. This approach has least total
power dissipation during pulsed operation. Since only
single Vt transistors are used in all the designs to
achieve ultra low power operation, the novel
technique provides new choice to the designers of
low power VLSI circuits.
V. CONCLUSION
Out of the above mentioned approaches,
GALEOR, LECTOR and LPSR approaches are used
quiet widely in the ultra deep submicron
regime(<100nm). These approaches are very efficient
in terms of reducing static leakage power
consumption. But they also suffer some
compromises.
In future an improvement of them or
combination of these approaches with some other
4. Sagar Ekade et al Int. Journal of Engineering Research and Applications www.ijera.com
ISSN : 2248-9622, Vol. 4, Issue 4( Version 6), April 2014, pp.104-107
www.ijera.com 107 | P a g e
techniques to remove their backdrops needs to be
done. One such combination of GALEOR with sleep
and state retention elements is under study.
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