Download to read offline
More Related Content
![No[1][1]](https://cdn.slidesharecdn.com/ss_thumbnails/no11-1196304502995116-2-thumbnail.jpg?width=640&height=640&fit=bounds)
![[EWiLi2016] Towards a performance-aware power capping orchestrator for the Xe...](https://cdn.slidesharecdn.com/ss_thumbnails/xempupilewili-171206183909-thumbnail.jpg?width=640&height=640&fit=bounds)
Similar to Exploration of Radars and Software Defined Radios using VisualSim
Exploration of Radars and Software Defined Radios using VisualSim
- 1. EXPLORATION OF RADARS ANDSOFTWARE DEFINED RADIOS USING VISUALSIM Deepak Shankar Founder Mirabilis Design Inc. Email: dshankar@mirabilisdesign.com
- 2. About Mirabilis Design Softwarecompany based in Silicon Valley providing electronics design solutions Development centers in US, India, China and Czech republic Visualize, optimize and validate the system specification prior to development Customers in Aerospace, Defense, Semiconductors and Automotive VisualSim Architect- Modeling and simulation software Largest source of system modeling blocks and analysis tools Select the “Right” configuration to match customer request
- 3. What is aSystem? Market opportunity is huge because of the breath of applications
- 4. Concept of SystemAnalysis Architecture Exploration ◦ Is the process of evaluating the specification prior to development System modeling ◦ Construct virtual model to represent functionality, timing and power without the implementation code Trade-off ◦ Select right configuration and parameters to meet requirements ◦ Evaluate task mapping, power vs timing, hardware vs software, distributed vs centralized etc. Making Better Quality Products
- 5. Traditional Analysis Focus onthe quality of the algorithm
- 6. Impact of IncorrectArchitecture Analysis Impacts mechanical, thermal, electronics and software implementation Power consumption using Spreadsheet Power consumption using VisualSim
- 7. Library of ModelingComponents Graphical & Hierarchical Modeling Collaborative Engineering Tools Custom Statistics & Reports Open API for integration Timing Throughput Security Capacity Planning Power Planning Buffer Usage Resource Efficiency Failure Analysis The Way Forward using System Simulation with VisualSim Architect Software Network Electronics Analysis Embedded Systems Distributed Systems Semiconductors Eliminate all surprises prior to development Features Segment
- 8. Functional Diagram ofa Radar System
- 9. Architecture Design Challenges Whatshould be the hardware configuration for this application? Does the processing meet the timing deadline? Which tasks consume the most time and memory bandwidth? Can I modify the sequence or change the prior or create an offset that would get better performance without changing the hardware What is the power consumed by the system? Can I increase the number of sensors or handle larger data sizes? What is the individual processing and resource capacity for each task- input to the developers? What are the corner cases for additional test development?
- 10. Comparing the ArchitectureOptions
- 11. Secondary PCI Bus,64 Bit Up to 66 MHz ADSP-TS201S TigerSHARC DSP DSP #1 512MB～1024MB SDRAM 8片TSOPII54 QL5064 QuickLogic 64-bit Embedded PCI Controller ADSP-TS201S TigerSHARC DSP DSP #2 64-bit, 83.3 MHz DSP Cluster Bus 1 LINK LINK LINK LINK LINK VirtexII-Pro XILINX LINK to VirtexII-Pro RocketIO (4 Channels) to VXS P0 Boot Flash peripheral 8-bit bus QL5064 Peripheral 8-bit bus DSP1 Ints&Flags DSP2 Ints&Flags DSP3 Ints&Flags DSP4 Ints&Flags QL5064 Peripheral 8-bit bus ADSP-TS201S TigerSHARC DSP DSP #3 512MB～1024MB SDRAM 8片TSOPII54 QL5064 QuickLogic 64-bit Embedded PCI Controller ADSP-TS201S TigerSHARC DSP DSP #4 64-bit, 83.3 MHz DSP Cluster Bus 2 LINK Boot Flash peripheral 8-bit bus LINK to VirtexII-Pro LINK to VirtexII-Pro LINK to VirtexII-Pro DSP 1 LINK DSP 2 LINK DSP 3 LINK DSP 4 LINK PCI 64/66 IPcore PowerPC 405e RS232接口 RS232 串行接口 to P2 PCI 64位/66MHz PMC槽 Boot Flash Map Individual Functions to Hardware Units LDS6527- Mercury Computer TI DSP based
- 12.
- 13. VisualSim Systems-Level IP Comprehensiveimplementation-accurate Library Traffic • Distribution • Sequence • Trace file • Instruction profile Reports • Latency • Throughput • Utilization • Ave/peak power • Statistics Support • Listeners • Debuggers • Tracers • Assertions Power • Table • Energy harvesters • Battery SoC • AMBA (AHB/ APB/ AXI) • Corelink • CoreConnect • Network-on-Chip • Virtual Channel • DMA • Crossbar • Serial Switch • Bridge Board-Level • VME • PCI/PCI-X/PCIe • SPI 3.0 • Rapid IO • 1553B • FlexRay • CAN-FD • AFDX • TTEthernet • OpenVPX Processors • ARM (M-Series) • ARM (A8, A72, A53, A76) • RISC-V • Nvidia- Drive-PX • Configurable GPU, DSP, mP and mC • PowerPC • X86- Intel and AMD • DSP- TI and ADI • Others: MIPS, Tensilica, Renesas SH, Marvel RTL-like • Clock, Wire-Delay • Registers, Latches and Flip-flop • ALU and FSM • Mux, DeMux • Lookup table RTOS • Generic RTOS • ARINC 653 • AUTOSAR Stochastic • Queue • Time Queue • Quantity Queue • System Resources • Scheduling algorithms Custom Creator • Script language • 600 RegEx • Task graph • Use cases • Programming languages Storage • Flash • NVMe • Disk • Memory Controller • MPMC • Fibre Channel • Fire Wire Networking • Switched Ethernet • Resilient Packet Ring • RP3 • Wireless LAN 802.11 • Bluetooth and PAN • Spacewire • Audio-Video Bridging • IEEE802.1Q FPGA • Xilinx- Zynq, Virtex, Kintex • Intel-Stratix, Arria • Microsemi- Smartfusion • Programmable logic generator • External links to I/O, Network and Memory Memory • Memory Controller • SDR • DDR DRAM 2,3,4 • LPDDR 2, 3, 4 • HBM, HMC • QDR, RDRAM
- 14. Concept To Specification IdeaDiscussion Input your ideas Customer Requirements Build Optimize Validate Architecture Component/Device Selection Functional Partitioning Parameters/Attributes Experiment with configurations and parameters Output Validated Specification
- 15. Examples of VisualSimUsage Multiple Vendors Avionics and Flight Control ◦ Design a reconnaissance aircraft with Mercury servers, BAE interface ASICs and internal software ◦ Measure processing MIPS and networking bandwidth for different virtual channels and data input rates ◦ Reduce the battery usage and the battery size for the proposed system Designing OpenVPX and SpaceVPX ◦ Compare SpacevPX and OpenVPX for high performance computing applications ◦ Identify system bottlenecks as data rates, processing requirements and storage accesses are increased ◦ Tested the interoperability of different vendors China Aerospace Radar ◦ Validate the algorithm sequence and assignment to hardware platform for different traffic and data sizes ◦ Compare Xilinx Ultrascale MPSoC, TI DSP and Kintex ◦ Trade-off compute-intensive vs. memory-intensive
- 16. Examples of VisualSimUsage Gradual Failure ◦ Determine the longest duration of sustained basic operation for a gradual power failure ◦ Test for various power loss rates and combination of instrument activities to maximize return on investment ◦ Select the right schedule for shutting down sub-systems Hardware and Software Failure ◦ Evaluate the recovery time and continued operation using redundant boards ◦ Modify the different failure combinations ◦ Determine the best case continued operation requirements Network failure ◦ Impact of re-routing because of a link shutdown ◦ Experiment with different routing algorithms ◦ Measure the latency from Source to data center
- 17. Examples of VisualSimUsage Mission Planning ◦ Compute resource and battery requirements for different Cubesat orbits ◦ Experiment with processing and battery charge during charging and discharging periods ◦ Vary the activities in each orbit and vary the sub-systems used for each task Cybersecurity ◦ Evaluate the overhead for computing hash values for packets on Gateways ◦ Provide feedback to development teams on the available resources for each algorithm ◦ Generate documentation with anticipated parameter values to attach with the specification Software-Defined Radio ◦ Study the processing overhead of different encryption algorithms ◦ Using Analog Devices ADC and Xilinx Virtex 5 FPGA ◦ Determine ways to reduce overhead by using local BRAM for block buffering
- 18. Examples of VisualSimUsage JPL Europa Clipper ◦ Determine corner cases with wait states and termination requests that cause long delays and data loss ◦ Reuse legacy architecture with Radiation-hardened parts ◦ Determine the maximum number of sensors assignment to each board and the DMA speed JPL Nexus Project ◦ Select a standard bus topology for interfacing between boards and for the backplane ◦ Standardized on RapidIO for future projects from 12 bus families for a set of traffic profiles ◦ Developed reusable project to work on multiple projects US Air Force Processor vs FPGA ◦ Create a table of preferred parts based on battery capacity, orbital activities, sensor rates and error conditions ◦ Compared FPGAs, DSP and ARM-based processor families ◦ Established a list of criteria to select the board for each spacecraft sub-system
- 19. Example of anEmbedded System Design a new computing system Handle two types of requests generated every 1 ms and 1.5 ms respectively Each request type will trigger a different application I/O DSP CPU1 CPU2 task1 task2 task3 task4 The right system is based on the Application behavior Appl 1 1 ms 1.5 ms Appl 2
- 20. VisualSim Block Diagram Library FolderParameters Reports & Statistics Single Board Computer Architecture Application 1 Application 2 Workload
- 21. Select the Architecturebased on Reports System with faster Bus is slower in places Unpredictable System Response for Various Parameter Settings Decision Slower bus is more efficient and has a better latency profile
- 22. Failures Analysis Hardware Failure:Loss of processing cores, limited storage, reduced or loss memory device or bus overload/incorrect signals. Software failure: Resource starvation, deadlocks, data overwrite. Network failure: Network Congestion, misconfiguration, link loss and network errors. RTOS failure :Unable to achieve real-time deadlines, malicious change in schedule table, and executes beyond time slots. Power Failure: Both reduced and full power failure. Slower processing speed, limited number of resources can be executing concurrently.
- 23. Evaluating Timing Requirementsin a Multi Task-Multi Core Processor T3 Expected T3 Complete Looking at Priority of the tasks Data and processing requirements Scheduling algorithm System electronics Analysis output T1 and T2 have higher priority Preempt T3 T3 does not complete within Timing Deadline Challenges must be studied globally, ideally in the context of power, performance, and reliability
- 24. VisualSim Power Technology Modelinput is list of states, associated power and power management Power consumption over time Based on system activity and state change Multiple state change at any instance with variable duration Power management logic to change state Supports network, interface, hardware and software Power impact entities ◦ Generation- wind, solar, motor, steady, custom ◦ Storage- types of batteries ◦ Consumption- rates, devices and clocks ◦ Management- time and custom Power is an integral part of Architecture Exploration Block Power Mode Diagram Function 1 Function 2 Function N . . . Functional Portion Timing 1 Timing 2 Timing N . . . Timing and Resource Portion Block Functional and Timing Diagram
- 25. SYSTEM DESIGN ANDEXPLORATION USING VISUALSIM Deepak Shankar Founder Mirabilis Design Inc. Email: dshankar@mirabilisdesign.com
- 26. Defining Software Tasks Dividedinto four parts ◦ Task scheduling ◦ Time slices with a schedule table for the task distribution cross the slices and cores ◦ Task execution ◦ Delay for execution the task ◦ Count the number of instructions for a function * average number of cycles per instruction ◦ Task data access ◦ Read and Write ◦ Data size which will impact the cache, memory, buses, dma and switches ◦ Accessing resources ◦ Delay associated with accessing registers, semaphores, timers and watchdogs
- 27. Defining Existing orNew Processors Gather the following information from the data sheet ◦ Pipeline ◦ Instruction set with number of cycles for each instruction ◦ Cache and memory hierarchy ◦ Context switching time ◦ SIMD/MIMD/Out-of-order queues and number per cycle Connect the VisualSim blocks and update the parameters
- 28. Software Development usingGEM5 MSM7201A Qualcomm ARM11@528MHz ARM926@274(modem) LCD Sharp 3.2” TFT HVGA (320 x 480) LCD Controller Touch Screen NAND Flash (256MB) + DDR SDRAM (128MB) Samsung MCP K5E2G1GACM Wi-Fi Transceiver 802.11b/g TI WL1251B Power AMP 802.11b/g TI WL1251FE Power Management Qualcomm PM7540 Battery 35H00106-01M 1150mAh Capacitive Touch Screen Controller Synaptics 1007A Key Board Hardware Platform on VisualSim transactions CORBA GEM5 System SW Platform Application (Web, Map, Youtube, etc) ARM Java ARM ISA MMU Memory LCD KEY Touch Screen WiFi Speaker Mic Cache goldfish Cycle Counter FB
- 29. 5G Application Processing-Task Graph
- 30.
- 31. 5G Application Processing-Statistics
- 32.
- 33. Custom Processor forAI/ML Processing Innovation in Parallel Computing with Accelerators